2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/platform_data/sh_ipmmu.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
43 #include "dma-register.h"
46 #include "pm-rmobile.h"
49 static struct map_desc sh7372_io_desc[] __initdata = {
50 /* create a 1:1 entity map for 0xe6xxxxxx
51 * used by CPGA, INTC and PFC.
54 .virtual = 0xe6000000,
55 .pfn = __phys_to_pfn(0xe6000000),
57 .type = MT_DEVICE_NONSHARED
61 void __init sh7372_map_io(void)
63 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
67 static struct resource sh7372_pfc_resources[] = {
71 .flags = IORESOURCE_MEM,
76 .flags = IORESOURCE_MEM,
80 static struct platform_device sh7372_pfc_device = {
83 .resource = sh7372_pfc_resources,
84 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
87 void __init sh7372_pinmux_init(void)
89 platform_device_register(&sh7372_pfc_device);
93 #define SH7372_SCIF(scif_type, index, baseaddr, irq) \
94 static struct plat_sci_port scif##index##_platform_data = { \
96 .flags = UPF_BOOT_AUTOCONF, \
97 .scscr = SCSCR_RE | SCSCR_TE, \
100 static struct resource scif##index##_resources[] = { \
101 DEFINE_RES_MEM(baseaddr, 0x100), \
102 DEFINE_RES_IRQ(irq), \
105 static struct platform_device scif##index##_device = { \
108 .resource = scif##index##_resources, \
109 .num_resources = ARRAY_SIZE(scif##index##_resources), \
111 .platform_data = &scif##index##_platform_data, \
115 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
116 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
117 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
118 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
119 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
120 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
121 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
124 static struct sh_timer_config cmt2_platform_data = {
125 .channels_mask = 0x20,
128 static struct resource cmt2_resources[] = {
129 DEFINE_RES_MEM(0xe6130000, 0x50),
130 DEFINE_RES_IRQ(evt2irq(0x0b80)),
133 static struct platform_device cmt2_device = {
134 .name = "sh-cmt-32-fast",
137 .platform_data = &cmt2_platform_data,
139 .resource = cmt2_resources,
140 .num_resources = ARRAY_SIZE(cmt2_resources),
144 static struct sh_timer_config tmu0_platform_data = {
148 static struct resource tmu0_resources[] = {
149 DEFINE_RES_MEM(0xfff60000, 0x2c),
150 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
151 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
152 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
155 static struct platform_device tmu0_device = {
159 .platform_data = &tmu0_platform_data,
161 .resource = tmu0_resources,
162 .num_resources = ARRAY_SIZE(tmu0_resources),
166 static struct resource iic0_resources[] = {
170 .end = 0xFFF20425 - 1,
171 .flags = IORESOURCE_MEM,
174 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
175 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
176 .flags = IORESOURCE_IRQ,
180 static struct platform_device iic0_device = {
181 .name = "i2c-sh_mobile",
182 .id = 0, /* "i2c0" clock */
183 .num_resources = ARRAY_SIZE(iic0_resources),
184 .resource = iic0_resources,
187 static struct resource iic1_resources[] = {
191 .end = 0xE6C20425 - 1,
192 .flags = IORESOURCE_MEM,
195 .start = evt2irq(0x780), /* IIC1_ALI1 */
196 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
197 .flags = IORESOURCE_IRQ,
201 static struct platform_device iic1_device = {
202 .name = "i2c-sh_mobile",
203 .id = 1, /* "i2c1" clock */
204 .num_resources = ARRAY_SIZE(iic1_resources),
205 .resource = iic1_resources,
209 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
211 .slave_id = SHDMA_SLAVE_SCIF0_TX,
213 .chcr = CHCR_TX(XMIT_SZ_8BIT),
216 .slave_id = SHDMA_SLAVE_SCIF0_RX,
218 .chcr = CHCR_RX(XMIT_SZ_8BIT),
221 .slave_id = SHDMA_SLAVE_SCIF1_TX,
223 .chcr = CHCR_TX(XMIT_SZ_8BIT),
226 .slave_id = SHDMA_SLAVE_SCIF1_RX,
228 .chcr = CHCR_RX(XMIT_SZ_8BIT),
231 .slave_id = SHDMA_SLAVE_SCIF2_TX,
233 .chcr = CHCR_TX(XMIT_SZ_8BIT),
236 .slave_id = SHDMA_SLAVE_SCIF2_RX,
238 .chcr = CHCR_RX(XMIT_SZ_8BIT),
241 .slave_id = SHDMA_SLAVE_SCIF3_TX,
243 .chcr = CHCR_TX(XMIT_SZ_8BIT),
246 .slave_id = SHDMA_SLAVE_SCIF3_RX,
248 .chcr = CHCR_RX(XMIT_SZ_8BIT),
251 .slave_id = SHDMA_SLAVE_SCIF4_TX,
253 .chcr = CHCR_TX(XMIT_SZ_8BIT),
256 .slave_id = SHDMA_SLAVE_SCIF4_RX,
258 .chcr = CHCR_RX(XMIT_SZ_8BIT),
261 .slave_id = SHDMA_SLAVE_SCIF5_TX,
263 .chcr = CHCR_TX(XMIT_SZ_8BIT),
266 .slave_id = SHDMA_SLAVE_SCIF5_RX,
268 .chcr = CHCR_RX(XMIT_SZ_8BIT),
271 .slave_id = SHDMA_SLAVE_SCIF6_TX,
273 .chcr = CHCR_TX(XMIT_SZ_8BIT),
276 .slave_id = SHDMA_SLAVE_SCIF6_RX,
278 .chcr = CHCR_RX(XMIT_SZ_8BIT),
281 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
283 .chcr = CHCR_TX(XMIT_SZ_32BIT),
286 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
288 .chcr = CHCR_RX(XMIT_SZ_32BIT),
291 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
293 .chcr = CHCR_TX(XMIT_SZ_32BIT),
296 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
298 .chcr = CHCR_RX(XMIT_SZ_32BIT),
301 .slave_id = SHDMA_SLAVE_SDHI0_TX,
303 .chcr = CHCR_TX(XMIT_SZ_16BIT),
306 .slave_id = SHDMA_SLAVE_SDHI0_RX,
308 .chcr = CHCR_RX(XMIT_SZ_16BIT),
311 .slave_id = SHDMA_SLAVE_SDHI1_TX,
313 .chcr = CHCR_TX(XMIT_SZ_16BIT),
316 .slave_id = SHDMA_SLAVE_SDHI1_RX,
318 .chcr = CHCR_RX(XMIT_SZ_16BIT),
321 .slave_id = SHDMA_SLAVE_SDHI2_TX,
323 .chcr = CHCR_TX(XMIT_SZ_16BIT),
326 .slave_id = SHDMA_SLAVE_SDHI2_RX,
328 .chcr = CHCR_RX(XMIT_SZ_16BIT),
331 .slave_id = SHDMA_SLAVE_FSIA_TX,
333 .chcr = CHCR_TX(XMIT_SZ_32BIT),
336 .slave_id = SHDMA_SLAVE_FSIA_RX,
338 .chcr = CHCR_RX(XMIT_SZ_32BIT),
341 .slave_id = SHDMA_SLAVE_MMCIF_TX,
343 .chcr = CHCR_TX(XMIT_SZ_32BIT),
346 .slave_id = SHDMA_SLAVE_MMCIF_RX,
348 .chcr = CHCR_RX(XMIT_SZ_32BIT),
353 #define SH7372_CHCLR (0x220 - 0x20)
355 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
360 .chclr_offset = SH7372_CHCLR + 0,
365 .chclr_offset = SH7372_CHCLR + 0x10,
370 .chclr_offset = SH7372_CHCLR + 0x20,
375 .chclr_offset = SH7372_CHCLR + 0x30,
380 .chclr_offset = SH7372_CHCLR + 0x50,
385 .chclr_offset = SH7372_CHCLR + 0x60,
389 static struct sh_dmae_pdata dma_platform_data = {
390 .slave = sh7372_dmae_slaves,
391 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
392 .channel = sh7372_dmae_channels,
393 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
394 .ts_low_shift = TS_LOW_SHIFT,
395 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
396 .ts_high_shift = TS_HI_SHIFT,
397 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
398 .ts_shift = dma_ts_shift,
399 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
400 .dmaor_init = DMAOR_DME,
404 /* Resource order important! */
405 static struct resource sh7372_dmae0_resources[] = {
407 /* Channel registers and DMAOR */
410 .flags = IORESOURCE_MEM,
416 .flags = IORESOURCE_MEM,
420 .start = evt2irq(0x20c0),
421 .end = evt2irq(0x20c0),
422 .flags = IORESOURCE_IRQ,
425 /* IRQ for channels 0-5 */
426 .start = evt2irq(0x2000),
427 .end = evt2irq(0x20a0),
428 .flags = IORESOURCE_IRQ,
432 /* Resource order important! */
433 static struct resource sh7372_dmae1_resources[] = {
435 /* Channel registers and DMAOR */
438 .flags = IORESOURCE_MEM,
444 .flags = IORESOURCE_MEM,
448 .start = evt2irq(0x21c0),
449 .end = evt2irq(0x21c0),
450 .flags = IORESOURCE_IRQ,
453 /* IRQ for channels 0-5 */
454 .start = evt2irq(0x2100),
455 .end = evt2irq(0x21a0),
456 .flags = IORESOURCE_IRQ,
460 /* Resource order important! */
461 static struct resource sh7372_dmae2_resources[] = {
463 /* Channel registers and DMAOR */
466 .flags = IORESOURCE_MEM,
472 .flags = IORESOURCE_MEM,
476 .start = evt2irq(0x22c0),
477 .end = evt2irq(0x22c0),
478 .flags = IORESOURCE_IRQ,
481 /* IRQ for channels 0-5 */
482 .start = evt2irq(0x2200),
483 .end = evt2irq(0x22a0),
484 .flags = IORESOURCE_IRQ,
488 static struct platform_device dma0_device = {
489 .name = "sh-dma-engine",
491 .resource = sh7372_dmae0_resources,
492 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
494 .platform_data = &dma_platform_data,
498 static struct platform_device dma1_device = {
499 .name = "sh-dma-engine",
501 .resource = sh7372_dmae1_resources,
502 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
504 .platform_data = &dma_platform_data,
508 static struct platform_device dma2_device = {
509 .name = "sh-dma-engine",
511 .resource = sh7372_dmae2_resources,
512 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
514 .platform_data = &dma_platform_data,
521 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
530 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
532 .slave_id = SHDMA_SLAVE_USB0_TX,
533 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
535 .slave_id = SHDMA_SLAVE_USB0_RX,
536 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
540 static struct sh_dmae_pdata usb_dma0_platform_data = {
541 .slave = sh7372_usb_dmae0_slaves,
542 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
543 .channel = sh7372_usb_dmae_channels,
544 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
545 .ts_low_shift = USBTS_LOW_SHIFT,
546 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
547 .ts_high_shift = USBTS_HI_SHIFT,
548 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
549 .ts_shift = dma_usbts_shift,
550 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
551 .dmaor_init = DMAOR_DME,
553 .chcr_ie_bit = 1 << 5,
560 static struct resource sh7372_usb_dmae0_resources[] = {
562 /* Channel registers and DMAOR */
564 .end = 0xe68a0064 - 1,
565 .flags = IORESOURCE_MEM,
570 .end = 0xe68a0014 - 1,
571 .flags = IORESOURCE_MEM,
574 /* IRQ for channels */
575 .start = evt2irq(0x0a00),
576 .end = evt2irq(0x0a00),
577 .flags = IORESOURCE_IRQ,
581 static struct platform_device usb_dma0_device = {
582 .name = "sh-dma-engine",
584 .resource = sh7372_usb_dmae0_resources,
585 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
587 .platform_data = &usb_dma0_platform_data,
592 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
594 .slave_id = SHDMA_SLAVE_USB1_TX,
595 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
597 .slave_id = SHDMA_SLAVE_USB1_RX,
598 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
602 static struct sh_dmae_pdata usb_dma1_platform_data = {
603 .slave = sh7372_usb_dmae1_slaves,
604 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
605 .channel = sh7372_usb_dmae_channels,
606 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
607 .ts_low_shift = USBTS_LOW_SHIFT,
608 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
609 .ts_high_shift = USBTS_HI_SHIFT,
610 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
611 .ts_shift = dma_usbts_shift,
612 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
613 .dmaor_init = DMAOR_DME,
615 .chcr_ie_bit = 1 << 5,
622 static struct resource sh7372_usb_dmae1_resources[] = {
624 /* Channel registers and DMAOR */
626 .end = 0xe68c0064 - 1,
627 .flags = IORESOURCE_MEM,
632 .end = 0xe68c0014 - 1,
633 .flags = IORESOURCE_MEM,
636 /* IRQ for channels */
637 .start = evt2irq(0x1d00),
638 .end = evt2irq(0x1d00),
639 .flags = IORESOURCE_IRQ,
643 static struct platform_device usb_dma1_device = {
644 .name = "sh-dma-engine",
646 .resource = sh7372_usb_dmae1_resources,
647 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
649 .platform_data = &usb_dma1_platform_data,
654 static struct uio_info vpu_platform_data = {
657 .irq = intcs_evt2irq(0x980),
660 static struct resource vpu_resources[] = {
665 .flags = IORESOURCE_MEM,
669 static struct platform_device vpu_device = {
670 .name = "uio_pdrv_genirq",
673 .platform_data = &vpu_platform_data,
675 .resource = vpu_resources,
676 .num_resources = ARRAY_SIZE(vpu_resources),
680 static struct uio_info veu0_platform_data = {
683 .irq = intcs_evt2irq(0x700),
686 static struct resource veu0_resources[] = {
691 .flags = IORESOURCE_MEM,
695 static struct platform_device veu0_device = {
696 .name = "uio_pdrv_genirq",
699 .platform_data = &veu0_platform_data,
701 .resource = veu0_resources,
702 .num_resources = ARRAY_SIZE(veu0_resources),
706 static struct uio_info veu1_platform_data = {
709 .irq = intcs_evt2irq(0x720),
712 static struct resource veu1_resources[] = {
717 .flags = IORESOURCE_MEM,
721 static struct platform_device veu1_device = {
722 .name = "uio_pdrv_genirq",
725 .platform_data = &veu1_platform_data,
727 .resource = veu1_resources,
728 .num_resources = ARRAY_SIZE(veu1_resources),
732 static struct uio_info veu2_platform_data = {
735 .irq = intcs_evt2irq(0x740),
738 static struct resource veu2_resources[] = {
743 .flags = IORESOURCE_MEM,
747 static struct platform_device veu2_device = {
748 .name = "uio_pdrv_genirq",
751 .platform_data = &veu2_platform_data,
753 .resource = veu2_resources,
754 .num_resources = ARRAY_SIZE(veu2_resources),
758 static struct uio_info veu3_platform_data = {
761 .irq = intcs_evt2irq(0x760),
764 static struct resource veu3_resources[] = {
769 .flags = IORESOURCE_MEM,
773 static struct platform_device veu3_device = {
774 .name = "uio_pdrv_genirq",
777 .platform_data = &veu3_platform_data,
779 .resource = veu3_resources,
780 .num_resources = ARRAY_SIZE(veu3_resources),
784 static struct uio_info jpu_platform_data = {
787 .irq = intcs_evt2irq(0x560),
790 static struct resource jpu_resources[] = {
795 .flags = IORESOURCE_MEM,
799 static struct platform_device jpu_device = {
800 .name = "uio_pdrv_genirq",
803 .platform_data = &jpu_platform_data,
805 .resource = jpu_resources,
806 .num_resources = ARRAY_SIZE(jpu_resources),
810 static struct uio_info spu0_platform_data = {
813 .irq = evt2irq(0x1800),
816 static struct resource spu0_resources[] = {
821 .flags = IORESOURCE_MEM,
825 static struct platform_device spu0_device = {
826 .name = "uio_pdrv_genirq",
829 .platform_data = &spu0_platform_data,
831 .resource = spu0_resources,
832 .num_resources = ARRAY_SIZE(spu0_resources),
836 static struct uio_info spu1_platform_data = {
839 .irq = evt2irq(0x1820),
842 static struct resource spu1_resources[] = {
847 .flags = IORESOURCE_MEM,
851 static struct platform_device spu1_device = {
852 .name = "uio_pdrv_genirq",
855 .platform_data = &spu1_platform_data,
857 .resource = spu1_resources,
858 .num_resources = ARRAY_SIZE(spu1_resources),
861 /* IPMMUI (an IPMMU module for ICB/LMB) */
862 static struct resource ipmmu_resources[] = {
867 .flags = IORESOURCE_MEM,
871 static const char * const ipmmu_dev_names[] = {
872 "sh_mobile_lcdc_fb.0",
873 "sh_mobile_lcdc_fb.1",
883 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
884 .dev_names = ipmmu_dev_names,
885 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
888 static struct platform_device ipmmu_device = {
892 .platform_data = &ipmmu_platform_data,
894 .resource = ipmmu_resources,
895 .num_resources = ARRAY_SIZE(ipmmu_resources),
898 static struct platform_device *sh7372_early_devices[] __initdata = {
911 static struct platform_device *sh7372_late_devices[] __initdata = {
929 void __init sh7372_add_standard_devices(void)
931 static struct pm_domain_device domain_devices[] __initdata = {
932 { "A3RV", &vpu_device, },
933 { "A4MP", &spu0_device, },
934 { "A4MP", &spu1_device, },
935 { "A3SP", &scif0_device, },
936 { "A3SP", &scif1_device, },
937 { "A3SP", &scif2_device, },
938 { "A3SP", &scif3_device, },
939 { "A3SP", &scif4_device, },
940 { "A3SP", &scif5_device, },
941 { "A3SP", &scif6_device, },
942 { "A3SP", &iic1_device, },
943 { "A3SP", &dma0_device, },
944 { "A3SP", &dma1_device, },
945 { "A3SP", &dma2_device, },
946 { "A3SP", &usb_dma0_device, },
947 { "A3SP", &usb_dma1_device, },
948 { "A4R", &iic0_device, },
949 { "A4R", &veu0_device, },
950 { "A4R", &veu1_device, },
951 { "A4R", &veu2_device, },
952 { "A4R", &veu3_device, },
953 { "A4R", &jpu_device, },
954 { "A4R", &tmu0_device, },
957 sh7372_init_pm_domains();
959 platform_add_devices(sh7372_early_devices,
960 ARRAY_SIZE(sh7372_early_devices));
962 platform_add_devices(sh7372_late_devices,
963 ARRAY_SIZE(sh7372_late_devices));
965 rmobile_add_devices_to_domains(domain_devices,
966 ARRAY_SIZE(domain_devices));
969 void __init sh7372_earlytimer_init(void)
972 shmobile_earlytimer_init();
975 void __init sh7372_add_early_devices(void)
977 early_platform_add_devices(sh7372_early_devices,
978 ARRAY_SIZE(sh7372_early_devices));
980 /* setup early console here as well */
981 shmobile_setup_console();
986 void __init sh7372_add_early_devices_dt(void)
988 shmobile_init_delay();
990 sh7372_add_early_devices();
993 void __init sh7372_add_standard_devices_dt(void)
995 /* clocks are setup late during boot in the case of DT */
998 platform_add_devices(sh7372_early_devices,
999 ARRAY_SIZE(sh7372_early_devices));
1001 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1004 static const char *sh7372_boards_compat_dt[] __initdata = {
1009 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1010 .map_io = sh7372_map_io,
1011 .init_early = sh7372_add_early_devices_dt,
1012 .init_irq = sh7372_init_irq,
1013 .handle_irq = shmobile_handle_irq_intc,
1014 .init_machine = sh7372_add_standard_devices_dt,
1015 .init_late = shmobile_init_late,
1016 .dt_compat = sh7372_boards_compat_dt,
1019 #endif /* CONFIG_USE_OF */