2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <mach/dma-register.h>
37 #include <mach/hardware.h>
38 #include <mach/irqs.h>
39 #include <mach/sh7372.h>
40 #include <mach/common.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
46 static struct map_desc sh7372_io_desc[] __initdata = {
47 /* create a 1:1 entity map for 0xe6xxxxxx
48 * used by CPGA, INTC and PFC.
51 .virtual = 0xe6000000,
52 .pfn = __phys_to_pfn(0xe6000000),
54 .type = MT_DEVICE_NONSHARED
58 void __init sh7372_map_io(void)
60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
63 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
64 * enough to allocate the frame buffer memory.
66 init_consistent_dma_size(12 << 20);
70 static struct plat_sci_port scif0_platform_data = {
71 .mapbase = 0xe6c40000,
72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE,
74 .scbrr_algo_id = SCBRR_ALGO_4,
76 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
77 evt2irq(0x0c00), evt2irq(0x0c00) },
80 static struct platform_device scif0_device = {
84 .platform_data = &scif0_platform_data,
89 static struct plat_sci_port scif1_platform_data = {
90 .mapbase = 0xe6c50000,
91 .flags = UPF_BOOT_AUTOCONF,
92 .scscr = SCSCR_RE | SCSCR_TE,
93 .scbrr_algo_id = SCBRR_ALGO_4,
95 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
96 evt2irq(0x0c20), evt2irq(0x0c20) },
99 static struct platform_device scif1_device = {
103 .platform_data = &scif1_platform_data,
108 static struct plat_sci_port scif2_platform_data = {
109 .mapbase = 0xe6c60000,
110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE,
112 .scbrr_algo_id = SCBRR_ALGO_4,
114 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
115 evt2irq(0x0c40), evt2irq(0x0c40) },
118 static struct platform_device scif2_device = {
122 .platform_data = &scif2_platform_data,
127 static struct plat_sci_port scif3_platform_data = {
128 .mapbase = 0xe6c70000,
129 .flags = UPF_BOOT_AUTOCONF,
130 .scscr = SCSCR_RE | SCSCR_TE,
131 .scbrr_algo_id = SCBRR_ALGO_4,
133 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
134 evt2irq(0x0c60), evt2irq(0x0c60) },
137 static struct platform_device scif3_device = {
141 .platform_data = &scif3_platform_data,
146 static struct plat_sci_port scif4_platform_data = {
147 .mapbase = 0xe6c80000,
148 .flags = UPF_BOOT_AUTOCONF,
149 .scscr = SCSCR_RE | SCSCR_TE,
150 .scbrr_algo_id = SCBRR_ALGO_4,
152 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
153 evt2irq(0x0d20), evt2irq(0x0d20) },
156 static struct platform_device scif4_device = {
160 .platform_data = &scif4_platform_data,
165 static struct plat_sci_port scif5_platform_data = {
166 .mapbase = 0xe6cb0000,
167 .flags = UPF_BOOT_AUTOCONF,
168 .scscr = SCSCR_RE | SCSCR_TE,
169 .scbrr_algo_id = SCBRR_ALGO_4,
171 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
172 evt2irq(0x0d40), evt2irq(0x0d40) },
175 static struct platform_device scif5_device = {
179 .platform_data = &scif5_platform_data,
184 static struct plat_sci_port scif6_platform_data = {
185 .mapbase = 0xe6c30000,
186 .flags = UPF_BOOT_AUTOCONF,
187 .scscr = SCSCR_RE | SCSCR_TE,
188 .scbrr_algo_id = SCBRR_ALGO_4,
190 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
191 evt2irq(0x0d60), evt2irq(0x0d60) },
194 static struct platform_device scif6_device = {
198 .platform_data = &scif6_platform_data,
203 static struct sh_timer_config cmt2_platform_data = {
205 .channel_offset = 0x40,
207 .clockevent_rating = 125,
208 .clocksource_rating = 125,
211 static struct resource cmt2_resources[] = {
216 .flags = IORESOURCE_MEM,
219 .start = evt2irq(0x0b80), /* CMT2 */
220 .flags = IORESOURCE_IRQ,
224 static struct platform_device cmt2_device = {
228 .platform_data = &cmt2_platform_data,
230 .resource = cmt2_resources,
231 .num_resources = ARRAY_SIZE(cmt2_resources),
235 static struct sh_timer_config tmu00_platform_data = {
237 .channel_offset = 0x4,
239 .clockevent_rating = 200,
242 static struct resource tmu00_resources[] = {
247 .flags = IORESOURCE_MEM,
250 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
251 .flags = IORESOURCE_IRQ,
255 static struct platform_device tmu00_device = {
259 .platform_data = &tmu00_platform_data,
261 .resource = tmu00_resources,
262 .num_resources = ARRAY_SIZE(tmu00_resources),
265 static struct sh_timer_config tmu01_platform_data = {
267 .channel_offset = 0x10,
269 .clocksource_rating = 200,
272 static struct resource tmu01_resources[] = {
277 .flags = IORESOURCE_MEM,
280 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
281 .flags = IORESOURCE_IRQ,
285 static struct platform_device tmu01_device = {
289 .platform_data = &tmu01_platform_data,
291 .resource = tmu01_resources,
292 .num_resources = ARRAY_SIZE(tmu01_resources),
296 static struct resource iic0_resources[] = {
300 .end = 0xFFF20425 - 1,
301 .flags = IORESOURCE_MEM,
304 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
305 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
306 .flags = IORESOURCE_IRQ,
310 static struct platform_device iic0_device = {
311 .name = "i2c-sh_mobile",
312 .id = 0, /* "i2c0" clock */
313 .num_resources = ARRAY_SIZE(iic0_resources),
314 .resource = iic0_resources,
317 static struct resource iic1_resources[] = {
321 .end = 0xE6C20425 - 1,
322 .flags = IORESOURCE_MEM,
325 .start = evt2irq(0x780), /* IIC1_ALI1 */
326 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
327 .flags = IORESOURCE_IRQ,
331 static struct platform_device iic1_device = {
332 .name = "i2c-sh_mobile",
333 .id = 1, /* "i2c1" clock */
334 .num_resources = ARRAY_SIZE(iic1_resources),
335 .resource = iic1_resources,
339 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
341 .slave_id = SHDMA_SLAVE_SCIF0_TX,
343 .chcr = CHCR_TX(XMIT_SZ_8BIT),
346 .slave_id = SHDMA_SLAVE_SCIF0_RX,
348 .chcr = CHCR_RX(XMIT_SZ_8BIT),
351 .slave_id = SHDMA_SLAVE_SCIF1_TX,
353 .chcr = CHCR_TX(XMIT_SZ_8BIT),
356 .slave_id = SHDMA_SLAVE_SCIF1_RX,
358 .chcr = CHCR_RX(XMIT_SZ_8BIT),
361 .slave_id = SHDMA_SLAVE_SCIF2_TX,
363 .chcr = CHCR_TX(XMIT_SZ_8BIT),
366 .slave_id = SHDMA_SLAVE_SCIF2_RX,
368 .chcr = CHCR_RX(XMIT_SZ_8BIT),
371 .slave_id = SHDMA_SLAVE_SCIF3_TX,
373 .chcr = CHCR_TX(XMIT_SZ_8BIT),
376 .slave_id = SHDMA_SLAVE_SCIF3_RX,
378 .chcr = CHCR_RX(XMIT_SZ_8BIT),
381 .slave_id = SHDMA_SLAVE_SCIF4_TX,
383 .chcr = CHCR_TX(XMIT_SZ_8BIT),
386 .slave_id = SHDMA_SLAVE_SCIF4_RX,
388 .chcr = CHCR_RX(XMIT_SZ_8BIT),
391 .slave_id = SHDMA_SLAVE_SCIF5_TX,
393 .chcr = CHCR_TX(XMIT_SZ_8BIT),
396 .slave_id = SHDMA_SLAVE_SCIF5_RX,
398 .chcr = CHCR_RX(XMIT_SZ_8BIT),
401 .slave_id = SHDMA_SLAVE_SCIF6_TX,
403 .chcr = CHCR_TX(XMIT_SZ_8BIT),
406 .slave_id = SHDMA_SLAVE_SCIF6_RX,
408 .chcr = CHCR_RX(XMIT_SZ_8BIT),
411 .slave_id = SHDMA_SLAVE_SDHI0_TX,
413 .chcr = CHCR_TX(XMIT_SZ_16BIT),
416 .slave_id = SHDMA_SLAVE_SDHI0_RX,
418 .chcr = CHCR_RX(XMIT_SZ_16BIT),
421 .slave_id = SHDMA_SLAVE_SDHI1_TX,
423 .chcr = CHCR_TX(XMIT_SZ_16BIT),
426 .slave_id = SHDMA_SLAVE_SDHI1_RX,
428 .chcr = CHCR_RX(XMIT_SZ_16BIT),
431 .slave_id = SHDMA_SLAVE_SDHI2_TX,
433 .chcr = CHCR_TX(XMIT_SZ_16BIT),
436 .slave_id = SHDMA_SLAVE_SDHI2_RX,
438 .chcr = CHCR_RX(XMIT_SZ_16BIT),
441 .slave_id = SHDMA_SLAVE_FSIA_TX,
443 .chcr = CHCR_TX(XMIT_SZ_32BIT),
446 .slave_id = SHDMA_SLAVE_FSIA_RX,
448 .chcr = CHCR_RX(XMIT_SZ_32BIT),
451 .slave_id = SHDMA_SLAVE_MMCIF_TX,
453 .chcr = CHCR_TX(XMIT_SZ_32BIT),
456 .slave_id = SHDMA_SLAVE_MMCIF_RX,
458 .chcr = CHCR_RX(XMIT_SZ_32BIT),
463 #define SH7372_CHCLR (0x220 - 0x20)
465 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
470 .chclr_offset = SH7372_CHCLR + 0,
475 .chclr_offset = SH7372_CHCLR + 0x10,
480 .chclr_offset = SH7372_CHCLR + 0x20,
485 .chclr_offset = SH7372_CHCLR + 0x30,
490 .chclr_offset = SH7372_CHCLR + 0x50,
495 .chclr_offset = SH7372_CHCLR + 0x60,
499 static struct sh_dmae_pdata dma_platform_data = {
500 .slave = sh7372_dmae_slaves,
501 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
502 .channel = sh7372_dmae_channels,
503 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
504 .ts_low_shift = TS_LOW_SHIFT,
505 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
506 .ts_high_shift = TS_HI_SHIFT,
507 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
508 .ts_shift = dma_ts_shift,
509 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
510 .dmaor_init = DMAOR_DME,
514 /* Resource order important! */
515 static struct resource sh7372_dmae0_resources[] = {
517 /* Channel registers and DMAOR */
520 .flags = IORESOURCE_MEM,
526 .flags = IORESOURCE_MEM,
530 .start = evt2irq(0x20c0),
531 .end = evt2irq(0x20c0),
532 .flags = IORESOURCE_IRQ,
535 /* IRQ for channels 0-5 */
536 .start = evt2irq(0x2000),
537 .end = evt2irq(0x20a0),
538 .flags = IORESOURCE_IRQ,
542 /* Resource order important! */
543 static struct resource sh7372_dmae1_resources[] = {
545 /* Channel registers and DMAOR */
548 .flags = IORESOURCE_MEM,
554 .flags = IORESOURCE_MEM,
558 .start = evt2irq(0x21c0),
559 .end = evt2irq(0x21c0),
560 .flags = IORESOURCE_IRQ,
563 /* IRQ for channels 0-5 */
564 .start = evt2irq(0x2100),
565 .end = evt2irq(0x21a0),
566 .flags = IORESOURCE_IRQ,
570 /* Resource order important! */
571 static struct resource sh7372_dmae2_resources[] = {
573 /* Channel registers and DMAOR */
576 .flags = IORESOURCE_MEM,
582 .flags = IORESOURCE_MEM,
586 .start = evt2irq(0x22c0),
587 .end = evt2irq(0x22c0),
588 .flags = IORESOURCE_IRQ,
591 /* IRQ for channels 0-5 */
592 .start = evt2irq(0x2200),
593 .end = evt2irq(0x22a0),
594 .flags = IORESOURCE_IRQ,
598 static struct platform_device dma0_device = {
599 .name = "sh-dma-engine",
601 .resource = sh7372_dmae0_resources,
602 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
604 .platform_data = &dma_platform_data,
608 static struct platform_device dma1_device = {
609 .name = "sh-dma-engine",
611 .resource = sh7372_dmae1_resources,
612 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
614 .platform_data = &dma_platform_data,
618 static struct platform_device dma2_device = {
619 .name = "sh-dma-engine",
621 .resource = sh7372_dmae2_resources,
622 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
624 .platform_data = &dma_platform_data,
631 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
640 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
642 .slave_id = SHDMA_SLAVE_USB0_TX,
643 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
645 .slave_id = SHDMA_SLAVE_USB0_RX,
646 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
650 static struct sh_dmae_pdata usb_dma0_platform_data = {
651 .slave = sh7372_usb_dmae0_slaves,
652 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
653 .channel = sh7372_usb_dmae_channels,
654 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
655 .ts_low_shift = USBTS_LOW_SHIFT,
656 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
657 .ts_high_shift = USBTS_HI_SHIFT,
658 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
659 .ts_shift = dma_usbts_shift,
660 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
661 .dmaor_init = DMAOR_DME,
663 .chcr_ie_bit = 1 << 5,
670 static struct resource sh7372_usb_dmae0_resources[] = {
672 /* Channel registers and DMAOR */
674 .end = 0xe68a0064 - 1,
675 .flags = IORESOURCE_MEM,
680 .end = 0xe68a0014 - 1,
681 .flags = IORESOURCE_MEM,
684 /* IRQ for channels */
685 .start = evt2irq(0x0a00),
686 .end = evt2irq(0x0a00),
687 .flags = IORESOURCE_IRQ,
691 static struct platform_device usb_dma0_device = {
692 .name = "sh-dma-engine",
694 .resource = sh7372_usb_dmae0_resources,
695 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
697 .platform_data = &usb_dma0_platform_data,
702 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
704 .slave_id = SHDMA_SLAVE_USB1_TX,
705 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
707 .slave_id = SHDMA_SLAVE_USB1_RX,
708 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
712 static struct sh_dmae_pdata usb_dma1_platform_data = {
713 .slave = sh7372_usb_dmae1_slaves,
714 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
715 .channel = sh7372_usb_dmae_channels,
716 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
717 .ts_low_shift = USBTS_LOW_SHIFT,
718 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
719 .ts_high_shift = USBTS_HI_SHIFT,
720 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
721 .ts_shift = dma_usbts_shift,
722 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
723 .dmaor_init = DMAOR_DME,
725 .chcr_ie_bit = 1 << 5,
732 static struct resource sh7372_usb_dmae1_resources[] = {
734 /* Channel registers and DMAOR */
736 .end = 0xe68c0064 - 1,
737 .flags = IORESOURCE_MEM,
742 .end = 0xe68c0014 - 1,
743 .flags = IORESOURCE_MEM,
746 /* IRQ for channels */
747 .start = evt2irq(0x1d00),
748 .end = evt2irq(0x1d00),
749 .flags = IORESOURCE_IRQ,
753 static struct platform_device usb_dma1_device = {
754 .name = "sh-dma-engine",
756 .resource = sh7372_usb_dmae1_resources,
757 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
759 .platform_data = &usb_dma1_platform_data,
764 static struct uio_info vpu_platform_data = {
767 .irq = intcs_evt2irq(0x980),
770 static struct resource vpu_resources[] = {
775 .flags = IORESOURCE_MEM,
779 static struct platform_device vpu_device = {
780 .name = "uio_pdrv_genirq",
783 .platform_data = &vpu_platform_data,
785 .resource = vpu_resources,
786 .num_resources = ARRAY_SIZE(vpu_resources),
790 static struct uio_info veu0_platform_data = {
793 .irq = intcs_evt2irq(0x700),
796 static struct resource veu0_resources[] = {
801 .flags = IORESOURCE_MEM,
805 static struct platform_device veu0_device = {
806 .name = "uio_pdrv_genirq",
809 .platform_data = &veu0_platform_data,
811 .resource = veu0_resources,
812 .num_resources = ARRAY_SIZE(veu0_resources),
816 static struct uio_info veu1_platform_data = {
819 .irq = intcs_evt2irq(0x720),
822 static struct resource veu1_resources[] = {
827 .flags = IORESOURCE_MEM,
831 static struct platform_device veu1_device = {
832 .name = "uio_pdrv_genirq",
835 .platform_data = &veu1_platform_data,
837 .resource = veu1_resources,
838 .num_resources = ARRAY_SIZE(veu1_resources),
842 static struct uio_info veu2_platform_data = {
845 .irq = intcs_evt2irq(0x740),
848 static struct resource veu2_resources[] = {
853 .flags = IORESOURCE_MEM,
857 static struct platform_device veu2_device = {
858 .name = "uio_pdrv_genirq",
861 .platform_data = &veu2_platform_data,
863 .resource = veu2_resources,
864 .num_resources = ARRAY_SIZE(veu2_resources),
868 static struct uio_info veu3_platform_data = {
871 .irq = intcs_evt2irq(0x760),
874 static struct resource veu3_resources[] = {
879 .flags = IORESOURCE_MEM,
883 static struct platform_device veu3_device = {
884 .name = "uio_pdrv_genirq",
887 .platform_data = &veu3_platform_data,
889 .resource = veu3_resources,
890 .num_resources = ARRAY_SIZE(veu3_resources),
894 static struct uio_info jpu_platform_data = {
897 .irq = intcs_evt2irq(0x560),
900 static struct resource jpu_resources[] = {
905 .flags = IORESOURCE_MEM,
909 static struct platform_device jpu_device = {
910 .name = "uio_pdrv_genirq",
913 .platform_data = &jpu_platform_data,
915 .resource = jpu_resources,
916 .num_resources = ARRAY_SIZE(jpu_resources),
920 static struct uio_info spu0_platform_data = {
923 .irq = evt2irq(0x1800),
926 static struct resource spu0_resources[] = {
931 .flags = IORESOURCE_MEM,
935 static struct platform_device spu0_device = {
936 .name = "uio_pdrv_genirq",
939 .platform_data = &spu0_platform_data,
941 .resource = spu0_resources,
942 .num_resources = ARRAY_SIZE(spu0_resources),
946 static struct uio_info spu1_platform_data = {
949 .irq = evt2irq(0x1820),
952 static struct resource spu1_resources[] = {
957 .flags = IORESOURCE_MEM,
961 static struct platform_device spu1_device = {
962 .name = "uio_pdrv_genirq",
965 .platform_data = &spu1_platform_data,
967 .resource = spu1_resources,
968 .num_resources = ARRAY_SIZE(spu1_resources),
971 static struct platform_device *sh7372_early_devices[] __initdata = {
984 static struct platform_device *sh7372_late_devices[] __initdata = {
1002 void __init sh7372_add_standard_devices(void)
1004 rmobile_init_pm_domain(&sh7372_pd_a4lc);
1005 rmobile_init_pm_domain(&sh7372_pd_a4mp);
1006 rmobile_init_pm_domain(&sh7372_pd_d4);
1007 rmobile_init_pm_domain(&sh7372_pd_a4r);
1008 rmobile_init_pm_domain(&sh7372_pd_a3rv);
1009 rmobile_init_pm_domain(&sh7372_pd_a3ri);
1010 rmobile_init_pm_domain(&sh7372_pd_a4s);
1011 rmobile_init_pm_domain(&sh7372_pd_a3sp);
1012 rmobile_init_pm_domain(&sh7372_pd_a3sg);
1014 rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv);
1015 rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc);
1017 rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg);
1018 rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp);
1020 platform_add_devices(sh7372_early_devices,
1021 ARRAY_SIZE(sh7372_early_devices));
1023 platform_add_devices(sh7372_late_devices,
1024 ARRAY_SIZE(sh7372_late_devices));
1026 rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device);
1027 rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device);
1028 rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device);
1029 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device);
1030 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device);
1031 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device);
1032 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device);
1033 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device);
1034 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device);
1035 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device);
1036 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device);
1037 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device);
1038 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device);
1039 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device);
1040 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device);
1041 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device);
1042 rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device);
1043 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device);
1044 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device);
1045 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device);
1046 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device);
1047 rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device);
1048 rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device);
1049 rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device);
1052 static void __init sh7372_earlytimer_init(void)
1054 sh7372_clock_init();
1055 shmobile_earlytimer_init();
1058 void __init sh7372_add_early_devices(void)
1060 early_platform_add_devices(sh7372_early_devices,
1061 ARRAY_SIZE(sh7372_early_devices));
1063 /* setup early console here as well */
1064 shmobile_setup_console();
1066 /* override timer setup with soc-specific code */
1067 shmobile_timer.init = sh7372_earlytimer_init;
1070 #ifdef CONFIG_USE_OF
1072 void __init sh7372_add_early_devices_dt(void)
1074 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1076 early_platform_add_devices(sh7372_early_devices,
1077 ARRAY_SIZE(sh7372_early_devices));
1079 /* setup early console here as well */
1080 shmobile_setup_console();
1083 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1087 void __init sh7372_add_standard_devices_dt(void)
1089 /* clocks are setup late during boot in the case of DT */
1090 sh7372_clock_init();
1092 platform_add_devices(sh7372_early_devices,
1093 ARRAY_SIZE(sh7372_early_devices));
1095 of_platform_populate(NULL, of_default_bus_match_table,
1096 sh7372_auxdata_lookup, NULL);
1099 static const char *sh7372_boards_compat_dt[] __initdata = {
1104 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1105 .map_io = sh7372_map_io,
1106 .init_early = sh7372_add_early_devices_dt,
1107 .nr_irqs = NR_IRQS_LEGACY,
1108 .init_irq = sh7372_init_irq,
1109 .handle_irq = shmobile_handle_irq_intc,
1110 .init_machine = sh7372_add_standard_devices_dt,
1111 .timer = &shmobile_timer,
1112 .dt_compat = sh7372_boards_compat_dt,
1115 #endif /* CONFIG_USE_OF */