2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_data/sh_ipmmu.h>
37 #include <mach/dma-register.h>
38 #include <mach/irqs.h>
39 #include <mach/sh7372.h>
40 #include <mach/common.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
46 static struct map_desc sh7372_io_desc[] __initdata = {
47 /* create a 1:1 entity map for 0xe6xxxxxx
48 * used by CPGA, INTC and PFC.
51 .virtual = 0xe6000000,
52 .pfn = __phys_to_pfn(0xe6000000),
54 .type = MT_DEVICE_NONSHARED
58 void __init sh7372_map_io(void)
60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
64 static struct resource sh7372_pfc_resources[] = {
68 .flags = IORESOURCE_MEM,
73 .flags = IORESOURCE_MEM,
77 static struct platform_device sh7372_pfc_device = {
80 .resource = sh7372_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
84 void __init sh7372_pinmux_init(void)
86 platform_device_register(&sh7372_pfc_device);
90 #define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91 static struct plat_sci_port scif##index##_platform_data = { \
93 .flags = UPF_BOOT_AUTOCONF, \
94 .scscr = SCSCR_RE | SCSCR_TE, \
97 static struct resource scif##index##_resources[] = { \
98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 DEFINE_RES_IRQ(irq), \
102 static struct platform_device scif##index##_device = { \
105 .resource = scif##index##_resources, \
106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
108 .platform_data = &scif##index##_platform_data, \
112 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
113 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
114 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
115 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
116 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
117 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
118 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
121 static struct sh_timer_config cmt2_platform_data = {
122 .channels_mask = 0x20,
125 static struct resource cmt2_resources[] = {
126 DEFINE_RES_MEM(0xe6130000, 0x50),
127 DEFINE_RES_IRQ(evt2irq(0x0b80)),
130 static struct platform_device cmt2_device = {
131 .name = "sh-cmt-32-fast",
134 .platform_data = &cmt2_platform_data,
136 .resource = cmt2_resources,
137 .num_resources = ARRAY_SIZE(cmt2_resources),
141 static struct sh_timer_config tmu0_platform_data = {
145 static struct resource tmu0_resources[] = {
146 DEFINE_RES_MEM(0xfff60000, 0x2c),
147 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
148 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
149 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
152 static struct platform_device tmu0_device = {
156 .platform_data = &tmu0_platform_data,
158 .resource = tmu0_resources,
159 .num_resources = ARRAY_SIZE(tmu0_resources),
163 static struct resource iic0_resources[] = {
167 .end = 0xFFF20425 - 1,
168 .flags = IORESOURCE_MEM,
171 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
172 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
173 .flags = IORESOURCE_IRQ,
177 static struct platform_device iic0_device = {
178 .name = "i2c-sh_mobile",
179 .id = 0, /* "i2c0" clock */
180 .num_resources = ARRAY_SIZE(iic0_resources),
181 .resource = iic0_resources,
184 static struct resource iic1_resources[] = {
188 .end = 0xE6C20425 - 1,
189 .flags = IORESOURCE_MEM,
192 .start = evt2irq(0x780), /* IIC1_ALI1 */
193 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
194 .flags = IORESOURCE_IRQ,
198 static struct platform_device iic1_device = {
199 .name = "i2c-sh_mobile",
200 .id = 1, /* "i2c1" clock */
201 .num_resources = ARRAY_SIZE(iic1_resources),
202 .resource = iic1_resources,
206 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
208 .slave_id = SHDMA_SLAVE_SCIF0_TX,
210 .chcr = CHCR_TX(XMIT_SZ_8BIT),
213 .slave_id = SHDMA_SLAVE_SCIF0_RX,
215 .chcr = CHCR_RX(XMIT_SZ_8BIT),
218 .slave_id = SHDMA_SLAVE_SCIF1_TX,
220 .chcr = CHCR_TX(XMIT_SZ_8BIT),
223 .slave_id = SHDMA_SLAVE_SCIF1_RX,
225 .chcr = CHCR_RX(XMIT_SZ_8BIT),
228 .slave_id = SHDMA_SLAVE_SCIF2_TX,
230 .chcr = CHCR_TX(XMIT_SZ_8BIT),
233 .slave_id = SHDMA_SLAVE_SCIF2_RX,
235 .chcr = CHCR_RX(XMIT_SZ_8BIT),
238 .slave_id = SHDMA_SLAVE_SCIF3_TX,
240 .chcr = CHCR_TX(XMIT_SZ_8BIT),
243 .slave_id = SHDMA_SLAVE_SCIF3_RX,
245 .chcr = CHCR_RX(XMIT_SZ_8BIT),
248 .slave_id = SHDMA_SLAVE_SCIF4_TX,
250 .chcr = CHCR_TX(XMIT_SZ_8BIT),
253 .slave_id = SHDMA_SLAVE_SCIF4_RX,
255 .chcr = CHCR_RX(XMIT_SZ_8BIT),
258 .slave_id = SHDMA_SLAVE_SCIF5_TX,
260 .chcr = CHCR_TX(XMIT_SZ_8BIT),
263 .slave_id = SHDMA_SLAVE_SCIF5_RX,
265 .chcr = CHCR_RX(XMIT_SZ_8BIT),
268 .slave_id = SHDMA_SLAVE_SCIF6_TX,
270 .chcr = CHCR_TX(XMIT_SZ_8BIT),
273 .slave_id = SHDMA_SLAVE_SCIF6_RX,
275 .chcr = CHCR_RX(XMIT_SZ_8BIT),
278 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
280 .chcr = CHCR_TX(XMIT_SZ_32BIT),
283 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
285 .chcr = CHCR_RX(XMIT_SZ_32BIT),
288 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
290 .chcr = CHCR_TX(XMIT_SZ_32BIT),
293 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
295 .chcr = CHCR_RX(XMIT_SZ_32BIT),
298 .slave_id = SHDMA_SLAVE_SDHI0_TX,
300 .chcr = CHCR_TX(XMIT_SZ_16BIT),
303 .slave_id = SHDMA_SLAVE_SDHI0_RX,
305 .chcr = CHCR_RX(XMIT_SZ_16BIT),
308 .slave_id = SHDMA_SLAVE_SDHI1_TX,
310 .chcr = CHCR_TX(XMIT_SZ_16BIT),
313 .slave_id = SHDMA_SLAVE_SDHI1_RX,
315 .chcr = CHCR_RX(XMIT_SZ_16BIT),
318 .slave_id = SHDMA_SLAVE_SDHI2_TX,
320 .chcr = CHCR_TX(XMIT_SZ_16BIT),
323 .slave_id = SHDMA_SLAVE_SDHI2_RX,
325 .chcr = CHCR_RX(XMIT_SZ_16BIT),
328 .slave_id = SHDMA_SLAVE_FSIA_TX,
330 .chcr = CHCR_TX(XMIT_SZ_32BIT),
333 .slave_id = SHDMA_SLAVE_FSIA_RX,
335 .chcr = CHCR_RX(XMIT_SZ_32BIT),
338 .slave_id = SHDMA_SLAVE_MMCIF_TX,
340 .chcr = CHCR_TX(XMIT_SZ_32BIT),
343 .slave_id = SHDMA_SLAVE_MMCIF_RX,
345 .chcr = CHCR_RX(XMIT_SZ_32BIT),
350 #define SH7372_CHCLR (0x220 - 0x20)
352 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
357 .chclr_offset = SH7372_CHCLR + 0,
362 .chclr_offset = SH7372_CHCLR + 0x10,
367 .chclr_offset = SH7372_CHCLR + 0x20,
372 .chclr_offset = SH7372_CHCLR + 0x30,
377 .chclr_offset = SH7372_CHCLR + 0x50,
382 .chclr_offset = SH7372_CHCLR + 0x60,
386 static struct sh_dmae_pdata dma_platform_data = {
387 .slave = sh7372_dmae_slaves,
388 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
389 .channel = sh7372_dmae_channels,
390 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
391 .ts_low_shift = TS_LOW_SHIFT,
392 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
393 .ts_high_shift = TS_HI_SHIFT,
394 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
395 .ts_shift = dma_ts_shift,
396 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
397 .dmaor_init = DMAOR_DME,
401 /* Resource order important! */
402 static struct resource sh7372_dmae0_resources[] = {
404 /* Channel registers and DMAOR */
407 .flags = IORESOURCE_MEM,
413 .flags = IORESOURCE_MEM,
417 .start = evt2irq(0x20c0),
418 .end = evt2irq(0x20c0),
419 .flags = IORESOURCE_IRQ,
422 /* IRQ for channels 0-5 */
423 .start = evt2irq(0x2000),
424 .end = evt2irq(0x20a0),
425 .flags = IORESOURCE_IRQ,
429 /* Resource order important! */
430 static struct resource sh7372_dmae1_resources[] = {
432 /* Channel registers and DMAOR */
435 .flags = IORESOURCE_MEM,
441 .flags = IORESOURCE_MEM,
445 .start = evt2irq(0x21c0),
446 .end = evt2irq(0x21c0),
447 .flags = IORESOURCE_IRQ,
450 /* IRQ for channels 0-5 */
451 .start = evt2irq(0x2100),
452 .end = evt2irq(0x21a0),
453 .flags = IORESOURCE_IRQ,
457 /* Resource order important! */
458 static struct resource sh7372_dmae2_resources[] = {
460 /* Channel registers and DMAOR */
463 .flags = IORESOURCE_MEM,
469 .flags = IORESOURCE_MEM,
473 .start = evt2irq(0x22c0),
474 .end = evt2irq(0x22c0),
475 .flags = IORESOURCE_IRQ,
478 /* IRQ for channels 0-5 */
479 .start = evt2irq(0x2200),
480 .end = evt2irq(0x22a0),
481 .flags = IORESOURCE_IRQ,
485 static struct platform_device dma0_device = {
486 .name = "sh-dma-engine",
488 .resource = sh7372_dmae0_resources,
489 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
491 .platform_data = &dma_platform_data,
495 static struct platform_device dma1_device = {
496 .name = "sh-dma-engine",
498 .resource = sh7372_dmae1_resources,
499 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
501 .platform_data = &dma_platform_data,
505 static struct platform_device dma2_device = {
506 .name = "sh-dma-engine",
508 .resource = sh7372_dmae2_resources,
509 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
511 .platform_data = &dma_platform_data,
518 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
527 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
529 .slave_id = SHDMA_SLAVE_USB0_TX,
530 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
532 .slave_id = SHDMA_SLAVE_USB0_RX,
533 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
537 static struct sh_dmae_pdata usb_dma0_platform_data = {
538 .slave = sh7372_usb_dmae0_slaves,
539 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
540 .channel = sh7372_usb_dmae_channels,
541 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
542 .ts_low_shift = USBTS_LOW_SHIFT,
543 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
544 .ts_high_shift = USBTS_HI_SHIFT,
545 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
546 .ts_shift = dma_usbts_shift,
547 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
548 .dmaor_init = DMAOR_DME,
550 .chcr_ie_bit = 1 << 5,
557 static struct resource sh7372_usb_dmae0_resources[] = {
559 /* Channel registers and DMAOR */
561 .end = 0xe68a0064 - 1,
562 .flags = IORESOURCE_MEM,
567 .end = 0xe68a0014 - 1,
568 .flags = IORESOURCE_MEM,
571 /* IRQ for channels */
572 .start = evt2irq(0x0a00),
573 .end = evt2irq(0x0a00),
574 .flags = IORESOURCE_IRQ,
578 static struct platform_device usb_dma0_device = {
579 .name = "sh-dma-engine",
581 .resource = sh7372_usb_dmae0_resources,
582 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
584 .platform_data = &usb_dma0_platform_data,
589 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
591 .slave_id = SHDMA_SLAVE_USB1_TX,
592 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
594 .slave_id = SHDMA_SLAVE_USB1_RX,
595 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
599 static struct sh_dmae_pdata usb_dma1_platform_data = {
600 .slave = sh7372_usb_dmae1_slaves,
601 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
602 .channel = sh7372_usb_dmae_channels,
603 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
604 .ts_low_shift = USBTS_LOW_SHIFT,
605 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
606 .ts_high_shift = USBTS_HI_SHIFT,
607 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
608 .ts_shift = dma_usbts_shift,
609 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
610 .dmaor_init = DMAOR_DME,
612 .chcr_ie_bit = 1 << 5,
619 static struct resource sh7372_usb_dmae1_resources[] = {
621 /* Channel registers and DMAOR */
623 .end = 0xe68c0064 - 1,
624 .flags = IORESOURCE_MEM,
629 .end = 0xe68c0014 - 1,
630 .flags = IORESOURCE_MEM,
633 /* IRQ for channels */
634 .start = evt2irq(0x1d00),
635 .end = evt2irq(0x1d00),
636 .flags = IORESOURCE_IRQ,
640 static struct platform_device usb_dma1_device = {
641 .name = "sh-dma-engine",
643 .resource = sh7372_usb_dmae1_resources,
644 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
646 .platform_data = &usb_dma1_platform_data,
651 static struct uio_info vpu_platform_data = {
654 .irq = intcs_evt2irq(0x980),
657 static struct resource vpu_resources[] = {
662 .flags = IORESOURCE_MEM,
666 static struct platform_device vpu_device = {
667 .name = "uio_pdrv_genirq",
670 .platform_data = &vpu_platform_data,
672 .resource = vpu_resources,
673 .num_resources = ARRAY_SIZE(vpu_resources),
677 static struct uio_info veu0_platform_data = {
680 .irq = intcs_evt2irq(0x700),
683 static struct resource veu0_resources[] = {
688 .flags = IORESOURCE_MEM,
692 static struct platform_device veu0_device = {
693 .name = "uio_pdrv_genirq",
696 .platform_data = &veu0_platform_data,
698 .resource = veu0_resources,
699 .num_resources = ARRAY_SIZE(veu0_resources),
703 static struct uio_info veu1_platform_data = {
706 .irq = intcs_evt2irq(0x720),
709 static struct resource veu1_resources[] = {
714 .flags = IORESOURCE_MEM,
718 static struct platform_device veu1_device = {
719 .name = "uio_pdrv_genirq",
722 .platform_data = &veu1_platform_data,
724 .resource = veu1_resources,
725 .num_resources = ARRAY_SIZE(veu1_resources),
729 static struct uio_info veu2_platform_data = {
732 .irq = intcs_evt2irq(0x740),
735 static struct resource veu2_resources[] = {
740 .flags = IORESOURCE_MEM,
744 static struct platform_device veu2_device = {
745 .name = "uio_pdrv_genirq",
748 .platform_data = &veu2_platform_data,
750 .resource = veu2_resources,
751 .num_resources = ARRAY_SIZE(veu2_resources),
755 static struct uio_info veu3_platform_data = {
758 .irq = intcs_evt2irq(0x760),
761 static struct resource veu3_resources[] = {
766 .flags = IORESOURCE_MEM,
770 static struct platform_device veu3_device = {
771 .name = "uio_pdrv_genirq",
774 .platform_data = &veu3_platform_data,
776 .resource = veu3_resources,
777 .num_resources = ARRAY_SIZE(veu3_resources),
781 static struct uio_info jpu_platform_data = {
784 .irq = intcs_evt2irq(0x560),
787 static struct resource jpu_resources[] = {
792 .flags = IORESOURCE_MEM,
796 static struct platform_device jpu_device = {
797 .name = "uio_pdrv_genirq",
800 .platform_data = &jpu_platform_data,
802 .resource = jpu_resources,
803 .num_resources = ARRAY_SIZE(jpu_resources),
807 static struct uio_info spu0_platform_data = {
810 .irq = evt2irq(0x1800),
813 static struct resource spu0_resources[] = {
818 .flags = IORESOURCE_MEM,
822 static struct platform_device spu0_device = {
823 .name = "uio_pdrv_genirq",
826 .platform_data = &spu0_platform_data,
828 .resource = spu0_resources,
829 .num_resources = ARRAY_SIZE(spu0_resources),
833 static struct uio_info spu1_platform_data = {
836 .irq = evt2irq(0x1820),
839 static struct resource spu1_resources[] = {
844 .flags = IORESOURCE_MEM,
848 static struct platform_device spu1_device = {
849 .name = "uio_pdrv_genirq",
852 .platform_data = &spu1_platform_data,
854 .resource = spu1_resources,
855 .num_resources = ARRAY_SIZE(spu1_resources),
858 /* IPMMUI (an IPMMU module for ICB/LMB) */
859 static struct resource ipmmu_resources[] = {
864 .flags = IORESOURCE_MEM,
868 static const char * const ipmmu_dev_names[] = {
869 "sh_mobile_lcdc_fb.0",
870 "sh_mobile_lcdc_fb.1",
880 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
881 .dev_names = ipmmu_dev_names,
882 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
885 static struct platform_device ipmmu_device = {
889 .platform_data = &ipmmu_platform_data,
891 .resource = ipmmu_resources,
892 .num_resources = ARRAY_SIZE(ipmmu_resources),
895 static struct platform_device *sh7372_early_devices[] __initdata = {
908 static struct platform_device *sh7372_late_devices[] __initdata = {
926 void __init sh7372_add_standard_devices(void)
928 struct pm_domain_device domain_devices[] = {
929 { "A3RV", &vpu_device, },
930 { "A4MP", &spu0_device, },
931 { "A4MP", &spu1_device, },
932 { "A3SP", &scif0_device, },
933 { "A3SP", &scif1_device, },
934 { "A3SP", &scif2_device, },
935 { "A3SP", &scif3_device, },
936 { "A3SP", &scif4_device, },
937 { "A3SP", &scif5_device, },
938 { "A3SP", &scif6_device, },
939 { "A3SP", &iic1_device, },
940 { "A3SP", &dma0_device, },
941 { "A3SP", &dma1_device, },
942 { "A3SP", &dma2_device, },
943 { "A3SP", &usb_dma0_device, },
944 { "A3SP", &usb_dma1_device, },
945 { "A4R", &iic0_device, },
946 { "A4R", &veu0_device, },
947 { "A4R", &veu1_device, },
948 { "A4R", &veu2_device, },
949 { "A4R", &veu3_device, },
950 { "A4R", &jpu_device, },
951 { "A4R", &tmu0_device, },
954 sh7372_init_pm_domains();
956 platform_add_devices(sh7372_early_devices,
957 ARRAY_SIZE(sh7372_early_devices));
959 platform_add_devices(sh7372_late_devices,
960 ARRAY_SIZE(sh7372_late_devices));
962 rmobile_add_devices_to_domains(domain_devices,
963 ARRAY_SIZE(domain_devices));
966 void __init sh7372_earlytimer_init(void)
969 shmobile_earlytimer_init();
972 void __init sh7372_add_early_devices(void)
974 early_platform_add_devices(sh7372_early_devices,
975 ARRAY_SIZE(sh7372_early_devices));
977 /* setup early console here as well */
978 shmobile_setup_console();
983 void __init sh7372_add_early_devices_dt(void)
985 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
987 sh7372_add_early_devices();
990 void __init sh7372_add_standard_devices_dt(void)
992 /* clocks are setup late during boot in the case of DT */
995 platform_add_devices(sh7372_early_devices,
996 ARRAY_SIZE(sh7372_early_devices));
998 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1001 static const char *sh7372_boards_compat_dt[] __initdata = {
1006 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1007 .map_io = sh7372_map_io,
1008 .init_early = sh7372_add_early_devices_dt,
1009 .nr_irqs = NR_IRQS_LEGACY,
1010 .init_irq = sh7372_init_irq,
1011 .handle_irq = shmobile_handle_irq_intc,
1012 .init_machine = sh7372_add_standard_devices_dt,
1013 .dt_compat = sh7372_boards_compat_dt,
1016 #endif /* CONFIG_USE_OF */