2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/platform_data/sh_ipmmu.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
43 #include "dma-register.h"
45 #include "pm-rmobile.h"
48 static struct map_desc sh7372_io_desc[] __initdata = {
49 /* create a 1:1 entity map for 0xe6xxxxxx
50 * used by CPGA, INTC and PFC.
53 .virtual = 0xe6000000,
54 .pfn = __phys_to_pfn(0xe6000000),
56 .type = MT_DEVICE_NONSHARED
60 void __init sh7372_map_io(void)
62 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
66 static struct resource sh7372_pfc_resources[] = {
70 .flags = IORESOURCE_MEM,
75 .flags = IORESOURCE_MEM,
79 static struct platform_device sh7372_pfc_device = {
82 .resource = sh7372_pfc_resources,
83 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
86 void __init sh7372_pinmux_init(void)
88 platform_device_register(&sh7372_pfc_device);
92 #define SH7372_SCIF(scif_type, index, baseaddr, irq) \
93 static struct plat_sci_port scif##index##_platform_data = { \
95 .flags = UPF_BOOT_AUTOCONF, \
96 .scscr = SCSCR_RE | SCSCR_TE, \
99 static struct resource scif##index##_resources[] = { \
100 DEFINE_RES_MEM(baseaddr, 0x100), \
101 DEFINE_RES_IRQ(irq), \
104 static struct platform_device scif##index##_device = { \
107 .resource = scif##index##_resources, \
108 .num_resources = ARRAY_SIZE(scif##index##_resources), \
110 .platform_data = &scif##index##_platform_data, \
114 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
115 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
116 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
117 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
118 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
119 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
120 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
123 static struct sh_timer_config cmt2_platform_data = {
124 .channels_mask = 0x20,
127 static struct resource cmt2_resources[] = {
128 DEFINE_RES_MEM(0xe6130000, 0x50),
129 DEFINE_RES_IRQ(evt2irq(0x0b80)),
132 static struct platform_device cmt2_device = {
133 .name = "sh-cmt-32-fast",
136 .platform_data = &cmt2_platform_data,
138 .resource = cmt2_resources,
139 .num_resources = ARRAY_SIZE(cmt2_resources),
143 static struct sh_timer_config tmu0_platform_data = {
147 static struct resource tmu0_resources[] = {
148 DEFINE_RES_MEM(0xfff60000, 0x2c),
149 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
150 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
151 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
154 static struct platform_device tmu0_device = {
158 .platform_data = &tmu0_platform_data,
160 .resource = tmu0_resources,
161 .num_resources = ARRAY_SIZE(tmu0_resources),
165 static struct resource iic0_resources[] = {
169 .end = 0xFFF20425 - 1,
170 .flags = IORESOURCE_MEM,
173 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
174 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
175 .flags = IORESOURCE_IRQ,
179 static struct platform_device iic0_device = {
180 .name = "i2c-sh_mobile",
181 .id = 0, /* "i2c0" clock */
182 .num_resources = ARRAY_SIZE(iic0_resources),
183 .resource = iic0_resources,
186 static struct resource iic1_resources[] = {
190 .end = 0xE6C20425 - 1,
191 .flags = IORESOURCE_MEM,
194 .start = evt2irq(0x780), /* IIC1_ALI1 */
195 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
196 .flags = IORESOURCE_IRQ,
200 static struct platform_device iic1_device = {
201 .name = "i2c-sh_mobile",
202 .id = 1, /* "i2c1" clock */
203 .num_resources = ARRAY_SIZE(iic1_resources),
204 .resource = iic1_resources,
208 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
210 .slave_id = SHDMA_SLAVE_SCIF0_TX,
212 .chcr = CHCR_TX(XMIT_SZ_8BIT),
215 .slave_id = SHDMA_SLAVE_SCIF0_RX,
217 .chcr = CHCR_RX(XMIT_SZ_8BIT),
220 .slave_id = SHDMA_SLAVE_SCIF1_TX,
222 .chcr = CHCR_TX(XMIT_SZ_8BIT),
225 .slave_id = SHDMA_SLAVE_SCIF1_RX,
227 .chcr = CHCR_RX(XMIT_SZ_8BIT),
230 .slave_id = SHDMA_SLAVE_SCIF2_TX,
232 .chcr = CHCR_TX(XMIT_SZ_8BIT),
235 .slave_id = SHDMA_SLAVE_SCIF2_RX,
237 .chcr = CHCR_RX(XMIT_SZ_8BIT),
240 .slave_id = SHDMA_SLAVE_SCIF3_TX,
242 .chcr = CHCR_TX(XMIT_SZ_8BIT),
245 .slave_id = SHDMA_SLAVE_SCIF3_RX,
247 .chcr = CHCR_RX(XMIT_SZ_8BIT),
250 .slave_id = SHDMA_SLAVE_SCIF4_TX,
252 .chcr = CHCR_TX(XMIT_SZ_8BIT),
255 .slave_id = SHDMA_SLAVE_SCIF4_RX,
257 .chcr = CHCR_RX(XMIT_SZ_8BIT),
260 .slave_id = SHDMA_SLAVE_SCIF5_TX,
262 .chcr = CHCR_TX(XMIT_SZ_8BIT),
265 .slave_id = SHDMA_SLAVE_SCIF5_RX,
267 .chcr = CHCR_RX(XMIT_SZ_8BIT),
270 .slave_id = SHDMA_SLAVE_SCIF6_TX,
272 .chcr = CHCR_TX(XMIT_SZ_8BIT),
275 .slave_id = SHDMA_SLAVE_SCIF6_RX,
277 .chcr = CHCR_RX(XMIT_SZ_8BIT),
280 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
282 .chcr = CHCR_TX(XMIT_SZ_32BIT),
285 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
287 .chcr = CHCR_RX(XMIT_SZ_32BIT),
290 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
292 .chcr = CHCR_TX(XMIT_SZ_32BIT),
295 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
297 .chcr = CHCR_RX(XMIT_SZ_32BIT),
300 .slave_id = SHDMA_SLAVE_SDHI0_TX,
302 .chcr = CHCR_TX(XMIT_SZ_16BIT),
305 .slave_id = SHDMA_SLAVE_SDHI0_RX,
307 .chcr = CHCR_RX(XMIT_SZ_16BIT),
310 .slave_id = SHDMA_SLAVE_SDHI1_TX,
312 .chcr = CHCR_TX(XMIT_SZ_16BIT),
315 .slave_id = SHDMA_SLAVE_SDHI1_RX,
317 .chcr = CHCR_RX(XMIT_SZ_16BIT),
320 .slave_id = SHDMA_SLAVE_SDHI2_TX,
322 .chcr = CHCR_TX(XMIT_SZ_16BIT),
325 .slave_id = SHDMA_SLAVE_SDHI2_RX,
327 .chcr = CHCR_RX(XMIT_SZ_16BIT),
330 .slave_id = SHDMA_SLAVE_FSIA_TX,
332 .chcr = CHCR_TX(XMIT_SZ_32BIT),
335 .slave_id = SHDMA_SLAVE_FSIA_RX,
337 .chcr = CHCR_RX(XMIT_SZ_32BIT),
340 .slave_id = SHDMA_SLAVE_MMCIF_TX,
342 .chcr = CHCR_TX(XMIT_SZ_32BIT),
345 .slave_id = SHDMA_SLAVE_MMCIF_RX,
347 .chcr = CHCR_RX(XMIT_SZ_32BIT),
352 #define SH7372_CHCLR (0x220 - 0x20)
354 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
359 .chclr_offset = SH7372_CHCLR + 0,
364 .chclr_offset = SH7372_CHCLR + 0x10,
369 .chclr_offset = SH7372_CHCLR + 0x20,
374 .chclr_offset = SH7372_CHCLR + 0x30,
379 .chclr_offset = SH7372_CHCLR + 0x50,
384 .chclr_offset = SH7372_CHCLR + 0x60,
388 static struct sh_dmae_pdata dma_platform_data = {
389 .slave = sh7372_dmae_slaves,
390 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
391 .channel = sh7372_dmae_channels,
392 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
393 .ts_low_shift = TS_LOW_SHIFT,
394 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
395 .ts_high_shift = TS_HI_SHIFT,
396 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
397 .ts_shift = dma_ts_shift,
398 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
399 .dmaor_init = DMAOR_DME,
403 /* Resource order important! */
404 static struct resource sh7372_dmae0_resources[] = {
406 /* Channel registers and DMAOR */
409 .flags = IORESOURCE_MEM,
415 .flags = IORESOURCE_MEM,
419 .start = evt2irq(0x20c0),
420 .end = evt2irq(0x20c0),
421 .flags = IORESOURCE_IRQ,
424 /* IRQ for channels 0-5 */
425 .start = evt2irq(0x2000),
426 .end = evt2irq(0x20a0),
427 .flags = IORESOURCE_IRQ,
431 /* Resource order important! */
432 static struct resource sh7372_dmae1_resources[] = {
434 /* Channel registers and DMAOR */
437 .flags = IORESOURCE_MEM,
443 .flags = IORESOURCE_MEM,
447 .start = evt2irq(0x21c0),
448 .end = evt2irq(0x21c0),
449 .flags = IORESOURCE_IRQ,
452 /* IRQ for channels 0-5 */
453 .start = evt2irq(0x2100),
454 .end = evt2irq(0x21a0),
455 .flags = IORESOURCE_IRQ,
459 /* Resource order important! */
460 static struct resource sh7372_dmae2_resources[] = {
462 /* Channel registers and DMAOR */
465 .flags = IORESOURCE_MEM,
471 .flags = IORESOURCE_MEM,
475 .start = evt2irq(0x22c0),
476 .end = evt2irq(0x22c0),
477 .flags = IORESOURCE_IRQ,
480 /* IRQ for channels 0-5 */
481 .start = evt2irq(0x2200),
482 .end = evt2irq(0x22a0),
483 .flags = IORESOURCE_IRQ,
487 static struct platform_device dma0_device = {
488 .name = "sh-dma-engine",
490 .resource = sh7372_dmae0_resources,
491 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
493 .platform_data = &dma_platform_data,
497 static struct platform_device dma1_device = {
498 .name = "sh-dma-engine",
500 .resource = sh7372_dmae1_resources,
501 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
503 .platform_data = &dma_platform_data,
507 static struct platform_device dma2_device = {
508 .name = "sh-dma-engine",
510 .resource = sh7372_dmae2_resources,
511 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
513 .platform_data = &dma_platform_data,
520 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
529 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
531 .slave_id = SHDMA_SLAVE_USB0_TX,
532 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
534 .slave_id = SHDMA_SLAVE_USB0_RX,
535 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
539 static struct sh_dmae_pdata usb_dma0_platform_data = {
540 .slave = sh7372_usb_dmae0_slaves,
541 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
542 .channel = sh7372_usb_dmae_channels,
543 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
544 .ts_low_shift = USBTS_LOW_SHIFT,
545 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
546 .ts_high_shift = USBTS_HI_SHIFT,
547 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
548 .ts_shift = dma_usbts_shift,
549 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
550 .dmaor_init = DMAOR_DME,
552 .chcr_ie_bit = 1 << 5,
559 static struct resource sh7372_usb_dmae0_resources[] = {
561 /* Channel registers and DMAOR */
563 .end = 0xe68a0064 - 1,
564 .flags = IORESOURCE_MEM,
569 .end = 0xe68a0014 - 1,
570 .flags = IORESOURCE_MEM,
573 /* IRQ for channels */
574 .start = evt2irq(0x0a00),
575 .end = evt2irq(0x0a00),
576 .flags = IORESOURCE_IRQ,
580 static struct platform_device usb_dma0_device = {
581 .name = "sh-dma-engine",
583 .resource = sh7372_usb_dmae0_resources,
584 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
586 .platform_data = &usb_dma0_platform_data,
591 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
593 .slave_id = SHDMA_SLAVE_USB1_TX,
594 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
596 .slave_id = SHDMA_SLAVE_USB1_RX,
597 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
601 static struct sh_dmae_pdata usb_dma1_platform_data = {
602 .slave = sh7372_usb_dmae1_slaves,
603 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
604 .channel = sh7372_usb_dmae_channels,
605 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
606 .ts_low_shift = USBTS_LOW_SHIFT,
607 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
608 .ts_high_shift = USBTS_HI_SHIFT,
609 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
610 .ts_shift = dma_usbts_shift,
611 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
612 .dmaor_init = DMAOR_DME,
614 .chcr_ie_bit = 1 << 5,
621 static struct resource sh7372_usb_dmae1_resources[] = {
623 /* Channel registers and DMAOR */
625 .end = 0xe68c0064 - 1,
626 .flags = IORESOURCE_MEM,
631 .end = 0xe68c0014 - 1,
632 .flags = IORESOURCE_MEM,
635 /* IRQ for channels */
636 .start = evt2irq(0x1d00),
637 .end = evt2irq(0x1d00),
638 .flags = IORESOURCE_IRQ,
642 static struct platform_device usb_dma1_device = {
643 .name = "sh-dma-engine",
645 .resource = sh7372_usb_dmae1_resources,
646 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
648 .platform_data = &usb_dma1_platform_data,
653 static struct uio_info vpu_platform_data = {
656 .irq = intcs_evt2irq(0x980),
659 static struct resource vpu_resources[] = {
664 .flags = IORESOURCE_MEM,
668 static struct platform_device vpu_device = {
669 .name = "uio_pdrv_genirq",
672 .platform_data = &vpu_platform_data,
674 .resource = vpu_resources,
675 .num_resources = ARRAY_SIZE(vpu_resources),
679 static struct uio_info veu0_platform_data = {
682 .irq = intcs_evt2irq(0x700),
685 static struct resource veu0_resources[] = {
690 .flags = IORESOURCE_MEM,
694 static struct platform_device veu0_device = {
695 .name = "uio_pdrv_genirq",
698 .platform_data = &veu0_platform_data,
700 .resource = veu0_resources,
701 .num_resources = ARRAY_SIZE(veu0_resources),
705 static struct uio_info veu1_platform_data = {
708 .irq = intcs_evt2irq(0x720),
711 static struct resource veu1_resources[] = {
716 .flags = IORESOURCE_MEM,
720 static struct platform_device veu1_device = {
721 .name = "uio_pdrv_genirq",
724 .platform_data = &veu1_platform_data,
726 .resource = veu1_resources,
727 .num_resources = ARRAY_SIZE(veu1_resources),
731 static struct uio_info veu2_platform_data = {
734 .irq = intcs_evt2irq(0x740),
737 static struct resource veu2_resources[] = {
742 .flags = IORESOURCE_MEM,
746 static struct platform_device veu2_device = {
747 .name = "uio_pdrv_genirq",
750 .platform_data = &veu2_platform_data,
752 .resource = veu2_resources,
753 .num_resources = ARRAY_SIZE(veu2_resources),
757 static struct uio_info veu3_platform_data = {
760 .irq = intcs_evt2irq(0x760),
763 static struct resource veu3_resources[] = {
768 .flags = IORESOURCE_MEM,
772 static struct platform_device veu3_device = {
773 .name = "uio_pdrv_genirq",
776 .platform_data = &veu3_platform_data,
778 .resource = veu3_resources,
779 .num_resources = ARRAY_SIZE(veu3_resources),
783 static struct uio_info jpu_platform_data = {
786 .irq = intcs_evt2irq(0x560),
789 static struct resource jpu_resources[] = {
794 .flags = IORESOURCE_MEM,
798 static struct platform_device jpu_device = {
799 .name = "uio_pdrv_genirq",
802 .platform_data = &jpu_platform_data,
804 .resource = jpu_resources,
805 .num_resources = ARRAY_SIZE(jpu_resources),
809 static struct uio_info spu0_platform_data = {
812 .irq = evt2irq(0x1800),
815 static struct resource spu0_resources[] = {
820 .flags = IORESOURCE_MEM,
824 static struct platform_device spu0_device = {
825 .name = "uio_pdrv_genirq",
828 .platform_data = &spu0_platform_data,
830 .resource = spu0_resources,
831 .num_resources = ARRAY_SIZE(spu0_resources),
835 static struct uio_info spu1_platform_data = {
838 .irq = evt2irq(0x1820),
841 static struct resource spu1_resources[] = {
846 .flags = IORESOURCE_MEM,
850 static struct platform_device spu1_device = {
851 .name = "uio_pdrv_genirq",
854 .platform_data = &spu1_platform_data,
856 .resource = spu1_resources,
857 .num_resources = ARRAY_SIZE(spu1_resources),
860 /* IPMMUI (an IPMMU module for ICB/LMB) */
861 static struct resource ipmmu_resources[] = {
866 .flags = IORESOURCE_MEM,
870 static const char * const ipmmu_dev_names[] = {
871 "sh_mobile_lcdc_fb.0",
872 "sh_mobile_lcdc_fb.1",
882 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
883 .dev_names = ipmmu_dev_names,
884 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
887 static struct platform_device ipmmu_device = {
891 .platform_data = &ipmmu_platform_data,
893 .resource = ipmmu_resources,
894 .num_resources = ARRAY_SIZE(ipmmu_resources),
897 static struct platform_device *sh7372_early_devices[] __initdata = {
910 static struct platform_device *sh7372_late_devices[] __initdata = {
928 void __init sh7372_add_standard_devices(void)
930 struct pm_domain_device domain_devices[] = {
931 { "A3RV", &vpu_device, },
932 { "A4MP", &spu0_device, },
933 { "A4MP", &spu1_device, },
934 { "A3SP", &scif0_device, },
935 { "A3SP", &scif1_device, },
936 { "A3SP", &scif2_device, },
937 { "A3SP", &scif3_device, },
938 { "A3SP", &scif4_device, },
939 { "A3SP", &scif5_device, },
940 { "A3SP", &scif6_device, },
941 { "A3SP", &iic1_device, },
942 { "A3SP", &dma0_device, },
943 { "A3SP", &dma1_device, },
944 { "A3SP", &dma2_device, },
945 { "A3SP", &usb_dma0_device, },
946 { "A3SP", &usb_dma1_device, },
947 { "A4R", &iic0_device, },
948 { "A4R", &veu0_device, },
949 { "A4R", &veu1_device, },
950 { "A4R", &veu2_device, },
951 { "A4R", &veu3_device, },
952 { "A4R", &jpu_device, },
953 { "A4R", &tmu0_device, },
956 sh7372_init_pm_domains();
958 platform_add_devices(sh7372_early_devices,
959 ARRAY_SIZE(sh7372_early_devices));
961 platform_add_devices(sh7372_late_devices,
962 ARRAY_SIZE(sh7372_late_devices));
964 rmobile_add_devices_to_domains(domain_devices,
965 ARRAY_SIZE(domain_devices));
968 void __init sh7372_earlytimer_init(void)
971 shmobile_earlytimer_init();
974 void __init sh7372_add_early_devices(void)
976 early_platform_add_devices(sh7372_early_devices,
977 ARRAY_SIZE(sh7372_early_devices));
979 /* setup early console here as well */
980 shmobile_setup_console();
985 void __init sh7372_add_early_devices_dt(void)
987 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
989 sh7372_add_early_devices();
992 void __init sh7372_add_standard_devices_dt(void)
994 /* clocks are setup late during boot in the case of DT */
997 platform_add_devices(sh7372_early_devices,
998 ARRAY_SIZE(sh7372_early_devices));
1000 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1003 static const char *sh7372_boards_compat_dt[] __initdata = {
1008 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1009 .map_io = sh7372_map_io,
1010 .init_early = sh7372_add_early_devices_dt,
1011 .nr_irqs = NR_IRQS_LEGACY,
1012 .init_irq = sh7372_init_irq,
1013 .handle_irq = shmobile_handle_irq_intc,
1014 .init_machine = sh7372_add_standard_devices_dt,
1015 .dt_compat = sh7372_boards_compat_dt,
1018 #endif /* CONFIG_USE_OF */