2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <mach/hardware.h>
34 #include <mach/irqs.h>
35 #include <mach/sh73a0.h>
36 #include <mach/common.h>
37 #include <asm/mach-types.h>
38 #include <asm/mach/map.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
42 static struct map_desc sh73a0_io_desc[] __initdata = {
43 /* create a 1:1 entity map for 0xe6xxxxxx
44 * used by CPGA, INTC and PFC.
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
50 .type = MT_DEVICE_NONSHARED
54 void __init sh73a0_map_io(void)
56 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
59 static struct plat_sci_port scif0_platform_data = {
60 .mapbase = 0xe6c40000,
61 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_RE | SCSCR_TE,
63 .scbrr_algo_id = SCBRR_ALGO_4,
65 .irqs = { gic_spi(72), gic_spi(72),
66 gic_spi(72), gic_spi(72) },
69 static struct platform_device scif0_device = {
73 .platform_data = &scif0_platform_data,
77 static struct plat_sci_port scif1_platform_data = {
78 .mapbase = 0xe6c50000,
79 .flags = UPF_BOOT_AUTOCONF,
80 .scscr = SCSCR_RE | SCSCR_TE,
81 .scbrr_algo_id = SCBRR_ALGO_4,
83 .irqs = { gic_spi(73), gic_spi(73),
84 gic_spi(73), gic_spi(73) },
87 static struct platform_device scif1_device = {
91 .platform_data = &scif1_platform_data,
95 static struct plat_sci_port scif2_platform_data = {
96 .mapbase = 0xe6c60000,
97 .flags = UPF_BOOT_AUTOCONF,
98 .scscr = SCSCR_RE | SCSCR_TE,
99 .scbrr_algo_id = SCBRR_ALGO_4,
101 .irqs = { gic_spi(74), gic_spi(74),
102 gic_spi(74), gic_spi(74) },
105 static struct platform_device scif2_device = {
109 .platform_data = &scif2_platform_data,
113 static struct plat_sci_port scif3_platform_data = {
114 .mapbase = 0xe6c70000,
115 .flags = UPF_BOOT_AUTOCONF,
116 .scscr = SCSCR_RE | SCSCR_TE,
117 .scbrr_algo_id = SCBRR_ALGO_4,
119 .irqs = { gic_spi(75), gic_spi(75),
120 gic_spi(75), gic_spi(75) },
123 static struct platform_device scif3_device = {
127 .platform_data = &scif3_platform_data,
131 static struct plat_sci_port scif4_platform_data = {
132 .mapbase = 0xe6c80000,
133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE,
135 .scbrr_algo_id = SCBRR_ALGO_4,
137 .irqs = { gic_spi(78), gic_spi(78),
138 gic_spi(78), gic_spi(78) },
141 static struct platform_device scif4_device = {
145 .platform_data = &scif4_platform_data,
149 static struct plat_sci_port scif5_platform_data = {
150 .mapbase = 0xe6cb0000,
151 .flags = UPF_BOOT_AUTOCONF,
152 .scscr = SCSCR_RE | SCSCR_TE,
153 .scbrr_algo_id = SCBRR_ALGO_4,
155 .irqs = { gic_spi(79), gic_spi(79),
156 gic_spi(79), gic_spi(79) },
159 static struct platform_device scif5_device = {
163 .platform_data = &scif5_platform_data,
167 static struct plat_sci_port scif6_platform_data = {
168 .mapbase = 0xe6cc0000,
169 .flags = UPF_BOOT_AUTOCONF,
170 .scscr = SCSCR_RE | SCSCR_TE,
171 .scbrr_algo_id = SCBRR_ALGO_4,
173 .irqs = { gic_spi(156), gic_spi(156),
174 gic_spi(156), gic_spi(156) },
177 static struct platform_device scif6_device = {
181 .platform_data = &scif6_platform_data,
185 static struct plat_sci_port scif7_platform_data = {
186 .mapbase = 0xe6cd0000,
187 .flags = UPF_BOOT_AUTOCONF,
188 .scscr = SCSCR_RE | SCSCR_TE,
189 .scbrr_algo_id = SCBRR_ALGO_4,
191 .irqs = { gic_spi(143), gic_spi(143),
192 gic_spi(143), gic_spi(143) },
195 static struct platform_device scif7_device = {
199 .platform_data = &scif7_platform_data,
203 static struct plat_sci_port scif8_platform_data = {
204 .mapbase = 0xe6c30000,
205 .flags = UPF_BOOT_AUTOCONF,
206 .scscr = SCSCR_RE | SCSCR_TE,
207 .scbrr_algo_id = SCBRR_ALGO_4,
209 .irqs = { gic_spi(80), gic_spi(80),
210 gic_spi(80), gic_spi(80) },
213 static struct platform_device scif8_device = {
217 .platform_data = &scif8_platform_data,
221 static struct sh_timer_config cmt10_platform_data = {
223 .channel_offset = 0x10,
225 .clockevent_rating = 125,
226 .clocksource_rating = 125,
229 static struct resource cmt10_resources[] = {
234 .flags = IORESOURCE_MEM,
237 .start = gic_spi(65),
238 .flags = IORESOURCE_IRQ,
242 static struct platform_device cmt10_device = {
246 .platform_data = &cmt10_platform_data,
248 .resource = cmt10_resources,
249 .num_resources = ARRAY_SIZE(cmt10_resources),
253 static struct sh_timer_config tmu00_platform_data = {
255 .channel_offset = 0x4,
257 .clockevent_rating = 200,
260 static struct resource tmu00_resources[] = {
265 .flags = IORESOURCE_MEM,
268 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
269 .flags = IORESOURCE_IRQ,
273 static struct platform_device tmu00_device = {
277 .platform_data = &tmu00_platform_data,
279 .resource = tmu00_resources,
280 .num_resources = ARRAY_SIZE(tmu00_resources),
283 static struct sh_timer_config tmu01_platform_data = {
285 .channel_offset = 0x10,
287 .clocksource_rating = 200,
290 static struct resource tmu01_resources[] = {
295 .flags = IORESOURCE_MEM,
298 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
299 .flags = IORESOURCE_IRQ,
303 static struct platform_device tmu01_device = {
307 .platform_data = &tmu01_platform_data,
309 .resource = tmu01_resources,
310 .num_resources = ARRAY_SIZE(tmu01_resources),
313 static struct resource i2c0_resources[] = {
317 .end = 0xe6820425 - 1,
318 .flags = IORESOURCE_MEM,
321 .start = gic_spi(167),
323 .flags = IORESOURCE_IRQ,
327 static struct resource i2c1_resources[] = {
331 .end = 0xe6822425 - 1,
332 .flags = IORESOURCE_MEM,
335 .start = gic_spi(51),
337 .flags = IORESOURCE_IRQ,
341 static struct resource i2c2_resources[] = {
345 .end = 0xe6824425 - 1,
346 .flags = IORESOURCE_MEM,
349 .start = gic_spi(171),
351 .flags = IORESOURCE_IRQ,
355 static struct resource i2c3_resources[] = {
359 .end = 0xe6826425 - 1,
360 .flags = IORESOURCE_MEM,
363 .start = gic_spi(183),
365 .flags = IORESOURCE_IRQ,
369 static struct resource i2c4_resources[] = {
373 .end = 0xe6828425 - 1,
374 .flags = IORESOURCE_MEM,
377 .start = gic_spi(187),
379 .flags = IORESOURCE_IRQ,
383 static struct platform_device i2c0_device = {
384 .name = "i2c-sh_mobile",
386 .resource = i2c0_resources,
387 .num_resources = ARRAY_SIZE(i2c0_resources),
390 static struct platform_device i2c1_device = {
391 .name = "i2c-sh_mobile",
393 .resource = i2c1_resources,
394 .num_resources = ARRAY_SIZE(i2c1_resources),
397 static struct platform_device i2c2_device = {
398 .name = "i2c-sh_mobile",
400 .resource = i2c2_resources,
401 .num_resources = ARRAY_SIZE(i2c2_resources),
404 static struct platform_device i2c3_device = {
405 .name = "i2c-sh_mobile",
407 .resource = i2c3_resources,
408 .num_resources = ARRAY_SIZE(i2c3_resources),
411 static struct platform_device i2c4_device = {
412 .name = "i2c-sh_mobile",
414 .resource = i2c4_resources,
415 .num_resources = ARRAY_SIZE(i2c4_resources),
418 /* Transmit sizes and respective CHCR register values */
429 /* log2(size / 8) - used to calculate number of transfers */
431 [XMIT_SZ_8BIT] = 0, \
432 [XMIT_SZ_16BIT] = 1, \
433 [XMIT_SZ_32BIT] = 2, \
434 [XMIT_SZ_64BIT] = 3, \
435 [XMIT_SZ_128BIT] = 4, \
436 [XMIT_SZ_256BIT] = 5, \
437 [XMIT_SZ_512BIT] = 6, \
440 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
441 #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
442 #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
444 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
446 .slave_id = SHDMA_SLAVE_SCIF0_TX,
448 .chcr = CHCR_TX(XMIT_SZ_8BIT),
451 .slave_id = SHDMA_SLAVE_SCIF0_RX,
453 .chcr = CHCR_RX(XMIT_SZ_8BIT),
456 .slave_id = SHDMA_SLAVE_SCIF1_TX,
458 .chcr = CHCR_TX(XMIT_SZ_8BIT),
461 .slave_id = SHDMA_SLAVE_SCIF1_RX,
463 .chcr = CHCR_RX(XMIT_SZ_8BIT),
466 .slave_id = SHDMA_SLAVE_SCIF2_TX,
468 .chcr = CHCR_TX(XMIT_SZ_8BIT),
471 .slave_id = SHDMA_SLAVE_SCIF2_RX,
473 .chcr = CHCR_RX(XMIT_SZ_8BIT),
476 .slave_id = SHDMA_SLAVE_SCIF3_TX,
478 .chcr = CHCR_TX(XMIT_SZ_8BIT),
481 .slave_id = SHDMA_SLAVE_SCIF3_RX,
483 .chcr = CHCR_RX(XMIT_SZ_8BIT),
486 .slave_id = SHDMA_SLAVE_SCIF4_TX,
488 .chcr = CHCR_TX(XMIT_SZ_8BIT),
491 .slave_id = SHDMA_SLAVE_SCIF4_RX,
493 .chcr = CHCR_RX(XMIT_SZ_8BIT),
496 .slave_id = SHDMA_SLAVE_SCIF5_TX,
498 .chcr = CHCR_TX(XMIT_SZ_8BIT),
501 .slave_id = SHDMA_SLAVE_SCIF5_RX,
503 .chcr = CHCR_RX(XMIT_SZ_8BIT),
506 .slave_id = SHDMA_SLAVE_SCIF6_TX,
508 .chcr = CHCR_TX(XMIT_SZ_8BIT),
511 .slave_id = SHDMA_SLAVE_SCIF6_RX,
513 .chcr = CHCR_RX(XMIT_SZ_8BIT),
516 .slave_id = SHDMA_SLAVE_SCIF7_TX,
518 .chcr = CHCR_TX(XMIT_SZ_8BIT),
521 .slave_id = SHDMA_SLAVE_SCIF7_RX,
523 .chcr = CHCR_RX(XMIT_SZ_8BIT),
526 .slave_id = SHDMA_SLAVE_SCIF8_TX,
528 .chcr = CHCR_TX(XMIT_SZ_8BIT),
531 .slave_id = SHDMA_SLAVE_SCIF8_RX,
533 .chcr = CHCR_RX(XMIT_SZ_8BIT),
536 .slave_id = SHDMA_SLAVE_SDHI0_TX,
538 .chcr = CHCR_TX(XMIT_SZ_16BIT),
541 .slave_id = SHDMA_SLAVE_SDHI0_RX,
543 .chcr = CHCR_RX(XMIT_SZ_16BIT),
546 .slave_id = SHDMA_SLAVE_SDHI1_TX,
548 .chcr = CHCR_TX(XMIT_SZ_16BIT),
551 .slave_id = SHDMA_SLAVE_SDHI1_RX,
553 .chcr = CHCR_RX(XMIT_SZ_16BIT),
556 .slave_id = SHDMA_SLAVE_SDHI2_TX,
558 .chcr = CHCR_TX(XMIT_SZ_16BIT),
561 .slave_id = SHDMA_SLAVE_SDHI2_RX,
563 .chcr = CHCR_RX(XMIT_SZ_16BIT),
566 .slave_id = SHDMA_SLAVE_MMCIF_TX,
568 .chcr = CHCR_TX(XMIT_SZ_32BIT),
571 .slave_id = SHDMA_SLAVE_MMCIF_RX,
573 .chcr = CHCR_RX(XMIT_SZ_32BIT),
578 #define DMAE_CHANNEL(_offset) \
580 .offset = _offset - 0x20, \
581 .dmars = _offset - 0x20 + 0x40, \
584 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
585 DMAE_CHANNEL(0x8000),
586 DMAE_CHANNEL(0x8080),
587 DMAE_CHANNEL(0x8100),
588 DMAE_CHANNEL(0x8180),
589 DMAE_CHANNEL(0x8200),
590 DMAE_CHANNEL(0x8280),
591 DMAE_CHANNEL(0x8300),
592 DMAE_CHANNEL(0x8380),
593 DMAE_CHANNEL(0x8400),
594 DMAE_CHANNEL(0x8480),
595 DMAE_CHANNEL(0x8500),
596 DMAE_CHANNEL(0x8580),
597 DMAE_CHANNEL(0x8600),
598 DMAE_CHANNEL(0x8680),
599 DMAE_CHANNEL(0x8700),
600 DMAE_CHANNEL(0x8780),
601 DMAE_CHANNEL(0x8800),
602 DMAE_CHANNEL(0x8880),
603 DMAE_CHANNEL(0x8900),
604 DMAE_CHANNEL(0x8980),
607 static const unsigned int ts_shift[] = TS_SHIFT;
609 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
610 .slave = sh73a0_dmae_slaves,
611 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
612 .channel = sh73a0_dmae_channels,
613 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
616 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
617 .ts_high_mask = 0x00300000,
618 .ts_shift = ts_shift,
619 .ts_shift_num = ARRAY_SIZE(ts_shift),
620 .dmaor_init = DMAOR_DME,
623 static struct resource sh73a0_dmae_resources[] = {
625 /* Registers including DMAOR and channels including DMARSx */
627 .end = 0xfe008a00 - 1,
628 .flags = IORESOURCE_MEM,
632 .start = gic_spi(129),
634 .flags = IORESOURCE_IRQ,
637 /* IRQ for channels 0-19 */
638 .start = gic_spi(109),
640 .flags = IORESOURCE_IRQ,
644 static struct platform_device dma0_device = {
645 .name = "sh-dma-engine",
647 .resource = sh73a0_dmae_resources,
648 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
650 .platform_data = &sh73a0_dmae_platform_data,
654 static struct platform_device *sh73a0_early_devices[] __initdata = {
669 static struct platform_device *sh73a0_late_devices[] __initdata = {
678 #define SRCR2 0xe61580b0
680 void __init sh73a0_add_standard_devices(void)
682 /* Clear software reset bit on SY-DMAC module */
683 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
685 platform_add_devices(sh73a0_early_devices,
686 ARRAY_SIZE(sh73a0_early_devices));
687 platform_add_devices(sh73a0_late_devices,
688 ARRAY_SIZE(sh73a0_late_devices));
691 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
692 void __init __weak sh73a0_register_twd(void) { }
694 static void __init sh73a0_earlytimer_init(void)
697 shmobile_earlytimer_init();
698 sh73a0_register_twd();
701 void __init sh73a0_add_early_devices(void)
703 early_platform_add_devices(sh73a0_early_devices,
704 ARRAY_SIZE(sh73a0_early_devices));
706 /* setup early console here as well */
707 shmobile_setup_console();
709 /* override timer setup with soc-specific code */
710 shmobile_timer.init = sh73a0_earlytimer_init;