2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_timer.h>
33 #include <linux/platform_data/sh_ipmmu.h>
34 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/time.h>
42 #include "dma-register.h"
47 static struct map_desc sh73a0_io_desc[] __initdata = {
48 /* create a 1:1 entity map for 0xe6xxxxxx
49 * used by CPGA, INTC and PFC.
52 .virtual = 0xe6000000,
53 .pfn = __phys_to_pfn(0xe6000000),
55 .type = MT_DEVICE_NONSHARED
59 void __init sh73a0_map_io(void)
61 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
65 static struct resource pfc_resources[] __initdata = {
66 DEFINE_RES_MEM(0xe6050000, 0x8000),
67 DEFINE_RES_MEM(0xe605801c, 0x000c),
70 void __init sh73a0_pinmux_init(void)
72 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
73 ARRAY_SIZE(pfc_resources));
77 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
78 static struct plat_sci_port scif##index##_platform_data = { \
80 .flags = UPF_BOOT_AUTOCONF, \
81 .scscr = SCSCR_RE | SCSCR_TE, \
84 static struct resource scif##index##_resources[] = { \
85 DEFINE_RES_MEM(baseaddr, 0x100), \
86 DEFINE_RES_IRQ(irq), \
89 static struct platform_device scif##index##_device = { \
92 .resource = scif##index##_resources, \
93 .num_resources = ARRAY_SIZE(scif##index##_resources), \
95 .platform_data = &scif##index##_platform_data, \
99 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
100 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
101 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
102 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
103 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
104 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
105 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
106 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
107 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
109 static struct sh_timer_config cmt1_platform_data = {
110 .channels_mask = 0x3f,
113 static struct resource cmt1_resources[] = {
114 DEFINE_RES_MEM(0xe6138000, 0x200),
115 DEFINE_RES_IRQ(gic_spi(65)),
118 static struct platform_device cmt1_device = {
122 .platform_data = &cmt1_platform_data,
124 .resource = cmt1_resources,
125 .num_resources = ARRAY_SIZE(cmt1_resources),
129 static struct sh_timer_config tmu0_platform_data = {
133 static struct resource tmu0_resources[] = {
134 DEFINE_RES_MEM(0xfff60000, 0x2c),
135 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
136 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
137 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
140 static struct platform_device tmu0_device = {
144 .platform_data = &tmu0_platform_data,
146 .resource = tmu0_resources,
147 .num_resources = ARRAY_SIZE(tmu0_resources),
150 static struct resource i2c0_resources[] = {
151 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
153 .start = gic_spi(167),
155 .flags = IORESOURCE_IRQ,
159 static struct resource i2c1_resources[] = {
160 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
162 .start = gic_spi(51),
164 .flags = IORESOURCE_IRQ,
168 static struct resource i2c2_resources[] = {
169 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
171 .start = gic_spi(171),
173 .flags = IORESOURCE_IRQ,
177 static struct resource i2c3_resources[] = {
178 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
180 .start = gic_spi(183),
182 .flags = IORESOURCE_IRQ,
186 static struct resource i2c4_resources[] = {
187 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
189 .start = gic_spi(187),
191 .flags = IORESOURCE_IRQ,
195 static struct platform_device i2c0_device = {
196 .name = "i2c-sh_mobile",
198 .resource = i2c0_resources,
199 .num_resources = ARRAY_SIZE(i2c0_resources),
202 static struct platform_device i2c1_device = {
203 .name = "i2c-sh_mobile",
205 .resource = i2c1_resources,
206 .num_resources = ARRAY_SIZE(i2c1_resources),
209 static struct platform_device i2c2_device = {
210 .name = "i2c-sh_mobile",
212 .resource = i2c2_resources,
213 .num_resources = ARRAY_SIZE(i2c2_resources),
216 static struct platform_device i2c3_device = {
217 .name = "i2c-sh_mobile",
219 .resource = i2c3_resources,
220 .num_resources = ARRAY_SIZE(i2c3_resources),
223 static struct platform_device i2c4_device = {
224 .name = "i2c-sh_mobile",
226 .resource = i2c4_resources,
227 .num_resources = ARRAY_SIZE(i2c4_resources),
230 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
232 .slave_id = SHDMA_SLAVE_SCIF0_TX,
234 .chcr = CHCR_TX(XMIT_SZ_8BIT),
237 .slave_id = SHDMA_SLAVE_SCIF0_RX,
239 .chcr = CHCR_RX(XMIT_SZ_8BIT),
242 .slave_id = SHDMA_SLAVE_SCIF1_TX,
244 .chcr = CHCR_TX(XMIT_SZ_8BIT),
247 .slave_id = SHDMA_SLAVE_SCIF1_RX,
249 .chcr = CHCR_RX(XMIT_SZ_8BIT),
252 .slave_id = SHDMA_SLAVE_SCIF2_TX,
254 .chcr = CHCR_TX(XMIT_SZ_8BIT),
257 .slave_id = SHDMA_SLAVE_SCIF2_RX,
259 .chcr = CHCR_RX(XMIT_SZ_8BIT),
262 .slave_id = SHDMA_SLAVE_SCIF3_TX,
264 .chcr = CHCR_TX(XMIT_SZ_8BIT),
267 .slave_id = SHDMA_SLAVE_SCIF3_RX,
269 .chcr = CHCR_RX(XMIT_SZ_8BIT),
272 .slave_id = SHDMA_SLAVE_SCIF4_TX,
274 .chcr = CHCR_TX(XMIT_SZ_8BIT),
277 .slave_id = SHDMA_SLAVE_SCIF4_RX,
279 .chcr = CHCR_RX(XMIT_SZ_8BIT),
282 .slave_id = SHDMA_SLAVE_SCIF5_TX,
284 .chcr = CHCR_TX(XMIT_SZ_8BIT),
287 .slave_id = SHDMA_SLAVE_SCIF5_RX,
289 .chcr = CHCR_RX(XMIT_SZ_8BIT),
292 .slave_id = SHDMA_SLAVE_SCIF6_TX,
294 .chcr = CHCR_TX(XMIT_SZ_8BIT),
297 .slave_id = SHDMA_SLAVE_SCIF6_RX,
299 .chcr = CHCR_RX(XMIT_SZ_8BIT),
302 .slave_id = SHDMA_SLAVE_SCIF7_TX,
304 .chcr = CHCR_TX(XMIT_SZ_8BIT),
307 .slave_id = SHDMA_SLAVE_SCIF7_RX,
309 .chcr = CHCR_RX(XMIT_SZ_8BIT),
312 .slave_id = SHDMA_SLAVE_SCIF8_TX,
314 .chcr = CHCR_TX(XMIT_SZ_8BIT),
317 .slave_id = SHDMA_SLAVE_SCIF8_RX,
319 .chcr = CHCR_RX(XMIT_SZ_8BIT),
322 .slave_id = SHDMA_SLAVE_SDHI0_TX,
324 .chcr = CHCR_TX(XMIT_SZ_16BIT),
327 .slave_id = SHDMA_SLAVE_SDHI0_RX,
329 .chcr = CHCR_RX(XMIT_SZ_16BIT),
332 .slave_id = SHDMA_SLAVE_SDHI1_TX,
334 .chcr = CHCR_TX(XMIT_SZ_16BIT),
337 .slave_id = SHDMA_SLAVE_SDHI1_RX,
339 .chcr = CHCR_RX(XMIT_SZ_16BIT),
342 .slave_id = SHDMA_SLAVE_SDHI2_TX,
344 .chcr = CHCR_TX(XMIT_SZ_16BIT),
347 .slave_id = SHDMA_SLAVE_SDHI2_RX,
349 .chcr = CHCR_RX(XMIT_SZ_16BIT),
352 .slave_id = SHDMA_SLAVE_MMCIF_TX,
354 .chcr = CHCR_TX(XMIT_SZ_32BIT),
357 .slave_id = SHDMA_SLAVE_MMCIF_RX,
359 .chcr = CHCR_RX(XMIT_SZ_32BIT),
364 #define DMAE_CHANNEL(_offset) \
366 .offset = _offset - 0x20, \
367 .dmars = _offset - 0x20 + 0x40, \
370 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
371 DMAE_CHANNEL(0x8000),
372 DMAE_CHANNEL(0x8080),
373 DMAE_CHANNEL(0x8100),
374 DMAE_CHANNEL(0x8180),
375 DMAE_CHANNEL(0x8200),
376 DMAE_CHANNEL(0x8280),
377 DMAE_CHANNEL(0x8300),
378 DMAE_CHANNEL(0x8380),
379 DMAE_CHANNEL(0x8400),
380 DMAE_CHANNEL(0x8480),
381 DMAE_CHANNEL(0x8500),
382 DMAE_CHANNEL(0x8580),
383 DMAE_CHANNEL(0x8600),
384 DMAE_CHANNEL(0x8680),
385 DMAE_CHANNEL(0x8700),
386 DMAE_CHANNEL(0x8780),
387 DMAE_CHANNEL(0x8800),
388 DMAE_CHANNEL(0x8880),
389 DMAE_CHANNEL(0x8900),
390 DMAE_CHANNEL(0x8980),
393 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
394 .slave = sh73a0_dmae_slaves,
395 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
396 .channel = sh73a0_dmae_channels,
397 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
398 .ts_low_shift = TS_LOW_SHIFT,
399 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
400 .ts_high_shift = TS_HI_SHIFT,
401 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
402 .ts_shift = dma_ts_shift,
403 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
404 .dmaor_init = DMAOR_DME,
407 static struct resource sh73a0_dmae_resources[] = {
408 DEFINE_RES_MEM(0xfe000020, 0x89e0),
411 .start = gic_spi(129),
413 .flags = IORESOURCE_IRQ,
416 /* IRQ for channels 0-19 */
417 .start = gic_spi(109),
419 .flags = IORESOURCE_IRQ,
423 static struct platform_device dma0_device = {
424 .name = "sh-dma-engine",
426 .resource = sh73a0_dmae_resources,
427 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
429 .platform_data = &sh73a0_dmae_platform_data,
434 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
436 .slave_id = SHDMA_SLAVE_FSI2A_RX,
438 .chcr = CHCR_RX(XMIT_SZ_32BIT),
439 .mid_rid = 0xd6, /* CHECK ME */
441 .slave_id = SHDMA_SLAVE_FSI2A_TX,
443 .chcr = CHCR_TX(XMIT_SZ_32BIT),
444 .mid_rid = 0xd5, /* CHECK ME */
446 .slave_id = SHDMA_SLAVE_FSI2C_RX,
448 .chcr = CHCR_RX(XMIT_SZ_32BIT),
449 .mid_rid = 0xda, /* CHECK ME */
451 .slave_id = SHDMA_SLAVE_FSI2C_TX,
453 .chcr = CHCR_TX(XMIT_SZ_32BIT),
454 .mid_rid = 0xd9, /* CHECK ME */
456 .slave_id = SHDMA_SLAVE_FSI2B_RX,
458 .chcr = CHCR_RX(XMIT_SZ_32BIT),
459 .mid_rid = 0x8e, /* CHECK ME */
461 .slave_id = SHDMA_SLAVE_FSI2B_TX,
463 .chcr = CHCR_RX(XMIT_SZ_32BIT),
464 .mid_rid = 0x8d, /* CHECK ME */
466 .slave_id = SHDMA_SLAVE_FSI2D_RX,
468 .chcr = CHCR_RX(XMIT_SZ_32BIT),
469 .mid_rid = 0x9a, /* CHECK ME */
473 #define MPDMA_CHANNEL(a, b, c) \
478 .chclr_offset = (0x220 - 0x20) + a \
481 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
482 MPDMA_CHANNEL(0x00, 0, 0),
483 MPDMA_CHANNEL(0x10, 0, 8),
484 MPDMA_CHANNEL(0x20, 4, 0),
485 MPDMA_CHANNEL(0x30, 4, 8),
486 MPDMA_CHANNEL(0x50, 8, 0),
487 MPDMA_CHANNEL(0x70, 8, 8),
490 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
491 .slave = sh73a0_mpdma_slaves,
492 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
493 .channel = sh73a0_mpdma_channels,
494 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
495 .ts_low_shift = TS_LOW_SHIFT,
496 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
497 .ts_high_shift = TS_HI_SHIFT,
498 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
499 .ts_shift = dma_ts_shift,
500 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
501 .dmaor_init = DMAOR_DME,
505 /* Resource order important! */
506 static struct resource sh73a0_mpdma_resources[] = {
507 /* Channel registers and DMAOR */
508 DEFINE_RES_MEM(0xec618020, 0x270),
510 DEFINE_RES_MEM(0xec619000, 0xc),
513 .start = gic_spi(181),
515 .flags = IORESOURCE_IRQ,
518 /* IRQ for channels 0-5 */
519 .start = gic_spi(175),
521 .flags = IORESOURCE_IRQ,
525 static struct platform_device mpdma0_device = {
526 .name = "sh-dma-engine",
528 .resource = sh73a0_mpdma_resources,
529 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
531 .platform_data = &sh73a0_mpdma_platform_data,
535 static struct resource pmu_resources[] = {
537 .start = gic_spi(55),
539 .flags = IORESOURCE_IRQ,
542 .start = gic_spi(56),
544 .flags = IORESOURCE_IRQ,
548 static struct platform_device pmu_device = {
551 .num_resources = ARRAY_SIZE(pmu_resources),
552 .resource = pmu_resources,
555 /* an IPMMU module for ICB */
556 static struct resource ipmmu_resources[] = {
557 DEFINE_RES_MEM(0xfe951000, 0x100),
560 static const char * const ipmmu_dev_names[] = {
561 "sh_mobile_lcdc_fb.0",
564 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
565 .dev_names = ipmmu_dev_names,
566 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
569 static struct platform_device ipmmu_device = {
573 .platform_data = &ipmmu_platform_data,
575 .resource = ipmmu_resources,
576 .num_resources = ARRAY_SIZE(ipmmu_resources),
579 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
580 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
583 static struct resource irqpin0_resources[] = {
584 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
585 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
586 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
587 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
588 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
589 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
590 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
591 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
592 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
593 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
594 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
595 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
596 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
599 static struct platform_device irqpin0_device = {
600 .name = "renesas_intc_irqpin",
602 .resource = irqpin0_resources,
603 .num_resources = ARRAY_SIZE(irqpin0_resources),
605 .platform_data = &irqpin0_platform_data,
609 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
610 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
611 .control_parent = true, /* Disable spurious IRQ10 */
614 static struct resource irqpin1_resources[] = {
615 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
616 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
617 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
618 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
619 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
620 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
621 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
622 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
623 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
624 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
625 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
626 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
627 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
630 static struct platform_device irqpin1_device = {
631 .name = "renesas_intc_irqpin",
633 .resource = irqpin1_resources,
634 .num_resources = ARRAY_SIZE(irqpin1_resources),
636 .platform_data = &irqpin1_platform_data,
640 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
641 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
644 static struct resource irqpin2_resources[] = {
645 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
646 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
647 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
648 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
649 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
650 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
651 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
652 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
653 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
654 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
655 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
656 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
657 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
660 static struct platform_device irqpin2_device = {
661 .name = "renesas_intc_irqpin",
663 .resource = irqpin2_resources,
664 .num_resources = ARRAY_SIZE(irqpin2_resources),
666 .platform_data = &irqpin2_platform_data,
670 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
671 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
674 static struct resource irqpin3_resources[] = {
675 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
676 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
677 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
678 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
679 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
680 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
681 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
682 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
683 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
684 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
685 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
686 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
687 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
690 static struct platform_device irqpin3_device = {
691 .name = "renesas_intc_irqpin",
693 .resource = irqpin3_resources,
694 .num_resources = ARRAY_SIZE(irqpin3_resources),
696 .platform_data = &irqpin3_platform_data,
700 static struct platform_device *sh73a0_early_devices[] __initdata = {
715 static struct platform_device *sh73a0_late_devices[] __initdata = {
730 #define SRCR2 IOMEM(0xe61580b0)
732 void __init sh73a0_add_standard_devices(void)
734 /* Clear software reset bit on SY-DMAC module */
735 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
737 platform_add_devices(sh73a0_early_devices,
738 ARRAY_SIZE(sh73a0_early_devices));
739 platform_add_devices(sh73a0_late_devices,
740 ARRAY_SIZE(sh73a0_late_devices));
743 void __init sh73a0_init_delay(void)
745 shmobile_init_delay();
748 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
749 void __init __weak sh73a0_register_twd(void) { }
751 void __init sh73a0_earlytimer_init(void)
755 shmobile_earlytimer_init();
756 sh73a0_register_twd();
759 void __init sh73a0_add_early_devices(void)
761 early_platform_add_devices(sh73a0_early_devices,
762 ARRAY_SIZE(sh73a0_early_devices));
764 /* setup early console here as well */
765 shmobile_setup_console();
770 void __init sh73a0_add_standard_devices_dt(void)
772 /* clocks are setup late during boot in the case of DT */
775 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
778 static const char *sh73a0_boards_compat_dt[] __initdata = {
783 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
784 .smp = smp_ops(sh73a0_smp_ops),
785 .map_io = sh73a0_map_io,
786 .init_early = sh73a0_init_delay,
787 .init_machine = sh73a0_add_standard_devices_dt,
788 .init_late = shmobile_init_late,
789 .dt_compat = sh73a0_boards_compat_dt,
791 #endif /* CONFIG_USE_OF */