2 * arch/arm/mach-spear3xx/spear320.c
4 * SPEAr320 machine source file
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/ptrace.h>
16 #include <mach/generic.h>
17 #include <mach/spear.h>
18 #include <plat/shirq.h>
20 /* pad multiplexing support */
21 /* muxing registers */
22 #define PAD_MUX_CONFIG_REG 0x0C
23 #define MODE_CONFIG_REG 0x10
26 #define AUTO_NET_SMII_MODE (1 << 0)
27 #define AUTO_NET_MII_MODE (1 << 1)
28 #define AUTO_EXP_MODE (1 << 2)
29 #define SMALL_PRINTERS_MODE (1 << 3)
32 struct pmx_mode auto_net_smii_mode = {
33 .id = AUTO_NET_SMII_MODE,
34 .name = "Automation Networking SMII Mode",
38 struct pmx_mode auto_net_mii_mode = {
39 .id = AUTO_NET_MII_MODE,
40 .name = "Automation Networking MII Mode",
44 struct pmx_mode auto_exp_mode = {
46 .name = "Automation Expanded Mode",
50 struct pmx_mode small_printers_mode = {
51 .id = SMALL_PRINTERS_MODE,
52 .name = "Small Printers Mode",
57 struct pmx_dev_mode pmx_clcd_modes[] = {
59 .ids = AUTO_NET_SMII_MODE,
64 struct pmx_dev pmx_clcd = {
66 .modes = pmx_clcd_modes,
67 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
71 struct pmx_dev_mode pmx_emi_modes[] = {
74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
78 struct pmx_dev pmx_emi = {
80 .modes = pmx_emi_modes,
81 .mode_count = ARRAY_SIZE(pmx_emi_modes),
85 struct pmx_dev_mode pmx_fsmc_modes[] = {
92 struct pmx_dev pmx_fsmc = {
94 .modes = pmx_fsmc_modes,
95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
99 struct pmx_dev_mode pmx_spp_modes[] = {
101 .ids = SMALL_PRINTERS_MODE,
106 struct pmx_dev pmx_spp = {
108 .modes = pmx_spp_modes,
109 .mode_count = ARRAY_SIZE(pmx_spp_modes),
113 struct pmx_dev_mode pmx_sdio_modes[] = {
115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
117 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
121 struct pmx_dev pmx_sdio = {
123 .modes = pmx_sdio_modes,
124 .mode_count = ARRAY_SIZE(pmx_sdio_modes),
128 struct pmx_dev_mode pmx_i2s_modes[] = {
130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
131 .mask = PMX_UART0_MODEM_MASK,
135 struct pmx_dev pmx_i2s = {
137 .modes = pmx_i2s_modes,
138 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
142 struct pmx_dev_mode pmx_uart1_modes[] = {
145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
149 struct pmx_dev pmx_uart1 = {
151 .modes = pmx_uart1_modes,
152 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
156 struct pmx_dev_mode pmx_uart1_modem_modes[] = {
158 .ids = AUTO_EXP_MODE,
159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
162 .ids = SMALL_PRINTERS_MODE,
163 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
164 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
168 struct pmx_dev pmx_uart1_modem = {
169 .name = "uart1_modem",
170 .modes = pmx_uart1_modem_modes,
171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
175 struct pmx_dev_mode pmx_uart2_modes[] = {
178 .mask = PMX_FIRDA_MASK,
182 struct pmx_dev pmx_uart2 = {
184 .modes = pmx_uart2_modes,
185 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
189 struct pmx_dev_mode pmx_touchscreen_modes[] = {
191 .ids = AUTO_NET_SMII_MODE,
192 .mask = PMX_SSP_CS_MASK,
196 struct pmx_dev pmx_touchscreen = {
197 .name = "touchscreen",
198 .modes = pmx_touchscreen_modes,
199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
203 struct pmx_dev_mode pmx_can_modes[] = {
205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
207 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
211 struct pmx_dev pmx_can = {
213 .modes = pmx_can_modes,
214 .mode_count = ARRAY_SIZE(pmx_can_modes),
218 struct pmx_dev_mode pmx_sdio_led_modes[] = {
220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
221 .mask = PMX_SSP_CS_MASK,
225 struct pmx_dev pmx_sdio_led = {
227 .modes = pmx_sdio_led_modes,
228 .mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
232 struct pmx_dev_mode pmx_pwm0_modes[] = {
234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
235 .mask = PMX_UART0_MODEM_MASK,
237 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
238 .mask = PMX_MII_MASK,
242 struct pmx_dev pmx_pwm0 = {
244 .modes = pmx_pwm0_modes,
245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
249 struct pmx_dev_mode pmx_pwm1_modes[] = {
251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
252 .mask = PMX_UART0_MODEM_MASK,
254 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
255 .mask = PMX_MII_MASK,
259 struct pmx_dev pmx_pwm1 = {
261 .modes = pmx_pwm1_modes,
262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
266 struct pmx_dev_mode pmx_pwm2_modes[] = {
268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
269 .mask = PMX_SSP_CS_MASK,
271 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
272 .mask = PMX_MII_MASK,
276 struct pmx_dev pmx_pwm2 = {
278 .modes = pmx_pwm2_modes,
279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
283 struct pmx_dev_mode pmx_pwm3_modes[] = {
285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
286 .mask = PMX_MII_MASK,
290 struct pmx_dev pmx_pwm3 = {
292 .modes = pmx_pwm3_modes,
293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
297 struct pmx_dev_mode pmx_ssp1_modes[] = {
299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
300 .mask = PMX_MII_MASK,
304 struct pmx_dev pmx_ssp1 = {
306 .modes = pmx_ssp1_modes,
307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
311 struct pmx_dev_mode pmx_ssp2_modes[] = {
313 .ids = AUTO_NET_SMII_MODE,
314 .mask = PMX_MII_MASK,
318 struct pmx_dev pmx_ssp2 = {
320 .modes = pmx_ssp2_modes,
321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
325 struct pmx_dev_mode pmx_mii1_modes[] = {
327 .ids = AUTO_NET_MII_MODE,
332 struct pmx_dev pmx_mii1 = {
334 .modes = pmx_mii1_modes,
335 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
339 struct pmx_dev_mode pmx_smii0_modes[] = {
341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
342 .mask = PMX_MII_MASK,
346 struct pmx_dev pmx_smii0 = {
348 .modes = pmx_smii0_modes,
349 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
353 struct pmx_dev_mode pmx_smii1_modes[] = {
355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
356 .mask = PMX_MII_MASK,
360 struct pmx_dev pmx_smii1 = {
362 .modes = pmx_smii1_modes,
363 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
367 struct pmx_dev_mode pmx_i2c1_modes[] = {
369 .ids = AUTO_EXP_MODE,
374 struct pmx_dev pmx_i2c1 = {
376 .modes = pmx_i2c1_modes,
377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
381 /* pmx driver structure */
382 struct pmx_driver pmx_driver = {
383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
387 /* Add spear320 specific devices here */
389 /* spear3xx shared irq */
390 struct shirq_dev_config shirq_ras1_config[] = {
393 .status_mask = EMI_IRQ_MASK,
394 .clear_mask = EMI_IRQ_MASK,
397 .status_mask = CLCD_IRQ_MASK,
398 .clear_mask = CLCD_IRQ_MASK,
401 .status_mask = SPP_IRQ_MASK,
402 .clear_mask = SPP_IRQ_MASK,
406 struct spear_shirq shirq_ras1 = {
407 .irq = IRQ_GEN_RAS_1,
408 .dev_config = shirq_ras1_config,
409 .dev_count = ARRAY_SIZE(shirq_ras1_config),
412 .status_reg = INT_STS_MASK_REG,
413 .status_reg_mask = SHIRQ_RAS1_MASK,
414 .clear_reg = INT_CLR_MASK_REG,
419 struct shirq_dev_config shirq_ras3_config[] = {
422 .enb_mask = GPIO_IRQ_MASK,
423 .status_mask = GPIO_IRQ_MASK,
424 .clear_mask = GPIO_IRQ_MASK,
426 .virq = VIRQ_I2S_PLAY,
427 .enb_mask = I2S_PLAY_IRQ_MASK,
428 .status_mask = I2S_PLAY_IRQ_MASK,
429 .clear_mask = I2S_PLAY_IRQ_MASK,
431 .virq = VIRQ_I2S_REC,
432 .enb_mask = I2S_REC_IRQ_MASK,
433 .status_mask = I2S_REC_IRQ_MASK,
434 .clear_mask = I2S_REC_IRQ_MASK,
438 struct spear_shirq shirq_ras3 = {
439 .irq = IRQ_GEN_RAS_3,
440 .dev_config = shirq_ras3_config,
441 .dev_count = ARRAY_SIZE(shirq_ras3_config),
443 .enb_reg = INT_ENB_MASK_REG,
445 .status_reg = INT_STS_MASK_REG,
446 .status_reg_mask = SHIRQ_RAS3_MASK,
447 .clear_reg = INT_CLR_MASK_REG,
452 struct shirq_dev_config shirq_intrcomm_ras_config[] = {
455 .status_mask = CAN_U_IRQ_MASK,
456 .clear_mask = CAN_U_IRQ_MASK,
459 .status_mask = CAN_L_IRQ_MASK,
460 .clear_mask = CAN_L_IRQ_MASK,
463 .status_mask = UART1_IRQ_MASK,
464 .clear_mask = UART1_IRQ_MASK,
467 .status_mask = UART2_IRQ_MASK,
468 .clear_mask = UART2_IRQ_MASK,
471 .status_mask = SSP1_IRQ_MASK,
472 .clear_mask = SSP1_IRQ_MASK,
475 .status_mask = SSP2_IRQ_MASK,
476 .clear_mask = SSP2_IRQ_MASK,
479 .status_mask = SMII0_IRQ_MASK,
480 .clear_mask = SMII0_IRQ_MASK,
482 .virq = VIRQ_MII1_SMII1,
483 .status_mask = MII1_SMII1_IRQ_MASK,
484 .clear_mask = MII1_SMII1_IRQ_MASK,
486 .virq = VIRQ_WAKEUP_SMII0,
487 .status_mask = WAKEUP_SMII0_IRQ_MASK,
488 .clear_mask = WAKEUP_SMII0_IRQ_MASK,
490 .virq = VIRQ_WAKEUP_MII1_SMII1,
491 .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
492 .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
495 .status_mask = I2C1_IRQ_MASK,
496 .clear_mask = I2C1_IRQ_MASK,
500 struct spear_shirq shirq_intrcomm_ras = {
501 .irq = IRQ_INTRCOMM_RAS_ARM,
502 .dev_config = shirq_intrcomm_ras_config,
503 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
506 .status_reg = INT_STS_MASK_REG,
507 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
508 .clear_reg = INT_CLR_MASK_REG,
513 /* spear320 routines */
514 void __init spear320_init(void)
519 /* call spear3xx family common init function */
522 /* shared irq registration */
523 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
526 shirq_ras1.regs.base = base;
527 ret = spear_shirq_register(&shirq_ras1);
529 printk(KERN_ERR "Error registering Shared IRQ 1\n");
532 shirq_ras3.regs.base = base;
533 ret = spear_shirq_register(&shirq_ras3);
535 printk(KERN_ERR "Error registering Shared IRQ 3\n");
538 shirq_intrcomm_ras.regs.base = base;
539 ret = spear_shirq_register(&shirq_intrcomm_ras);
541 printk(KERN_ERR "Error registering Shared IRQ 4\n");
545 void spear320_pmx_init(void)
547 spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
548 SPEAR320_SOC_CONFIG_SIZE);