2 * arch/arm/mach-tegra/flowctrl.c
4 * functions and macros to control the flowcontroller
6 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/cpumask.h>
22 #include <linux/init.h>
24 #include <linux/kernel.h>
26 #include <soc/tegra/fuse.h>
31 static u8 flowctrl_offset_halt_cpu[] = {
32 FLOW_CTRL_HALT_CPU0_EVENTS,
33 FLOW_CTRL_HALT_CPU1_EVENTS,
34 FLOW_CTRL_HALT_CPU1_EVENTS + 8,
35 FLOW_CTRL_HALT_CPU1_EVENTS + 16,
38 static u8 flowctrl_offset_cpu_csr[] = {
41 FLOW_CTRL_CPU1_CSR + 8,
42 FLOW_CTRL_CPU1_CSR + 16,
45 static void flowctrl_update(u8 offset, u32 value)
47 void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
51 /* ensure the update has reached the flow controller */
56 u32 flowctrl_read_cpu_csr(unsigned int cpuid)
58 u8 offset = flowctrl_offset_cpu_csr[cpuid];
59 void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
64 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
66 return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
69 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
71 return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
74 void flowctrl_cpu_suspend_enter(unsigned int cpuid)
79 reg = flowctrl_read_cpu_csr(cpuid);
80 switch (tegra_get_chip_id()) {
82 /* clear wfe bitmap */
83 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
84 /* clear wfi bitmap */
85 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
86 /* pwr gating on wfe */
87 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
92 /* clear wfe bitmap */
93 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
94 /* clear wfi bitmap */
95 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
96 /* pwr gating on wfi */
97 reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
100 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
101 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
102 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
103 flowctrl_write_cpu_csr(cpuid, reg);
105 for (i = 0; i < num_possible_cpus(); i++) {
108 reg = flowctrl_read_cpu_csr(i);
109 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
110 reg |= FLOW_CTRL_CSR_INTR_FLAG;
111 flowctrl_write_cpu_csr(i, reg);
115 void flowctrl_cpu_suspend_exit(unsigned int cpuid)
119 /* Disable powergating via flow controller for CPU0 */
120 reg = flowctrl_read_cpu_csr(cpuid);
121 switch (tegra_get_chip_id()) {
123 /* clear wfe bitmap */
124 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
125 /* clear wfi bitmap */
126 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
131 /* clear wfe bitmap */
132 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
133 /* clear wfi bitmap */
134 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
137 reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
138 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
139 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
140 flowctrl_write_cpu_csr(cpuid, reg);