2 * arch/arm/mach-tegra/include/mach/debug-macro.S
4 * Copyright (C) 2010,2011 Google, Inc.
5 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 * Doug Anderson <dianders@chromium.org>
11 * Stephen Warren <swarren@nvidia.com>
13 * Portions based on mach-omap2's debug-macro.S
14 * Copyright (C) 1994-1999 Russell King
16 * This software is licensed under the terms of the GNU General Public
17 * License version 2, as published by the Free Software Foundation, and
18 * may be copied, distributed, and modified under those terms.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 #include <linux/serial_reg.h>
29 #include "../../iomap.h"
33 #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
34 #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
35 #define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
36 #define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
37 #define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
38 #define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
39 #define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
40 #define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
42 #define checkuart(rp, rv, lhu, bit, uart) \
43 /* Load address of CLK_RST register */ \
44 movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
45 movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
46 /* Load value from CLK_RST register */ \
48 /* Test UART's reset bit */ \
49 tst rp, #(1 << bit) ; \
50 /* If set, can't use UART; jump to save no UART */ \
52 /* Load address of CLK_OUT_ENB register */ \
53 movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
54 movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
55 /* Load value from CLK_OUT_ENB register */ \
57 /* Test UART's clock enable bit */ \
58 tst rp, #(1 << bit) ; \
59 /* If clear, can't use UART; jump to save no UART */ \
61 /* Passed all tests, load address of UART registers */ \
62 movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
63 movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
64 /* Jump to save UART address */ \
67 .macro addruart, rp, rv, tmp
68 adr \rp, 99f @ actual addr of 99f
69 ldr \rv, [\rp] @ linked addr is stored there
70 sub \rv, \rv, \rp @ offset between the two
71 ldr \rp, [\rp, #4] @ linked tegra_uart_config
72 sub \tmp, \rp, \rv @ actual tegra_uart_config
73 ldr \rp, [\tmp] @ Load tegra_uart_config
74 cmp \rp, #1 @ needs initialization?
75 bne 100f @ no; go load the addresses
76 mov \rv, #0 @ yes; record init is done
79 #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
81 10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
82 movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
83 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
84 ubfx \rv, \rp, #18, #2 @ 19:18 are console type
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
86 beq 11f @ some boards swap the meaning
87 cmp \rv, #3 @ so accept either
89 11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
103 #if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
104 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
105 /* Check UART A validity */
106 20: checkuart(\rp, \rv, L, 6, A)
109 #if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
110 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
111 /* Check UART B validity */
112 21: checkuart(\rp, \rv, L, 7, B)
115 #if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
116 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
117 /* Check UART C validity */
118 22: checkuart(\rp, \rv, H, 23, C)
121 #if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
122 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
123 /* Check UART D validity */
124 23: checkuart(\rp, \rv, U, 1, D)
127 #if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
128 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
129 /* Check UART E validity */
131 checkuart(\rp, \rv, U, 2, E)
134 /* No valid UART found */
138 /* Record whichever UART we chose */
139 91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
140 cmp \rp, #0 @ Valid UART address?
141 bne 92f @ Yes, go process it
142 str \rp, [\tmp, #8] @ Store 0 in tegra_uart_phys
144 92: sub \rv, \rp, #IO_APB_PHYS @ Calculate virt address
145 add \rv, \rv, #IO_APB_VIRT
146 str \rv, [\tmp, #8] @ Store in tegra_uart_virt
147 movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
148 movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
149 ldr \rv, [\rv, #0] @ Load HIDREV
150 ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
151 cmp \rv, #0x20 @ Tegra20?
152 moveq \rv, #0x75 @ Tegra20 divisor
153 movne \rv, #0xdd @ Tegra30 divisor
154 str \rv, [\tmp, #12] @ Save divisor to scratch
155 /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
156 mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
157 str \rv, [\rp, #UART_LCR << UART_SHIFT]
158 /* uart[UART_DLL] = div & 0xff; */
161 str \rv, [\rp, #UART_DLL << UART_SHIFT]
162 /* uart[UART_DLM] = div >> 8; */
165 str \rv, [\rp, #UART_DLM << UART_SHIFT]
166 /* uart[UART_LCR] = UART_LCR_WLEN8; */
167 mov \rv, #UART_LCR_WLEN8
168 str \rv, [\rp, #UART_LCR << UART_SHIFT]
173 .word tegra_uart_config
176 /* Load previously selected UART address */
177 100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
178 ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
182 * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
183 * check to make sure that the UART address is actually valid.
186 .macro senduart, rd, rx
188 strneb \rd, [\rx, #UART_TX << UART_SHIFT]
192 .macro busyuart, rd, rx
195 1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
196 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
197 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
202 .macro waituart, rd, rx
206 1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
207 tst \rd, #UART_MSR_CTS