2 * arch/arm/mach-tegra/pci.c
4 * PCIe host controller driver for TEGRA(2) SOCs
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
12 * Bits taken from arch/arm/mach-dove/pcie.c
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/export.h>
37 #include <asm/sizes.h>
38 #include <asm/mach/pci.h>
40 #include <mach/iomap.h>
42 #include <mach/powergate.h>
46 /* register definitions */
47 #define AFI_OFFSET 0x3800
48 #define PADS_OFFSET 0x3000
49 #define RP0_OFFSET 0x0000
50 #define RP1_OFFSET 0x1000
52 #define AFI_AXI_BAR0_SZ 0x00
53 #define AFI_AXI_BAR1_SZ 0x04
54 #define AFI_AXI_BAR2_SZ 0x08
55 #define AFI_AXI_BAR3_SZ 0x0c
56 #define AFI_AXI_BAR4_SZ 0x10
57 #define AFI_AXI_BAR5_SZ 0x14
59 #define AFI_AXI_BAR0_START 0x18
60 #define AFI_AXI_BAR1_START 0x1c
61 #define AFI_AXI_BAR2_START 0x20
62 #define AFI_AXI_BAR3_START 0x24
63 #define AFI_AXI_BAR4_START 0x28
64 #define AFI_AXI_BAR5_START 0x2c
66 #define AFI_FPCI_BAR0 0x30
67 #define AFI_FPCI_BAR1 0x34
68 #define AFI_FPCI_BAR2 0x38
69 #define AFI_FPCI_BAR3 0x3c
70 #define AFI_FPCI_BAR4 0x40
71 #define AFI_FPCI_BAR5 0x44
73 #define AFI_CACHE_BAR0_SZ 0x48
74 #define AFI_CACHE_BAR0_ST 0x4c
75 #define AFI_CACHE_BAR1_SZ 0x50
76 #define AFI_CACHE_BAR1_ST 0x54
78 #define AFI_MSI_BAR_SZ 0x60
79 #define AFI_MSI_FPCI_BAR_ST 0x64
80 #define AFI_MSI_AXI_BAR_ST 0x68
82 #define AFI_CONFIGURATION 0xac
83 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
85 #define AFI_FPCI_ERROR_MASKS 0xb0
87 #define AFI_INTR_MASK 0xb4
88 #define AFI_INTR_MASK_INT_MASK (1 << 0)
89 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
91 #define AFI_INTR_CODE 0xb8
92 #define AFI_INTR_CODE_MASK 0xf
93 #define AFI_INTR_MASTER_ABORT 4
94 #define AFI_INTR_LEGACY 6
96 #define AFI_INTR_SIGNATURE 0xbc
97 #define AFI_SM_INTR_ENABLE 0xc4
99 #define AFI_AFI_INTR_ENABLE 0xc8
100 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
101 #define AFI_INTR_EN_INI_DECERR (1 << 1)
102 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
103 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
104 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
105 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
106 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
107 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
109 #define AFI_PCIE_CONFIG 0x0f8
110 #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
111 #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
116 #define AFI_FUSE 0x104
117 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
119 #define AFI_PEX0_CTRL 0x110
120 #define AFI_PEX1_CTRL 0x118
121 #define AFI_PEX_CTRL_RST (1 << 0)
122 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
124 #define RP_VEND_XP 0x00000F00
125 #define RP_VEND_XP_DL_UP (1 << 30)
127 #define RP_LINK_CONTROL_STATUS 0x00000090
128 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
130 #define PADS_CTL_SEL 0x0000009C
132 #define PADS_CTL 0x000000A0
133 #define PADS_CTL_IDDQ_1L (1 << 0)
134 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
135 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
137 #define PADS_PLL_CTL 0x000000B8
138 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
139 #define PADS_PLL_CTL_LOCKDET (1 << 8)
140 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
141 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
142 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
143 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
144 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
145 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
146 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
148 /* PMC access is required for PCIE xclk (un)clamping */
149 #define PMC_SCRATCH42 0x144
150 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
152 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
154 #define pmc_writel(value, reg) \
155 __raw_writel(value, reg_pmc_base + (reg))
156 #define pmc_readl(reg) \
157 __raw_readl(reg_pmc_base + (reg))
160 * Tegra2 defines 1GB in the AXI address map for PCIe.
162 * That address space is split into different regions, with sizes and
163 * offsets as follows:
165 * 0x80000000 - 0x80003fff - PCI controller registers
166 * 0x80004000 - 0x80103fff - PCI configuration space
167 * 0x80104000 - 0x80203fff - PCI extended configuration space
168 * 0x80203fff - 0x803fffff - unused
169 * 0x80400000 - 0x8040ffff - downstream IO
170 * 0x80410000 - 0x8fffffff - unused
171 * 0x90000000 - 0x9fffffff - non-prefetchable memory
172 * 0xa0000000 - 0xbfffffff - prefetchable memory
174 #define TEGRA_PCIE_BASE 0x80000000
176 #define PCIE_REGS_SZ SZ_16K
177 #define PCIE_CFG_OFF PCIE_REGS_SZ
178 #define PCIE_CFG_SZ SZ_1M
179 #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
180 #define PCIE_EXT_CFG_SZ SZ_1M
181 #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
183 #define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M)
184 #define MMIO_SIZE SZ_64K
185 #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
186 #define MEM_SIZE_0 SZ_128M
187 #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
188 #define MEM_SIZE_1 SZ_128M
189 #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
190 #define PREFETCH_MEM_SIZE_0 SZ_128M
191 #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
192 #define PREFETCH_MEM_SIZE_1 SZ_128M
194 #define PCIE_CONF_BUS(b) ((b) << 16)
195 #define PCIE_CONF_DEV(d) ((d) << 11)
196 #define PCIE_CONF_FUNC(f) ((f) << 8)
197 #define PCIE_CONF_REG(r) \
198 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
200 struct tegra_pcie_port {
207 char io_space_name[16];
208 char mem_space_name[16];
209 char prefetch_space_name[20];
210 struct resource res[3];
213 struct tegra_pcie_info {
214 struct tegra_pcie_port port[2];
218 struct resource res_mmio;
222 struct clk *pcie_xclk;
226 static struct tegra_pcie_info tegra_pcie = {
230 .end = MMIO_BASE + MMIO_SIZE - 1,
231 .flags = IORESOURCE_MEM,
235 void __iomem *tegra_pcie_io_base;
236 EXPORT_SYMBOL(tegra_pcie_io_base);
238 static inline void afi_writel(u32 value, unsigned long offset)
240 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
243 static inline u32 afi_readl(unsigned long offset)
245 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
248 static inline void pads_writel(u32 value, unsigned long offset)
250 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
253 static inline u32 pads_readl(unsigned long offset)
255 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
258 static struct tegra_pcie_port *bus_to_port(int bus)
262 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
263 int rbus = tegra_pcie.port[i].root_bus_nr;
264 if (rbus != -1 && rbus == bus)
268 return i >= 0 ? tegra_pcie.port + i : NULL;
271 static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
272 int where, int size, u32 *val)
274 struct tegra_pcie_port *pp = bus_to_port(bus->number);
280 return PCIBIOS_DEVICE_NOT_FOUND;
283 addr = pp->base + (where & ~0x3);
285 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
286 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
287 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
288 PCIE_CONF_REG(where));
294 *val = (*val >> (8 * (where & 3))) & 0xff;
296 *val = (*val >> (8 * (where & 3))) & 0xffff;
298 return PCIBIOS_SUCCESSFUL;
301 static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
302 int where, int size, u32 val)
304 struct tegra_pcie_port *pp = bus_to_port(bus->number);
312 return PCIBIOS_DEVICE_NOT_FOUND;
314 addr = pp->base + (where & ~0x3);
316 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
317 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
318 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
319 PCIE_CONF_REG(where));
324 return PCIBIOS_SUCCESSFUL;
328 mask = ~(0xffff << ((where & 0x3) * 8));
330 mask = ~(0xff << ((where & 0x3) * 8));
332 return PCIBIOS_BAD_REGISTER_NUMBER;
334 tmp = readl(addr) & mask;
335 tmp |= val << ((where & 0x3) * 8);
338 return PCIBIOS_SUCCESSFUL;
341 static struct pci_ops tegra_pcie_ops = {
342 .read = tegra_pcie_read_conf,
343 .write = tegra_pcie_write_conf,
346 static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev)
350 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
351 pci_read_config_word(dev, PCI_COMMAND, ®);
352 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
353 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
354 pci_write_config_word(dev, PCI_COMMAND, reg);
357 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
359 /* Tegra PCIE root complex wrongly reports device class */
360 static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev)
362 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
364 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
365 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
367 /* Tegra PCIE requires relaxed ordering */
368 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
371 int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
374 dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
378 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
379 val16 |= PCI_EXP_DEVCTL_RELAX_EN;
380 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
382 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
384 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
386 struct tegra_pcie_port *pp;
388 if (nr >= tegra_pcie.num_ports)
391 pp = tegra_pcie.port + nr;
392 pp->root_bus_nr = sys->busnr;
397 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
398 "PCIe %d I/O", pp->index);
399 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
400 pp->res[0].name = pp->io_space_name;
401 if (pp->index == 0) {
402 pp->res[0].start = PCIBIOS_MIN_IO;
403 pp->res[0].end = pp->res[0].start + SZ_32K - 1;
405 pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
406 pp->res[0].end = IO_SPACE_LIMIT;
408 pp->res[0].flags = IORESOURCE_IO;
409 if (request_resource(&ioport_resource, &pp->res[0]))
410 panic("Request PCIe IO resource failed\n");
411 pci_add_resource(&sys->resources, &pp->res[0]);
416 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
417 "PCIe %d MEM", pp->index);
418 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
419 pp->res[1].name = pp->mem_space_name;
420 if (pp->index == 0) {
421 pp->res[1].start = MEM_BASE_0;
422 pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
424 pp->res[1].start = MEM_BASE_1;
425 pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
427 pp->res[1].flags = IORESOURCE_MEM;
428 if (request_resource(&iomem_resource, &pp->res[1]))
429 panic("Request PCIe Memory resource failed\n");
430 pci_add_resource(&sys->resources, &pp->res[1]);
433 * IORESOURCE_MEM | IORESOURCE_PREFETCH
435 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
436 "PCIe %d PREFETCH MEM", pp->index);
437 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
438 pp->res[2].name = pp->prefetch_space_name;
439 if (pp->index == 0) {
440 pp->res[2].start = PREFETCH_MEM_BASE_0;
441 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
443 pp->res[2].start = PREFETCH_MEM_BASE_1;
444 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
446 pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (request_resource(&iomem_resource, &pp->res[2]))
448 panic("Request PCIe Prefetch Memory resource failed\n");
449 pci_add_resource(&sys->resources, &pp->res[2]);
454 static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
456 return INT_PCIE_INTR;
459 static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
460 struct pci_sys_data *sys)
462 struct tegra_pcie_port *pp;
464 if (nr >= tegra_pcie.num_ports)
467 pp = tegra_pcie.port + nr;
468 pp->root_bus_nr = sys->busnr;
470 return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
474 static struct hw_pci tegra_pcie_hw __initdata = {
476 .setup = tegra_pcie_setup,
477 .scan = tegra_pcie_scan_bus,
478 .swizzle = pci_std_swizzle,
479 .map_irq = tegra_pcie_map_irq,
483 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
485 const char *err_msg[] = {
492 "Response decoding error",
493 "AXI response decoding error",
494 "Transcation timeout",
499 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
500 signature = afi_readl(AFI_INTR_SIGNATURE);
501 afi_writel(0, AFI_INTR_CODE);
503 if (code == AFI_INTR_LEGACY)
506 if (code >= ARRAY_SIZE(err_msg))
510 * do not pollute kernel log with master abort reports since they
511 * happen a lot during enumeration
513 if (code == AFI_INTR_MASTER_ABORT)
514 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
516 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
521 static void tegra_pcie_setup_translations(void)
527 /* Bar 0: config Bar */
528 fpci_bar = ((u32)0xfdff << 16);
530 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
531 afi_writel(axi_address, AFI_AXI_BAR0_START);
532 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
533 afi_writel(fpci_bar, AFI_FPCI_BAR0);
535 /* Bar 1: extended config Bar */
536 fpci_bar = ((u32)0xfe1 << 20);
537 size = PCIE_EXT_CFG_SZ;
538 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
539 afi_writel(axi_address, AFI_AXI_BAR1_START);
540 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
541 afi_writel(fpci_bar, AFI_FPCI_BAR1);
543 /* Bar 2: downstream IO bar */
544 fpci_bar = ((__u32)0xfdfc << 16);
546 axi_address = MMIO_BASE;
547 afi_writel(axi_address, AFI_AXI_BAR2_START);
548 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
549 afi_writel(fpci_bar, AFI_FPCI_BAR2);
551 /* Bar 3: prefetchable memory BAR */
552 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
553 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
554 axi_address = PREFETCH_MEM_BASE_0;
555 afi_writel(axi_address, AFI_AXI_BAR3_START);
556 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
557 afi_writel(fpci_bar, AFI_FPCI_BAR3);
559 /* Bar 4: non prefetchable memory BAR */
560 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
561 size = MEM_SIZE_0 + MEM_SIZE_1;
562 axi_address = MEM_BASE_0;
563 afi_writel(axi_address, AFI_AXI_BAR4_START);
564 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
565 afi_writel(fpci_bar, AFI_FPCI_BAR4);
567 /* Bar 5: NULL out the remaining BAR as it is not used */
571 afi_writel(axi_address, AFI_AXI_BAR5_START);
572 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
573 afi_writel(fpci_bar, AFI_FPCI_BAR5);
575 /* map all upstream transactions as uncached */
576 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
577 afi_writel(0, AFI_CACHE_BAR0_SZ);
578 afi_writel(0, AFI_CACHE_BAR1_ST);
579 afi_writel(0, AFI_CACHE_BAR1_SZ);
582 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
583 afi_writel(0, AFI_MSI_BAR_SZ);
584 afi_writel(0, AFI_MSI_AXI_BAR_ST);
585 afi_writel(0, AFI_MSI_BAR_SZ);
588 static int tegra_pcie_enable_controller(void)
593 /* Enable slot clock and pulse the reset signals */
594 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
595 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
596 afi_writel(val, reg);
597 val &= ~AFI_PEX_CTRL_RST;
598 afi_writel(val, reg);
600 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
601 afi_writel(val, reg);
604 /* Enable dual controller and both ports */
605 val = afi_readl(AFI_PCIE_CONFIG);
606 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
607 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
608 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
609 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
610 afi_writel(val, AFI_PCIE_CONFIG);
612 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
613 afi_writel(val, AFI_FUSE);
615 /* Initialze internal PHY, enable up to 16 PCIE lanes */
616 pads_writel(0x0, PADS_CTL_SEL);
618 /* override IDDQ to 1 on all 4 lanes */
619 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
620 pads_writel(val, PADS_CTL);
623 * set up PHY PLL inputs select PLLE output as refclock,
624 * set TX ref sel to div10 (not div5)
626 val = pads_readl(PADS_PLL_CTL);
627 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
628 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
629 pads_writel(val, PADS_PLL_CTL);
631 /* take PLL out of reset */
632 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
633 pads_writel(val, PADS_PLL_CTL);
636 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
637 * This doesn't exist in the documentation
639 pads_writel(0xfa5cfa5c, 0xc8);
641 /* Wait for the PLL to lock */
644 val = pads_readl(PADS_PLL_CTL);
646 if (--timeout == 0) {
647 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
650 } while (!(val & PADS_PLL_CTL_LOCKDET));
652 /* turn off IDDQ override */
653 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
654 pads_writel(val, PADS_CTL);
656 /* enable TX/RX data */
657 val = pads_readl(PADS_CTL);
658 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
659 pads_writel(val, PADS_CTL);
661 /* Take the PCIe interface module out of reset */
662 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
664 /* Finally enable PCIe */
665 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
666 afi_writel(val, AFI_CONFIGURATION);
668 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
669 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
670 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
671 afi_writel(val, AFI_AFI_INTR_ENABLE);
672 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
674 /* FIXME: No MSI for now, only INT */
675 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
677 /* Disable all execptions */
678 afi_writel(0, AFI_FPCI_ERROR_MASKS);
683 static void tegra_pcie_xclk_clamp(bool clamp)
687 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
690 reg |= PMC_SCRATCH42_PCX_CLAMP;
692 pmc_writel(reg, PMC_SCRATCH42);
695 static void tegra_pcie_power_off(void)
697 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
698 tegra_periph_reset_assert(tegra_pcie.afi_clk);
699 tegra_periph_reset_assert(tegra_pcie.pex_clk);
701 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
702 tegra_pcie_xclk_clamp(true);
705 static int tegra_pcie_power_regate(void)
709 tegra_pcie_power_off();
711 tegra_pcie_xclk_clamp(true);
713 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
714 tegra_periph_reset_assert(tegra_pcie.afi_clk);
716 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
719 pr_err("PCIE: powerup sequence failed: %d\n", err);
723 tegra_periph_reset_deassert(tegra_pcie.afi_clk);
725 tegra_pcie_xclk_clamp(false);
727 clk_enable(tegra_pcie.afi_clk);
728 clk_enable(tegra_pcie.pex_clk);
729 return clk_enable(tegra_pcie.pll_e);
732 static int tegra_pcie_clocks_get(void)
736 tegra_pcie.pex_clk = clk_get(NULL, "pex");
737 if (IS_ERR(tegra_pcie.pex_clk))
738 return PTR_ERR(tegra_pcie.pex_clk);
740 tegra_pcie.afi_clk = clk_get(NULL, "afi");
741 if (IS_ERR(tegra_pcie.afi_clk)) {
742 err = PTR_ERR(tegra_pcie.afi_clk);
746 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
747 if (IS_ERR(tegra_pcie.pcie_xclk)) {
748 err = PTR_ERR(tegra_pcie.pcie_xclk);
752 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
753 if (IS_ERR(tegra_pcie.pll_e)) {
754 err = PTR_ERR(tegra_pcie.pll_e);
761 clk_put(tegra_pcie.pcie_xclk);
763 clk_put(tegra_pcie.afi_clk);
765 clk_put(tegra_pcie.pex_clk);
770 static void tegra_pcie_clocks_put(void)
772 clk_put(tegra_pcie.pll_e);
773 clk_put(tegra_pcie.pcie_xclk);
774 clk_put(tegra_pcie.afi_clk);
775 clk_put(tegra_pcie.pex_clk);
778 static int __init tegra_pcie_get_resources(void)
780 struct resource *res_mmio = &tegra_pcie.res_mmio;
783 err = tegra_pcie_clocks_get();
785 pr_err("PCIE: failed to get clocks: %d\n", err);
789 err = tegra_pcie_power_regate();
791 pr_err("PCIE: failed to power up: %d\n", err);
795 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
796 if (tegra_pcie.regs == NULL) {
797 pr_err("PCIE: Failed to map PCI/AFI registers\n");
802 err = request_resource(&iomem_resource, res_mmio);
804 pr_err("PCIE: Failed to request resources: %d\n", err);
808 tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
809 resource_size(res_mmio));
810 if (tegra_pcie_io_base == NULL) {
811 pr_err("PCIE: Failed to map IO\n");
816 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
817 IRQF_SHARED, "PCIE", &tegra_pcie);
819 pr_err("PCIE: Failed to register IRQ: %d\n", err);
822 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
827 iounmap(tegra_pcie_io_base);
829 release_resource(&tegra_pcie.res_mmio);
831 iounmap(tegra_pcie.regs);
833 tegra_pcie_power_off();
835 tegra_pcie_clocks_put();
841 * FIXME: If there are no PCIe cards attached, then calling this function
842 * can result in the increase of the bootup time as there are big timeout
845 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
846 static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
854 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
856 reg = readl(pp->base + RP_VEND_XP);
858 if (reg & RP_VEND_XP_DL_UP)
866 pr_err("PCIE: port %d: link down, retrying\n", idx);
870 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
872 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
874 if (reg & 0x20000000)
882 /* Pulse the PEX reset */
883 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
884 afi_writel(reg, reset_reg);
886 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
887 afi_writel(reg, reset_reg);
895 static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
897 struct tegra_pcie_port *pp;
899 pp = tegra_pcie.port + tegra_pcie.num_ports;
902 pp->base = tegra_pcie.regs + offset;
903 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
907 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
911 tegra_pcie.num_ports++;
913 pp->root_bus_nr = -1;
914 memset(pp->res, 0, sizeof(pp->res));
917 int __init tegra_pcie_init(bool init_port0, bool init_port1)
921 if (!(init_port0 || init_port1))
926 err = tegra_pcie_get_resources();
930 err = tegra_pcie_enable_controller();
934 /* setup the AFI address translations */
935 tegra_pcie_setup_translations();
938 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
941 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
943 pci_common_init(&tegra_pcie_hw);