2 * arch/arm/mach-tegra/tegra2_clocks.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
26 #include <linux/hrtimer.h>
28 #include <asm/clkdev.h>
30 #include <mach/iomap.h>
31 #include <mach/suspend.h>
36 #define RST_DEVICES 0x004
37 #define RST_DEVICES_SET 0x300
38 #define RST_DEVICES_CLR 0x304
39 #define RST_DEVICES_NUM 3
41 #define CLK_OUT_ENB 0x010
42 #define CLK_OUT_ENB_SET 0x320
43 #define CLK_OUT_ENB_CLR 0x324
44 #define CLK_OUT_ENB_NUM 3
46 #define CLK_MASK_ARM 0x44
47 #define MISC_CLK_ENB 0x48
50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
57 #define OSC_FREQ_DET 0x58
58 #define OSC_FREQ_DET_TRIG (1<<31)
60 #define OSC_FREQ_DET_STATUS 0x5C
61 #define OSC_FREQ_DET_BUSY (1<<31)
62 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
64 #define PERIPH_CLK_SOURCE_I2S1 0x100
65 #define PERIPH_CLK_SOURCE_EMC 0x19c
66 #define PERIPH_CLK_SOURCE_OSC 0x1fc
67 #define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
70 #define PERIPH_CLK_SOURCE_MASK (3<<30)
71 #define PERIPH_CLK_SOURCE_SHIFT 30
72 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
75 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
78 #define PLL_BASE_BYPASS (1<<31)
79 #define PLL_BASE_ENABLE (1<<30)
80 #define PLL_BASE_REF_ENABLE (1<<29)
81 #define PLL_BASE_OVERRIDE (1<<28)
82 #define PLL_BASE_DIVP_MASK (0x7<<20)
83 #define PLL_BASE_DIVP_SHIFT 20
84 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
85 #define PLL_BASE_DIVN_SHIFT 8
86 #define PLL_BASE_DIVM_MASK (0x1F)
87 #define PLL_BASE_DIVM_SHIFT 0
89 #define PLL_OUT_RATIO_MASK (0xFF<<8)
90 #define PLL_OUT_RATIO_SHIFT 8
91 #define PLL_OUT_OVERRIDE (1<<2)
92 #define PLL_OUT_CLKEN (1<<1)
93 #define PLL_OUT_RESET_DISABLE (1<<0)
95 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
97 #define PLL_MISC_DCCON_SHIFT 20
98 #define PLL_MISC_CPCON_SHIFT 8
99 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
100 #define PLL_MISC_LFCON_SHIFT 4
101 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
102 #define PLL_MISC_VCOCON_SHIFT 0
103 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
105 #define PLLU_BASE_POST_DIV (1<<20)
107 #define PLLD_MISC_CLKENABLE (1<<30)
108 #define PLLD_MISC_DIV_RST (1<<23)
109 #define PLLD_MISC_DCCON_SHIFT 12
111 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
112 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
113 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
115 #define SUPER_CLK_MUX 0x00
116 #define SUPER_STATE_SHIFT 28
117 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
118 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
119 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
120 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
121 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
122 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
123 #define SUPER_SOURCE_MASK 0xF
124 #define SUPER_FIQ_SOURCE_SHIFT 12
125 #define SUPER_IRQ_SOURCE_SHIFT 8
126 #define SUPER_RUN_SOURCE_SHIFT 4
127 #define SUPER_IDLE_SOURCE_SHIFT 0
129 #define SUPER_CLK_DIVIDER 0x04
131 #define BUS_CLK_DISABLE (1<<3)
132 #define BUS_CLK_DIV_MASK 0x3
135 #define PMC_CTRL_BLINK_ENB (1 << 7)
137 #define PMC_DPD_PADS_ORIDE 0x1c
138 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
140 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
141 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
142 #define PMC_BLINK_TIMER_ENB (1 << 15)
143 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
144 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
146 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
147 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
150 * Some peripheral clocks share an enable bit, so refcount the enable bits
151 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
153 static int tegra_periph_clk_enable_refcount[3 * 32];
155 #define clk_writel(value, reg) \
156 __raw_writel(value, (u32)reg_clk_base + (reg))
157 #define clk_readl(reg) \
158 __raw_readl((u32)reg_clk_base + (reg))
159 #define pmc_writel(value, reg) \
160 __raw_writel(value, (u32)reg_pmc_base + (reg))
161 #define pmc_readl(reg) \
162 __raw_readl((u32)reg_pmc_base + (reg))
164 unsigned long clk_measure_input_freq(void)
166 u32 clock_autodetect;
167 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
168 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
169 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
170 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
172 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
174 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
176 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
179 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
185 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
187 s64 divider_u71 = parent_rate * 2;
188 divider_u71 += rate - 1;
189 do_div(divider_u71, rate);
191 if (divider_u71 - 2 < 0)
194 if (divider_u71 - 2 > 255)
197 return divider_u71 - 2;
200 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
204 divider_u16 = parent_rate;
205 divider_u16 += rate - 1;
206 do_div(divider_u16, rate);
208 if (divider_u16 - 1 < 0)
211 if (divider_u16 - 1 > 255)
214 return divider_u16 - 1;
217 /* clk_m functions */
218 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
220 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
222 c->rate = clk_measure_input_freq();
225 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
228 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
231 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
234 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
237 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
240 clk_writel(auto_clock_control, OSC_CTRL);
244 static void tegra2_clk_m_init(struct clk *c)
246 pr_debug("%s on clock %s\n", __func__, c->name);
247 tegra2_clk_m_autodetect_rate(c);
250 static int tegra2_clk_m_enable(struct clk *c)
252 pr_debug("%s on clock %s\n", __func__, c->name);
256 static void tegra2_clk_m_disable(struct clk *c)
258 pr_debug("%s on clock %s\n", __func__, c->name);
262 static struct clk_ops tegra_clk_m_ops = {
263 .init = tegra2_clk_m_init,
264 .enable = tegra2_clk_m_enable,
265 .disable = tegra2_clk_m_disable,
268 void tegra2_periph_reset_assert(struct clk *c)
270 BUG_ON(!c->ops->reset);
271 c->ops->reset(c, true);
274 void tegra2_periph_reset_deassert(struct clk *c)
276 BUG_ON(!c->ops->reset);
277 c->ops->reset(c, false);
280 /* super clock functions */
281 /* "super clocks" on tegra have two-stage muxes and a clock skipping
282 * super divider. We will ignore the clock skipping divider, since we
283 * can't lower the voltage when using the clock skip, but we can if we
284 * lower the PLL frequency.
286 static void tegra2_super_clk_init(struct clk *c)
291 const struct clk_mux_sel *sel;
292 val = clk_readl(c->reg + SUPER_CLK_MUX);
294 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
295 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
296 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
297 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
298 source = (val >> shift) & SUPER_SOURCE_MASK;
299 for (sel = c->inputs; sel->input != NULL; sel++) {
300 if (sel->value == source)
303 BUG_ON(sel->input == NULL);
304 c->parent = sel->input;
306 INIT_LIST_HEAD(&c->u.shared_bus.list);
309 static int tegra2_super_clk_enable(struct clk *c)
311 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
315 static void tegra2_super_clk_disable(struct clk *c)
317 pr_debug("%s on clock %s\n", __func__, c->name);
319 /* oops - don't disable the CPU clock! */
323 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
326 const struct clk_mux_sel *sel;
329 val = clk_readl(c->reg + SUPER_CLK_MUX);;
330 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
331 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
332 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
333 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
334 for (sel = c->inputs; sel->input != NULL; sel++) {
335 if (sel->input == p) {
336 val &= ~(SUPER_SOURCE_MASK << shift);
337 val |= sel->value << shift;
340 clk_enable_locked(p);
342 clk_writel(val, c->reg);
344 if (c->refcnt && c->parent)
345 clk_disable_locked(c->parent);
354 static struct clk_ops tegra_super_ops = {
355 .init = tegra2_super_clk_init,
356 .enable = tegra2_super_clk_enable,
357 .disable = tegra2_super_clk_disable,
358 .set_parent = tegra2_super_clk_set_parent,
361 /* virtual cpu clock functions */
362 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
363 To change the frequency of these clocks, the parent pll may need to be
364 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
365 and then the clock moved back to the pll. To hide this sequence, a virtual
368 static void tegra2_cpu_clk_init(struct clk *c)
372 static int tegra2_cpu_clk_enable(struct clk *c)
377 static void tegra2_cpu_clk_disable(struct clk *c)
379 pr_debug("%s on clock %s\n", __func__, c->name);
381 /* oops - don't disable the CPU clock! */
385 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
389 * Take an extra reference to the main pll so it doesn't turn
390 * off when we move the cpu off of it
392 clk_enable_locked(c->u.cpu.main);
394 ret = clk_set_parent_locked(c->parent, c->u.cpu.backup);
396 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
400 if (rate == c->u.cpu.backup->rate)
403 ret = clk_set_rate_locked(c->u.cpu.main, rate);
405 pr_err("Failed to change cpu pll to %lu\n", rate);
409 ret = clk_set_parent_locked(c->parent, c->u.cpu.main);
411 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
416 clk_disable_locked(c->u.cpu.main);
420 static struct clk_ops tegra_cpu_ops = {
421 .init = tegra2_cpu_clk_init,
422 .enable = tegra2_cpu_clk_enable,
423 .disable = tegra2_cpu_clk_disable,
424 .set_rate = tegra2_cpu_clk_set_rate,
427 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
428 * reset the COP block (i.e. AVP) */
429 static void tegra2_cop_clk_reset(struct clk *c, bool assert)
431 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
433 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
434 clk_writel(1 << 1, reg);
437 static struct clk_ops tegra_cop_ops = {
438 .reset = tegra2_cop_clk_reset,
441 /* bus clock functions */
442 static void tegra2_bus_clk_init(struct clk *c)
444 u32 val = clk_readl(c->reg);
445 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
446 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
450 static int tegra2_bus_clk_enable(struct clk *c)
452 u32 val = clk_readl(c->reg);
453 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
454 clk_writel(val, c->reg);
458 static void tegra2_bus_clk_disable(struct clk *c)
460 u32 val = clk_readl(c->reg);
461 val |= BUS_CLK_DISABLE << c->reg_shift;
462 clk_writel(val, c->reg);
465 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
467 u32 val = clk_readl(c->reg);
468 unsigned long parent_rate = c->parent->rate;
470 for (i = 1; i <= 4; i++) {
471 if (rate == parent_rate / i) {
472 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
473 val |= (i - 1) << c->reg_shift;
474 clk_writel(val, c->reg);
483 static struct clk_ops tegra_bus_ops = {
484 .init = tegra2_bus_clk_init,
485 .enable = tegra2_bus_clk_enable,
486 .disable = tegra2_bus_clk_disable,
487 .set_rate = tegra2_bus_clk_set_rate,
490 /* Blink output functions */
492 static void tegra2_blink_clk_init(struct clk *c)
496 val = pmc_readl(PMC_CTRL);
497 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
499 val = pmc_readl(c->reg);
501 if (val & PMC_BLINK_TIMER_ENB) {
504 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
505 PMC_BLINK_TIMER_DATA_ON_MASK;
506 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
507 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
509 /* each tick in the blink timer is 4 32KHz clocks */
516 static int tegra2_blink_clk_enable(struct clk *c)
520 val = pmc_readl(PMC_DPD_PADS_ORIDE);
521 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
523 val = pmc_readl(PMC_CTRL);
524 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
529 static void tegra2_blink_clk_disable(struct clk *c)
533 val = pmc_readl(PMC_CTRL);
534 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
536 val = pmc_readl(PMC_DPD_PADS_ORIDE);
537 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
540 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
542 if (rate >= c->parent->rate) {
544 pmc_writel(0, c->reg);
549 on_off = DIV_ROUND_UP(c->parent->rate / 8, rate);
552 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
553 PMC_BLINK_TIMER_DATA_ON_SHIFT;
554 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
555 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
557 val |= PMC_BLINK_TIMER_ENB;
558 pmc_writel(val, c->reg);
564 static struct clk_ops tegra_blink_clk_ops = {
565 .init = &tegra2_blink_clk_init,
566 .enable = &tegra2_blink_clk_enable,
567 .disable = &tegra2_blink_clk_disable,
568 .set_rate = &tegra2_blink_clk_set_rate,
572 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
574 udelay(c->u.pll.lock_delay);
579 static void tegra2_pll_clk_init(struct clk *c)
581 u32 val = clk_readl(c->reg + PLL_BASE);
583 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
585 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
586 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
589 } else if (val & PLL_BASE_BYPASS) {
593 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
594 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
596 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
598 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
602 static int tegra2_pll_clk_enable(struct clk *c)
605 pr_debug("%s on clock %s\n", __func__, c->name);
607 val = clk_readl(c->reg + PLL_BASE);
608 val &= ~PLL_BASE_BYPASS;
609 val |= PLL_BASE_ENABLE;
610 clk_writel(val, c->reg + PLL_BASE);
612 tegra2_pll_clk_wait_for_lock(c);
617 static void tegra2_pll_clk_disable(struct clk *c)
620 pr_debug("%s on clock %s\n", __func__, c->name);
622 val = clk_readl(c->reg);
623 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
624 clk_writel(val, c->reg);
627 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
630 unsigned long input_rate;
631 const struct clk_pll_freq_table *sel;
633 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
635 input_rate = c->parent->rate;
636 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
637 if (sel->input_rate == input_rate && sel->output_rate == rate) {
639 c->div = sel->m * sel->p;
641 val = clk_readl(c->reg + PLL_BASE);
642 if (c->flags & PLL_FIXED)
643 val |= PLL_BASE_OVERRIDE;
644 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
646 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
647 (sel->n << PLL_BASE_DIVN_SHIFT);
648 BUG_ON(sel->p < 1 || sel->p > 2);
649 if (c->flags & PLLU) {
651 val |= PLLU_BASE_POST_DIV;
654 val |= 1 << PLL_BASE_DIVP_SHIFT;
656 clk_writel(val, c->reg + PLL_BASE);
658 if (c->flags & PLL_HAS_CPCON) {
659 val = clk_readl(c->reg + PLL_MISC(c));
660 val &= ~PLL_MISC_CPCON_MASK;
661 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
662 clk_writel(val, c->reg + PLL_MISC(c));
666 tegra2_pll_clk_enable(c);
674 static struct clk_ops tegra_pll_ops = {
675 .init = tegra2_pll_clk_init,
676 .enable = tegra2_pll_clk_enable,
677 .disable = tegra2_pll_clk_disable,
678 .set_rate = tegra2_pll_clk_set_rate,
681 static void tegra2_pllx_clk_init(struct clk *c)
683 tegra2_pll_clk_init(c);
685 if (tegra_sku_id() == 7)
686 c->max_rate = 750000000;
689 static struct clk_ops tegra_pllx_ops = {
690 .init = tegra2_pllx_clk_init,
691 .enable = tegra2_pll_clk_enable,
692 .disable = tegra2_pll_clk_disable,
693 .set_rate = tegra2_pll_clk_set_rate,
696 /* Clock divider ops */
697 static void tegra2_pll_div_clk_init(struct clk *c)
699 u32 val = clk_readl(c->reg);
701 val >>= c->reg_shift;
702 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
703 if (!(val & PLL_OUT_RESET_DISABLE))
706 if (c->flags & DIV_U71) {
707 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
708 c->div = (divu71 + 2);
710 } else if (c->flags & DIV_2) {
719 static int tegra2_pll_div_clk_enable(struct clk *c)
724 pr_debug("%s: %s\n", __func__, c->name);
725 if (c->flags & DIV_U71) {
726 val = clk_readl(c->reg);
727 new_val = val >> c->reg_shift;
730 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
732 val &= ~(0xFFFF << c->reg_shift);
733 val |= new_val << c->reg_shift;
734 clk_writel(val, c->reg);
736 } else if (c->flags & DIV_2) {
737 BUG_ON(!(c->flags & PLLD));
738 val = clk_readl(c->reg);
739 val &= ~PLLD_MISC_DIV_RST;
740 clk_writel(val, c->reg);
746 static void tegra2_pll_div_clk_disable(struct clk *c)
751 pr_debug("%s: %s\n", __func__, c->name);
752 if (c->flags & DIV_U71) {
753 val = clk_readl(c->reg);
754 new_val = val >> c->reg_shift;
757 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
759 val &= ~(0xFFFF << c->reg_shift);
760 val |= new_val << c->reg_shift;
761 clk_writel(val, c->reg);
762 } else if (c->flags & DIV_2) {
763 BUG_ON(!(c->flags & PLLD));
764 val = clk_readl(c->reg);
765 val |= PLLD_MISC_DIV_RST;
766 clk_writel(val, c->reg);
770 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
775 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
776 if (c->flags & DIV_U71) {
777 divider_u71 = clk_div71_get_divider(c->parent->rate, rate);
778 if (divider_u71 >= 0) {
779 val = clk_readl(c->reg);
780 new_val = val >> c->reg_shift;
782 if (c->flags & DIV_U71_FIXED)
783 new_val |= PLL_OUT_OVERRIDE;
784 new_val &= ~PLL_OUT_RATIO_MASK;
785 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
787 val &= ~(0xFFFF << c->reg_shift);
788 val |= new_val << c->reg_shift;
789 clk_writel(val, c->reg);
790 c->div = divider_u71 + 2;
794 } else if (c->flags & DIV_2) {
795 if (c->parent->rate == rate * 2)
801 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
804 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
806 if (c->flags & DIV_U71) {
807 divider = clk_div71_get_divider(c->parent->rate, rate);
810 return c->parent->rate * 2 / (divider + 2);
811 } else if (c->flags & DIV_2) {
812 return c->parent->rate / 2;
817 static struct clk_ops tegra_pll_div_ops = {
818 .init = tegra2_pll_div_clk_init,
819 .enable = tegra2_pll_div_clk_enable,
820 .disable = tegra2_pll_div_clk_disable,
821 .set_rate = tegra2_pll_div_clk_set_rate,
822 .round_rate = tegra2_pll_div_clk_round_rate,
827 static void tegra2_periph_clk_init(struct clk *c)
829 u32 val = clk_readl(c->reg);
830 const struct clk_mux_sel *mux = 0;
831 const struct clk_mux_sel *sel;
832 if (c->flags & MUX) {
833 for (sel = c->inputs; sel->input != NULL; sel++) {
834 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
839 c->parent = mux->input;
841 c->parent = c->inputs[0].input;
844 if (c->flags & DIV_U71) {
845 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
848 } else if (c->flags & DIV_U16) {
849 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
858 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
859 PERIPH_CLK_TO_ENB_BIT(c)))
861 if (!(c->flags & PERIPH_NO_RESET))
862 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
863 PERIPH_CLK_TO_ENB_BIT(c))
867 static int tegra2_periph_clk_enable(struct clk *c)
870 pr_debug("%s on clock %s\n", __func__, c->name);
872 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
873 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
876 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
877 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
878 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
879 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
880 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
881 if (c->flags & PERIPH_EMC_ENB) {
882 /* The EMC peripheral clock has 2 extra enable bits */
883 /* FIXME: Do they need to be disabled? */
884 val = clk_readl(c->reg);
886 clk_writel(val, c->reg);
891 static void tegra2_periph_clk_disable(struct clk *c)
893 pr_debug("%s on clock %s\n", __func__, c->name);
896 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
898 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
899 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
900 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
903 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
905 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
907 pr_debug("%s %s on clock %s\n", __func__,
908 assert ? "assert" : "deassert", c->name);
909 if (!(c->flags & PERIPH_NO_RESET))
910 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
911 base + PERIPH_CLK_TO_ENB_SET_REG(c));
914 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
917 const struct clk_mux_sel *sel;
918 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
919 for (sel = c->inputs; sel->input != NULL; sel++) {
920 if (sel->input == p) {
921 val = clk_readl(c->reg);
922 val &= ~PERIPH_CLK_SOURCE_MASK;
923 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
926 clk_enable_locked(p);
928 clk_writel(val, c->reg);
930 if (c->refcnt && c->parent)
931 clk_disable_locked(c->parent);
941 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
945 pr_debug("%s: %lu\n", __func__, rate);
946 if (c->flags & DIV_U71) {
947 divider = clk_div71_get_divider(c->parent->rate, rate);
949 val = clk_readl(c->reg);
950 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
952 clk_writel(val, c->reg);
953 c->div = divider + 2;
957 } else if (c->flags & DIV_U16) {
958 divider = clk_div16_get_divider(c->parent->rate, rate);
960 val = clk_readl(c->reg);
961 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
963 clk_writel(val, c->reg);
964 c->div = divider + 1;
968 } else if (c->parent->rate <= rate) {
976 static long tegra2_periph_clk_round_rate(struct clk *c,
980 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
982 if (c->flags & DIV_U71) {
983 divider = clk_div71_get_divider(c->parent->rate, rate);
987 return c->parent->rate * 2 / (divider + 2);
988 } else if (c->flags & DIV_U16) {
989 divider = clk_div16_get_divider(c->parent->rate, rate);
992 return c->parent->rate / (divider + 1);
997 static struct clk_ops tegra_periph_clk_ops = {
998 .init = &tegra2_periph_clk_init,
999 .enable = &tegra2_periph_clk_enable,
1000 .disable = &tegra2_periph_clk_disable,
1001 .set_parent = &tegra2_periph_clk_set_parent,
1002 .set_rate = &tegra2_periph_clk_set_rate,
1003 .round_rate = &tegra2_periph_clk_round_rate,
1004 .reset = &tegra2_periph_clk_reset,
1007 /* Clock doubler ops */
1008 static void tegra2_clk_double_init(struct clk *c)
1013 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1014 PERIPH_CLK_TO_ENB_BIT(c)))
1018 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1020 if (rate != 2 * c->parent->rate)
1027 static struct clk_ops tegra_clk_double_ops = {
1028 .init = &tegra2_clk_double_init,
1029 .enable = &tegra2_periph_clk_enable,
1030 .disable = &tegra2_periph_clk_disable,
1031 .set_rate = &tegra2_clk_double_set_rate,
1034 /* Audio sync clock ops */
1035 static void tegra2_audio_sync_clk_init(struct clk *c)
1038 const struct clk_mux_sel *sel;
1039 u32 val = clk_readl(c->reg);
1040 c->state = (val & (1<<4)) ? OFF : ON;
1042 for (sel = c->inputs; sel->input != NULL; sel++)
1043 if (sel->value == source)
1045 BUG_ON(sel->input == NULL);
1046 c->parent = sel->input;
1049 static int tegra2_audio_sync_clk_enable(struct clk *c)
1051 clk_writel(0, c->reg);
1055 static void tegra2_audio_sync_clk_disable(struct clk *c)
1057 clk_writel(1, c->reg);
1060 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1063 const struct clk_mux_sel *sel;
1064 for (sel = c->inputs; sel->input != NULL; sel++) {
1065 if (sel->input == p) {
1066 val = clk_readl(c->reg);
1071 clk_enable_locked(p);
1073 clk_writel(val, c->reg);
1075 if (c->refcnt && c->parent)
1076 clk_disable_locked(c->parent);
1086 static struct clk_ops tegra_audio_sync_clk_ops = {
1087 .init = tegra2_audio_sync_clk_init,
1088 .enable = tegra2_audio_sync_clk_enable,
1089 .disable = tegra2_audio_sync_clk_disable,
1090 .set_parent = tegra2_audio_sync_clk_set_parent,
1093 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1095 static void tegra2_cdev_clk_init(struct clk *c)
1097 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1098 * currently done in the pinmux code. */
1100 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1101 PERIPH_CLK_TO_ENB_BIT(c)))
1105 static int tegra2_cdev_clk_enable(struct clk *c)
1107 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1108 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1112 static void tegra2_cdev_clk_disable(struct clk *c)
1114 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1115 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1118 static struct clk_ops tegra_cdev_clk_ops = {
1119 .init = &tegra2_cdev_clk_init,
1120 .enable = &tegra2_cdev_clk_enable,
1121 .disable = &tegra2_cdev_clk_disable,
1124 /* shared bus ops */
1126 * Some clocks may have multiple downstream users that need to request a
1127 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1128 * clock to each user. The frequency of the bus is set to the highest
1129 * enabled shared_bus_user clock, with a minimum value set by the
1132 static void tegra_clk_shared_bus_update(struct clk *bus)
1135 unsigned long rate = bus->u.shared_bus.min_rate;
1137 list_for_each_entry(c, &bus->u.shared_bus.list, u.shared_bus_user.node)
1138 if (c->u.shared_bus_user.enabled)
1139 rate = max(c->u.shared_bus_user.rate, rate);
1141 if (rate != bus->rate)
1142 clk_set_rate_locked(bus, rate);
1145 static void tegra_clk_shared_bus_init(struct clk *c)
1147 c->max_rate = c->parent->max_rate;
1148 c->u.shared_bus_user.rate = c->parent->max_rate;
1152 list_add_tail(&c->u.shared_bus_user.node,
1153 &c->parent->u.shared_bus.list);
1156 static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1158 c->u.shared_bus_user.rate = rate;
1159 tegra_clk_shared_bus_update(c->parent);
1163 static int tegra_clk_shared_bus_enable(struct clk *c)
1165 c->u.shared_bus_user.enabled = true;
1166 tegra_clk_shared_bus_update(c->parent);
1170 static void tegra_clk_shared_bus_disable(struct clk *c)
1172 c->u.shared_bus_user.enabled = false;
1173 tegra_clk_shared_bus_update(c->parent);
1176 static struct clk_ops tegra_clk_shared_bus_ops = {
1177 .init = tegra_clk_shared_bus_init,
1178 .enable = tegra_clk_shared_bus_enable,
1179 .disable = tegra_clk_shared_bus_disable,
1180 .set_rate = tegra_clk_shared_bus_set_rate,
1184 /* Clock definitions */
1185 static struct clk tegra_clk_32k = {
1192 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1193 {32768, 12000000, 366, 1, 1, 0},
1194 {32768, 13000000, 397, 1, 1, 0},
1195 {32768, 19200000, 586, 1, 1, 0},
1196 {32768, 26000000, 793, 1, 1, 0},
1200 static struct clk tegra_pll_s = {
1202 .flags = PLL_ALT_MISC_REG,
1203 .ops = &tegra_pll_ops,
1204 .parent = &tegra_clk_32k,
1205 .max_rate = 26000000,
1210 .cf_min = 0, /* FIXME */
1211 .cf_max = 0, /* FIXME */
1212 .vco_min = 12000000,
1213 .vco_max = 26000000,
1214 .freq_table = tegra_pll_s_freq_table,
1219 static struct clk_mux_sel tegra_clk_m_sel[] = {
1220 { .input = &tegra_clk_32k, .value = 0},
1221 { .input = &tegra_pll_s, .value = 1},
1225 static struct clk tegra_clk_m = {
1227 .flags = ENABLE_ON_INIT,
1228 .ops = &tegra_clk_m_ops,
1229 .inputs = tegra_clk_m_sel,
1232 .max_rate = 26000000,
1235 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1236 { 0, 0, 0, 0, 0, 0 },
1239 static struct clk tegra_pll_c = {
1241 .flags = PLL_HAS_CPCON,
1242 .ops = &tegra_pll_ops,
1244 .parent = &tegra_clk_m,
1245 .max_rate = 600000000,
1247 .input_min = 2000000,
1248 .input_max = 31000000,
1251 .vco_min = 20000000,
1252 .vco_max = 1400000000,
1253 .freq_table = tegra_pll_c_freq_table,
1258 static struct clk tegra_pll_c_out1 = {
1259 .name = "pll_c_out1",
1260 .ops = &tegra_pll_div_ops,
1262 .parent = &tegra_pll_c,
1265 .max_rate = 600000000,
1268 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1269 { 12000000, 666000000, 666, 12, 1, 8},
1270 { 13000000, 666000000, 666, 13, 1, 8},
1271 { 19200000, 666000000, 555, 16, 1, 8},
1272 { 26000000, 666000000, 666, 26, 1, 8},
1273 { 12000000, 600000000, 600, 12, 1, 8},
1274 { 13000000, 600000000, 600, 13, 1, 8},
1275 { 19200000, 600000000, 375, 12, 1, 6},
1276 { 26000000, 600000000, 600, 26, 1, 8},
1277 { 0, 0, 0, 0, 0, 0 },
1280 static struct clk tegra_pll_m = {
1282 .flags = PLL_HAS_CPCON,
1283 .ops = &tegra_pll_ops,
1285 .parent = &tegra_clk_m,
1286 .max_rate = 800000000,
1288 .input_min = 2000000,
1289 .input_max = 31000000,
1292 .vco_min = 20000000,
1293 .vco_max = 1200000000,
1294 .freq_table = tegra_pll_m_freq_table,
1299 static struct clk tegra_pll_m_out1 = {
1300 .name = "pll_m_out1",
1301 .ops = &tegra_pll_div_ops,
1303 .parent = &tegra_pll_m,
1306 .max_rate = 600000000,
1309 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1310 { 12000000, 216000000, 432, 12, 2, 8},
1311 { 13000000, 216000000, 432, 13, 2, 8},
1312 { 19200000, 216000000, 90, 4, 2, 1},
1313 { 26000000, 216000000, 432, 26, 2, 8},
1314 { 12000000, 432000000, 432, 12, 1, 8},
1315 { 13000000, 432000000, 432, 13, 1, 8},
1316 { 19200000, 432000000, 90, 4, 1, 1},
1317 { 26000000, 432000000, 432, 26, 1, 8},
1318 { 0, 0, 0, 0, 0, 0 },
1321 static struct clk tegra_pll_p = {
1323 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1324 .ops = &tegra_pll_ops,
1326 .parent = &tegra_clk_m,
1327 .max_rate = 432000000,
1329 .input_min = 2000000,
1330 .input_max = 31000000,
1333 .vco_min = 20000000,
1334 .vco_max = 1400000000,
1335 .freq_table = tegra_pll_p_freq_table,
1340 static struct clk tegra_pll_p_out1 = {
1341 .name = "pll_p_out1",
1342 .ops = &tegra_pll_div_ops,
1343 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1344 .parent = &tegra_pll_p,
1347 .max_rate = 432000000,
1350 static struct clk tegra_pll_p_out2 = {
1351 .name = "pll_p_out2",
1352 .ops = &tegra_pll_div_ops,
1353 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1354 .parent = &tegra_pll_p,
1357 .max_rate = 432000000,
1360 static struct clk tegra_pll_p_out3 = {
1361 .name = "pll_p_out3",
1362 .ops = &tegra_pll_div_ops,
1363 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1364 .parent = &tegra_pll_p,
1367 .max_rate = 432000000,
1370 static struct clk tegra_pll_p_out4 = {
1371 .name = "pll_p_out4",
1372 .ops = &tegra_pll_div_ops,
1373 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1374 .parent = &tegra_pll_p,
1377 .max_rate = 432000000,
1380 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1381 { 28800000, 56448000, 49, 25, 1, 1},
1382 { 28800000, 73728000, 64, 25, 1, 1},
1383 { 28800000, 11289600, 49, 25, 1, 1},
1384 { 28800000, 12288000, 64, 25, 1, 1},
1385 { 28800000, 24000000, 5, 6, 1, 1},
1386 { 0, 0, 0, 0, 0, 0 },
1389 static struct clk tegra_pll_a = {
1391 .flags = PLL_HAS_CPCON,
1392 .ops = &tegra_pll_ops,
1394 .parent = &tegra_pll_p_out1,
1395 .max_rate = 56448000,
1397 .input_min = 2000000,
1398 .input_max = 31000000,
1401 .vco_min = 20000000,
1402 .vco_max = 1400000000,
1403 .freq_table = tegra_pll_a_freq_table,
1408 static struct clk tegra_pll_a_out0 = {
1409 .name = "pll_a_out0",
1410 .ops = &tegra_pll_div_ops,
1412 .parent = &tegra_pll_a,
1415 .max_rate = 56448000,
1418 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1419 { 12000000, 216000000, 216, 12, 1, 4},
1420 { 13000000, 216000000, 216, 13, 1, 4},
1421 { 19200000, 216000000, 135, 12, 1, 3},
1422 { 26000000, 216000000, 216, 26, 1, 4},
1424 { 12000000, 594000000, 594, 12, 1, 8},
1425 { 13000000, 594000000, 594, 13, 1, 8},
1426 { 19200000, 594000000, 495, 16, 1, 8},
1427 { 26000000, 594000000, 594, 26, 1, 8},
1429 { 12000000, 1000000000, 1000, 12, 1, 12},
1430 { 13000000, 1000000000, 1000, 13, 1, 12},
1431 { 19200000, 1000000000, 625, 12, 1, 8},
1432 { 26000000, 1000000000, 1000, 26, 1, 12},
1434 { 0, 0, 0, 0, 0, 0 },
1437 static struct clk tegra_pll_d = {
1439 .flags = PLL_HAS_CPCON | PLLD,
1440 .ops = &tegra_pll_ops,
1442 .parent = &tegra_clk_m,
1443 .max_rate = 1000000000,
1445 .input_min = 2000000,
1446 .input_max = 40000000,
1449 .vco_min = 40000000,
1450 .vco_max = 1000000000,
1451 .freq_table = tegra_pll_d_freq_table,
1456 static struct clk tegra_pll_d_out0 = {
1457 .name = "pll_d_out0",
1458 .ops = &tegra_pll_div_ops,
1459 .flags = DIV_2 | PLLD,
1460 .parent = &tegra_pll_d,
1461 .max_rate = 500000000,
1464 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1465 { 12000000, 480000000, 960, 12, 2, 0},
1466 { 13000000, 480000000, 960, 13, 2, 0},
1467 { 19200000, 480000000, 200, 4, 2, 0},
1468 { 26000000, 480000000, 960, 26, 2, 0},
1469 { 0, 0, 0, 0, 0, 0 },
1472 static struct clk tegra_pll_u = {
1475 .ops = &tegra_pll_ops,
1477 .parent = &tegra_clk_m,
1478 .max_rate = 480000000,
1480 .input_min = 2000000,
1481 .input_max = 40000000,
1484 .vco_min = 480000000,
1485 .vco_max = 960000000,
1486 .freq_table = tegra_pll_u_freq_table,
1491 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1493 { 12000000, 1000000000, 1000, 12, 1, 12},
1494 { 13000000, 1000000000, 1000, 13, 1, 12},
1495 { 19200000, 1000000000, 625, 12, 1, 8},
1496 { 26000000, 1000000000, 1000, 26, 1, 12},
1499 { 12000000, 912000000, 912, 12, 1, 12},
1500 { 13000000, 912000000, 912, 13, 1, 12},
1501 { 19200000, 912000000, 760, 16, 1, 8},
1502 { 26000000, 912000000, 912, 26, 1, 12},
1505 { 12000000, 816000000, 816, 12, 1, 12},
1506 { 13000000, 816000000, 816, 13, 1, 12},
1507 { 19200000, 816000000, 680, 16, 1, 8},
1508 { 26000000, 816000000, 816, 26, 1, 12},
1511 { 12000000, 760000000, 760, 12, 1, 12},
1512 { 13000000, 760000000, 760, 13, 1, 12},
1513 { 19200000, 760000000, 950, 24, 1, 8},
1514 { 26000000, 760000000, 760, 26, 1, 12},
1517 { 12000000, 608000000, 760, 12, 1, 12},
1518 { 13000000, 608000000, 760, 13, 1, 12},
1519 { 19200000, 608000000, 380, 12, 1, 8},
1520 { 26000000, 608000000, 760, 26, 1, 12},
1523 { 12000000, 456000000, 456, 12, 1, 12},
1524 { 13000000, 456000000, 456, 13, 1, 12},
1525 { 19200000, 456000000, 380, 16, 1, 8},
1526 { 26000000, 456000000, 456, 26, 1, 12},
1529 { 12000000, 312000000, 312, 12, 1, 12},
1530 { 13000000, 312000000, 312, 13, 1, 12},
1531 { 19200000, 312000000, 260, 16, 1, 8},
1532 { 26000000, 312000000, 312, 26, 1, 12},
1534 { 0, 0, 0, 0, 0, 0 },
1537 static struct clk tegra_pll_x = {
1539 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1540 .ops = &tegra_pllx_ops,
1542 .parent = &tegra_clk_m,
1543 .max_rate = 1000000000,
1545 .input_min = 2000000,
1546 .input_max = 31000000,
1549 .vco_min = 20000000,
1550 .vco_max = 1200000000,
1551 .freq_table = tegra_pll_x_freq_table,
1556 static struct clk tegra_clk_d = {
1558 .flags = PERIPH_NO_RESET,
1559 .ops = &tegra_clk_double_ops,
1562 .parent = &tegra_clk_m,
1563 .max_rate = 52000000,
1569 /* dap_mclk1, belongs to the cdev1 pingroup. */
1570 static struct clk tegra_dev1_clk = {
1572 .ops = &tegra_cdev_clk_ops,
1574 .max_rate = 26000000,
1580 /* dap_mclk2, belongs to the cdev2 pingroup. */
1581 static struct clk tegra_dev2_clk = {
1583 .ops = &tegra_cdev_clk_ops,
1585 .max_rate = 26000000,
1591 /* initialized before peripheral clocks */
1592 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1593 static const struct audio_sources {
1596 } mux_audio_sync_clk_sources[] = {
1597 { .name = "spdif_in", .value = 0 },
1598 { .name = "i2s1", .value = 1 },
1599 { .name = "i2s2", .value = 2 },
1600 { .name = "pll_a_out0", .value = 4 },
1601 #if 0 /* FIXME: not implemented */
1602 { .name = "ac97", .value = 3 },
1603 { .name = "ext_audio_clk2", .value = 5 },
1604 { .name = "ext_audio_clk1", .value = 6 },
1605 { .name = "ext_vimclk", .value = 7 },
1610 static struct clk tegra_clk_audio = {
1612 .inputs = mux_audio_sync_clk,
1614 .max_rate = 24000000,
1615 .ops = &tegra_audio_sync_clk_ops
1618 static struct clk tegra_clk_audio_2x = {
1620 .flags = PERIPH_NO_RESET,
1621 .max_rate = 48000000,
1622 .ops = &tegra_clk_double_ops,
1625 .parent = &tegra_clk_audio,
1631 struct clk_lookup tegra_audio_clk_lookups[] = {
1632 { .con_id = "audio", .clk = &tegra_clk_audio },
1633 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1636 /* This is called after peripheral clocks are initialized, as the
1637 * audio_sync clock depends on some of the peripheral clocks.
1640 static void init_audio_sync_clock_mux(void)
1643 struct clk_mux_sel *sel = mux_audio_sync_clk;
1644 const struct audio_sources *src = mux_audio_sync_clk_sources;
1645 struct clk_lookup *lookup;
1647 for (i = 0; src->name; i++, sel++, src++) {
1648 sel->input = tegra_get_clock_by_name(src->name);
1650 pr_err("%s: could not find clk %s\n", __func__,
1652 sel->value = src->value;
1655 lookup = tegra_audio_clk_lookups;
1656 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1657 clk_init(lookup->clk);
1662 static struct clk_mux_sel mux_cclk[] = {
1663 { .input = &tegra_clk_m, .value = 0},
1664 { .input = &tegra_pll_c, .value = 1},
1665 { .input = &tegra_clk_32k, .value = 2},
1666 { .input = &tegra_pll_m, .value = 3},
1667 { .input = &tegra_pll_p, .value = 4},
1668 { .input = &tegra_pll_p_out4, .value = 5},
1669 { .input = &tegra_pll_p_out3, .value = 6},
1670 { .input = &tegra_clk_d, .value = 7},
1671 { .input = &tegra_pll_x, .value = 8},
1675 static struct clk_mux_sel mux_sclk[] = {
1676 { .input = &tegra_clk_m, .value = 0},
1677 { .input = &tegra_pll_c_out1, .value = 1},
1678 { .input = &tegra_pll_p_out4, .value = 2},
1679 { .input = &tegra_pll_p_out3, .value = 3},
1680 { .input = &tegra_pll_p_out2, .value = 4},
1681 { .input = &tegra_clk_d, .value = 5},
1682 { .input = &tegra_clk_32k, .value = 6},
1683 { .input = &tegra_pll_m_out1, .value = 7},
1687 static struct clk tegra_clk_cclk = {
1691 .ops = &tegra_super_ops,
1692 .max_rate = 1000000000,
1695 static struct clk tegra_clk_sclk = {
1699 .ops = &tegra_super_ops,
1700 .max_rate = 240000000,
1702 .min_rate = 120000000,
1706 static struct clk tegra_clk_virtual_cpu = {
1708 .parent = &tegra_clk_cclk,
1709 .ops = &tegra_cpu_ops,
1710 .max_rate = 1000000000,
1712 .main = &tegra_pll_x,
1713 .backup = &tegra_pll_p,
1717 static struct clk tegra_clk_cop = {
1719 .parent = &tegra_clk_sclk,
1720 .ops = &tegra_cop_ops,
1721 .max_rate = 240000000,
1724 static struct clk tegra_clk_hclk = {
1727 .parent = &tegra_clk_sclk,
1730 .ops = &tegra_bus_ops,
1731 .max_rate = 240000000,
1734 static struct clk tegra_clk_pclk = {
1737 .parent = &tegra_clk_hclk,
1740 .ops = &tegra_bus_ops,
1741 .max_rate = 120000000,
1744 static struct clk tegra_clk_blink = {
1746 .parent = &tegra_clk_32k,
1748 .ops = &tegra_blink_clk_ops,
1752 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1753 { .input = &tegra_pll_m, .value = 0},
1754 { .input = &tegra_pll_c, .value = 1},
1755 { .input = &tegra_pll_p, .value = 2},
1756 { .input = &tegra_pll_a_out0, .value = 3},
1760 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1761 { .input = &tegra_pll_m, .value = 0},
1762 { .input = &tegra_pll_c, .value = 1},
1763 { .input = &tegra_pll_p, .value = 2},
1764 { .input = &tegra_clk_m, .value = 3},
1768 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1769 { .input = &tegra_pll_p, .value = 0},
1770 { .input = &tegra_pll_c, .value = 1},
1771 { .input = &tegra_pll_m, .value = 2},
1772 { .input = &tegra_clk_m, .value = 3},
1776 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
1777 {.input = &tegra_pll_a_out0, .value = 0},
1778 {.input = &tegra_clk_audio_2x, .value = 1},
1779 {.input = &tegra_pll_p, .value = 2},
1780 {.input = &tegra_clk_m, .value = 3},
1784 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1785 {.input = &tegra_pll_p, .value = 0},
1786 {.input = &tegra_pll_d_out0, .value = 1},
1787 {.input = &tegra_pll_c, .value = 2},
1788 {.input = &tegra_clk_m, .value = 3},
1792 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1793 {.input = &tegra_pll_p, .value = 0},
1794 {.input = &tegra_pll_c, .value = 1},
1795 {.input = &tegra_clk_audio, .value = 2},
1796 {.input = &tegra_clk_m, .value = 3},
1797 {.input = &tegra_clk_32k, .value = 4},
1801 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
1802 {.input = &tegra_pll_p, .value = 0},
1803 {.input = &tegra_pll_c, .value = 1},
1804 {.input = &tegra_pll_m, .value = 2},
1808 static struct clk_mux_sel mux_clk_m[] = {
1809 { .input = &tegra_clk_m, .value = 0},
1813 static struct clk_mux_sel mux_pllp_out3[] = {
1814 { .input = &tegra_pll_p_out3, .value = 0},
1818 static struct clk_mux_sel mux_plld[] = {
1819 { .input = &tegra_pll_d, .value = 0},
1823 static struct clk_mux_sel mux_clk_32k[] = {
1824 { .input = &tegra_clk_32k, .value = 0},
1828 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
1835 .ops = &tegra_periph_clk_ops, \
1837 .inputs = _inputs, \
1841 .clk_num = _clk_num, \
1845 #define SHARED_CLK(_name, _dev, _con, _parent) \
1852 .ops = &tegra_clk_shared_bus_ops, \
1853 .parent = _parent, \
1856 struct clk tegra_list_clks[] = {
1857 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
1858 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
1859 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1860 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1861 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1862 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
1863 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
1864 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1865 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1866 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1867 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1868 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1869 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1870 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1871 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1872 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1873 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1874 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1875 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1876 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1877 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1878 PERIPH_CLK("vcp", "vcp", NULL, 29, 0, 250000000, mux_clk_m, 0),
1879 PERIPH_CLK("bsea", "bsea", NULL, 62, 0, 250000000, mux_clk_m, 0),
1880 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1881 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
1882 /* FIXME: what is la? */
1883 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1884 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1885 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1886 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1887 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1888 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1889 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1890 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1891 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1892 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1893 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1894 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1895 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1896 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1897 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1898 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1899 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1900 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
1901 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1902 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1903 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
1904 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1905 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1906 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1907 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1908 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1909 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1910 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1911 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1912 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1913 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1914 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1915 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1916 PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB),
1917 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
1918 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
1919 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
1920 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
1922 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
1925 #define CLK_DUPLICATE(_name, _dev, _con) \
1934 /* Some clocks may be used by different drivers depending on the board
1935 * configuration. List those here to register them twice in the clock lookup
1936 * table under two names.
1938 struct clk_duplicate tegra_clk_duplicates[] = {
1939 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
1940 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
1941 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
1942 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
1943 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
1944 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1945 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1946 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1947 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1948 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1949 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
1950 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
1951 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
1952 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
1953 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
1954 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1955 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1956 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1957 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1958 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1961 #define CLK(dev, con, ck) \
1968 struct clk *tegra_ptr_clks[] = {
1994 &tegra_clk_virtual_cpu,
1999 static void tegra2_init_one_clock(struct clk *c)
2002 if (!c->lookup.dev_id && !c->lookup.con_id)
2003 c->lookup.con_id = c->name;
2005 clkdev_add(&c->lookup);
2008 void __init tegra2_init_clocks(void)
2013 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2014 tegra2_init_one_clock(tegra_ptr_clks[i]);
2016 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2017 tegra2_init_one_clock(&tegra_list_clks[i]);
2019 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2020 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2022 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2023 tegra_clk_duplicates[i].name);
2027 tegra_clk_duplicates[i].lookup.clk = c;
2028 clkdev_add(&tegra_clk_duplicates[i].lookup);
2031 init_audio_sync_clock_mux();
2035 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2036 PERIPH_CLK_SOURCE_NUM + 15];
2038 void tegra_clk_suspend(void)
2040 unsigned long off, i;
2041 u32 *ctx = clk_rst_suspend;
2043 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2044 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2045 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2046 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2047 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2049 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2050 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2051 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2053 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2054 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2056 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2057 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2058 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2060 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2062 if (off == PERIPH_CLK_SOURCE_EMC)
2064 *ctx++ = clk_readl(off);
2068 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2069 *ctx++ = clk_readl(off);
2072 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2073 *ctx++ = clk_readl(off);
2075 *ctx++ = clk_readl(MISC_CLK_ENB);
2076 *ctx++ = clk_readl(CLK_MASK_ARM);
2079 void tegra_clk_resume(void)
2081 unsigned long off, i;
2082 const u32 *ctx = clk_rst_suspend;
2085 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2087 clk_writel(val, OSC_CTRL);
2089 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2090 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2091 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2092 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2095 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2096 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2097 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2099 clk_writel(*ctx++, tegra_clk_cclk.reg);
2100 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2102 clk_writel(*ctx++, tegra_clk_sclk.reg);
2103 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2104 clk_writel(*ctx++, tegra_clk_pclk.reg);
2106 /* enable all clocks before configuring clock sources */
2107 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2108 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2109 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2112 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2114 if (off == PERIPH_CLK_SOURCE_EMC)
2116 clk_writel(*ctx++, off);
2121 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2122 clk_writel(*ctx++, off);
2126 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2127 clk_writel(*ctx++, off);
2130 clk_writel(*ctx++, MISC_CLK_ENB);
2131 clk_writel(*ctx++, CLK_MASK_ARM);