2 * Copyright (C) 2011 Google, Inc.
5 * Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/clk.h>
21 #include <linux/err.h>
23 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/platform_data/tegra_emc.h>
28 #include <mach/iomap.h>
30 #include "tegra2_emc.h"
33 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
34 static bool emc_enable = true;
36 static bool emc_enable;
38 module_param(emc_enable, bool, 0644);
40 static struct platform_device *emc_pdev;
41 static void __iomem *emc_regbase;
43 static inline void emc_writel(u32 val, unsigned long addr)
45 writel(val, emc_regbase + addr);
48 static inline u32 emc_readl(unsigned long addr)
50 return readl(emc_regbase + addr);
53 static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
72 0x74, /* BURST_REFRESH_NUM */
83 0xa0, /* TCLKSTABLE */
86 0xac, /* QUSE_EXTRA */
87 0x114, /* FBIO_CFG6 */
90 0x104, /* FBIO_CFG5 */
91 0x2bc, /* CFG_DIG_DLL */
92 0x2c0, /* DLL_XFORM_DQS */
93 0x2c4, /* DLL_XFORM_QUSE */
94 0x2e0, /* ZCAL_REF_CNT */
95 0x2e4, /* ZCAL_WAIT_CNT */
96 0x2a8, /* AUTO_CAL_INTERVAL */
97 0x2d0, /* CFG_CLKTRIM_0 */
98 0x2d4, /* CFG_CLKTRIM_1 */
99 0x2d8, /* CFG_CLKTRIM_2 */
102 /* Select the closest EMC rate that is higher than the requested rate */
103 long tegra_emc_round_rate(unsigned long rate)
105 struct tegra_emc_pdata *pdata;
108 unsigned long distance = ULONG_MAX;
113 pdata = emc_pdev->dev.platform_data;
115 pr_debug("%s: %lu\n", __func__, rate);
118 * The EMC clock rate is twice the bus rate, and the bus rate is
121 rate = rate / 2 / 1000;
123 for (i = 0; i < pdata->num_tables; i++) {
124 if (pdata->tables[i].rate >= rate &&
125 (pdata->tables[i].rate - rate) < distance) {
126 distance = pdata->tables[i].rate - rate;
134 pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate);
136 return pdata->tables[best].rate * 2 * 1000;
140 * The EMC registers have shadow registers. When the EMC clock is updated
141 * in the clock controller, the shadow registers are copied to the active
142 * registers, allowing glitchless memory bus frequency changes.
143 * This function updates the shadow registers for a new clock frequency,
144 * and relies on the clock lock on the emc clock to avoid races between
145 * multiple frequency changes
147 int tegra_emc_set_rate(unsigned long rate)
149 struct tegra_emc_pdata *pdata;
156 pdata = emc_pdev->dev.platform_data;
159 * The EMC clock rate is twice the bus rate, and the bus rate is
162 rate = rate / 2 / 1000;
164 for (i = 0; i < pdata->num_tables; i++)
165 if (pdata->tables[i].rate == rate)
168 if (i >= pdata->num_tables)
171 pr_debug("%s: setting to %lu\n", __func__, rate);
173 for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
174 emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]);
176 emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]);
182 static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
184 struct device_node *iter;
187 for_each_child_of_node(np, iter) {
188 if (of_property_read_u32(np, "nvidia,ram-code", ®))
190 if (reg == tegra_bct_strapping)
191 return of_node_get(iter);
197 static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
198 struct platform_device *pdev)
200 struct device_node *np = pdev->dev.of_node;
201 struct device_node *tnp, *iter;
202 struct tegra_emc_pdata *pdata;
203 int ret, i, num_tables;
208 if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
209 tnp = tegra_emc_ramcode_devnode(np);
212 "can't find emc table for ram-code 0x%02x\n",
213 tegra_bct_strapping);
215 tnp = of_node_get(np);
221 for_each_child_of_node(tnp, iter)
222 if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table"))
230 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
231 pdata->tables = devm_kzalloc(&pdev->dev,
232 sizeof(*pdata->tables) * num_tables,
236 for_each_child_of_node(tnp, iter) {
239 ret = of_property_read_u32(iter, "clock-frequency", &prop);
241 dev_err(&pdev->dev, "no clock-frequency in %s\n",
245 pdata->tables[i].rate = prop;
247 ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
248 pdata->tables[i].regs,
252 "malformed emc-registers property in %s\n",
259 pdata->num_tables = i;
266 static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
267 struct platform_device *pdev)
273 static struct tegra_emc_pdata __devinit *tegra_emc_fill_pdata(struct platform_device *pdev)
275 struct clk *c = clk_get_sys(NULL, "emc");
276 struct tegra_emc_pdata *pdata;
280 WARN_ON(pdev->dev.platform_data);
281 BUG_ON(IS_ERR_OR_NULL(c));
283 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
284 pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
287 pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000;
289 for (i = 0; i < TEGRA_EMC_NUM_REGS; i++)
290 pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]);
292 pdata->num_tables = 1;
294 khz = pdata->tables[0].rate;
295 dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, "
296 "%ld kHz mem\n", khz * 2, khz);
301 static int __devinit tegra_emc_probe(struct platform_device *pdev)
303 struct tegra_emc_pdata *pdata;
304 struct resource *res;
307 dev_err(&pdev->dev, "disabled per module parameter\n");
311 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
313 dev_err(&pdev->dev, "missing register base\n");
317 emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
319 dev_err(&pdev->dev, "failed to remap registers\n");
323 pdata = pdev->dev.platform_data;
326 pdata = tegra_emc_dt_parse_pdata(pdev);
329 pdata = tegra_emc_fill_pdata(pdev);
331 pdev->dev.platform_data = pdata;
338 static struct of_device_id tegra_emc_of_match[] __devinitdata = {
339 { .compatible = "nvidia,tegra20-emc", },
343 static struct platform_driver tegra_emc_driver = {
346 .owner = THIS_MODULE,
347 .of_match_table = tegra_emc_of_match,
349 .probe = tegra_emc_probe,
352 static int __init tegra_emc_init(void)
354 return platform_driver_register(&tegra_emc_driver);
356 device_initcall(tegra_emc_init);