2 * arch/arm/mach-tegra/tegra30_clocks.c
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/clk-private.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
29 #include <linux/clk.h>
30 #include <linux/cpufreq.h>
34 #include "tegra30_clocks.h"
36 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
37 _parent_names, _parents, _parent) \
38 static struct clk tegra_##_name = { \
39 .hw = &tegra_##_name##_hw.hw, \
44 .parent_names = _parent_names, \
45 .parents = _parents, \
46 .num_parents = ARRAY_SIZE(_parent_names), \
50 static struct clk tegra_clk_32k;
51 static struct clk_tegra tegra_clk_32k_hw = {
53 .clk = &tegra_clk_32k,
57 static struct clk tegra_clk_32k = {
59 .hw = &tegra_clk_32k_hw.hw,
60 .ops = &tegra_clk_32k_ops,
64 static struct clk tegra_clk_m;
65 static struct clk_tegra tegra_clk_m_hw = {
69 .flags = ENABLE_ON_INIT,
74 static struct clk tegra_clk_m = {
76 .hw = &tegra_clk_m_hw.hw,
77 .ops = &tegra30_clk_m_ops,
78 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
81 static const char *clk_m_div_parent_names[] = {
85 static struct clk *clk_m_div_parents[] = {
89 static struct clk tegra_clk_m_div2;
90 static struct clk_tegra tegra_clk_m_div2_hw = {
92 .clk = &tegra_clk_m_div2,
98 DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
99 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
101 static struct clk tegra_clk_m_div4;
102 static struct clk_tegra tegra_clk_m_div4_hw = {
104 .clk = &tegra_clk_m_div4,
108 .max_rate = 12000000,
110 DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
111 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
113 static struct clk tegra_pll_ref;
114 static struct clk_tegra tegra_pll_ref_hw = {
116 .clk = &tegra_pll_ref,
118 .flags = ENABLE_ON_INIT,
119 .max_rate = 26000000,
121 DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
122 clk_m_div_parents, &tegra_clk_m);
124 #define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
125 _input_max, _cf_min, _cf_max, _vco_min, \
126 _vco_max, _freq_table, _lock_delay, _ops, \
127 _fixed_rate, _clk_cfg_ex, _parent) \
128 static struct clk tegra_##_name; \
129 static const char *_name##_parent_names[] = { \
132 static struct clk *_name##_parents[] = { \
135 static struct clk_tegra tegra_##_name##_hw = { \
137 .clk = &tegra_##_name, \
141 .max_rate = _max_rate, \
143 .input_min = _input_min, \
144 .input_max = _input_max, \
147 .vco_min = _vco_min, \
148 .vco_max = _vco_max, \
149 .freq_table = _freq_table, \
150 .lock_delay = _lock_delay, \
151 .fixed_rate = _fixed_rate, \
153 .clk_cfg_ex = _clk_cfg_ex, \
155 DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
156 _name##_parent_names, _name##_parents, \
159 #define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
160 _max_rate, _ops, _parent, _clk_flags) \
161 static const char *_name##_parent_names[] = { \
164 static struct clk *_name##_parents[] = { \
167 static struct clk tegra_##_name; \
168 static struct clk_tegra tegra_##_name##_hw = { \
170 .clk = &tegra_##_name, \
174 .max_rate = _max_rate, \
175 .reg_shift = _reg_shift, \
177 DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
178 _clk_flags, _name##_parent_names, \
179 _name##_parents, &tegra_##_parent);
181 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
182 { 12000000, 1040000000, 520, 6, 1, 8},
183 { 13000000, 1040000000, 480, 6, 1, 8},
184 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
185 { 19200000, 1040000000, 325, 6, 1, 6},
186 { 26000000, 1040000000, 520, 13, 1, 8},
188 { 12000000, 832000000, 416, 6, 1, 8},
189 { 13000000, 832000000, 832, 13, 1, 8},
190 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
191 { 19200000, 832000000, 260, 6, 1, 8},
192 { 26000000, 832000000, 416, 13, 1, 8},
194 { 12000000, 624000000, 624, 12, 1, 8},
195 { 13000000, 624000000, 624, 13, 1, 8},
196 { 16800000, 600000000, 520, 14, 1, 8},
197 { 19200000, 624000000, 520, 16, 1, 8},
198 { 26000000, 624000000, 624, 26, 1, 8},
200 { 12000000, 600000000, 600, 12, 1, 8},
201 { 13000000, 600000000, 600, 13, 1, 8},
202 { 16800000, 600000000, 500, 14, 1, 8},
203 { 19200000, 600000000, 375, 12, 1, 6},
204 { 26000000, 600000000, 600, 26, 1, 8},
206 { 12000000, 520000000, 520, 12, 1, 8},
207 { 13000000, 520000000, 520, 13, 1, 8},
208 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
209 { 19200000, 520000000, 325, 12, 1, 6},
210 { 26000000, 520000000, 520, 26, 1, 8},
212 { 12000000, 416000000, 416, 12, 1, 8},
213 { 13000000, 416000000, 416, 13, 1, 8},
214 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
215 { 19200000, 416000000, 260, 12, 1, 6},
216 { 26000000, 416000000, 416, 26, 1, 8},
217 { 0, 0, 0, 0, 0, 0 },
220 DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
221 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
222 tegra30_pll_ops, 0, NULL, pll_ref);
224 DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
225 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
227 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
228 { 12000000, 666000000, 666, 12, 1, 8},
229 { 13000000, 666000000, 666, 13, 1, 8},
230 { 16800000, 666000000, 555, 14, 1, 8},
231 { 19200000, 666000000, 555, 16, 1, 8},
232 { 26000000, 666000000, 666, 26, 1, 8},
233 { 12000000, 600000000, 600, 12, 1, 8},
234 { 13000000, 600000000, 600, 13, 1, 8},
235 { 16800000, 600000000, 500, 14, 1, 8},
236 { 19200000, 600000000, 375, 12, 1, 6},
237 { 26000000, 600000000, 600, 26, 1, 8},
238 { 0, 0, 0, 0, 0, 0 },
241 DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
242 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
243 300, tegra30_pll_ops, 0, NULL, pll_ref);
245 DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
246 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
248 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
249 { 12000000, 216000000, 432, 12, 2, 8},
250 { 13000000, 216000000, 432, 13, 2, 8},
251 { 16800000, 216000000, 360, 14, 2, 8},
252 { 19200000, 216000000, 360, 16, 2, 8},
253 { 26000000, 216000000, 432, 26, 2, 8},
254 { 0, 0, 0, 0, 0, 0 },
257 DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
258 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
259 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
262 DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
263 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
264 DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
265 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
266 DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
267 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
268 DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
269 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
271 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
272 { 9600000, 564480000, 294, 5, 1, 4},
273 { 9600000, 552960000, 288, 5, 1, 4},
274 { 9600000, 24000000, 5, 2, 1, 1},
276 { 28800000, 56448000, 49, 25, 1, 1},
277 { 28800000, 73728000, 64, 25, 1, 1},
278 { 28800000, 24000000, 5, 6, 1, 1},
279 { 0, 0, 0, 0, 0, 0 },
282 DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
283 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
284 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
286 DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
287 pll_a, CLK_IGNORE_UNUSED);
289 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
290 { 12000000, 216000000, 216, 12, 1, 4},
291 { 13000000, 216000000, 216, 13, 1, 4},
292 { 16800000, 216000000, 180, 14, 1, 4},
293 { 19200000, 216000000, 180, 16, 1, 4},
294 { 26000000, 216000000, 216, 26, 1, 4},
296 { 12000000, 594000000, 594, 12, 1, 8},
297 { 13000000, 594000000, 594, 13, 1, 8},
298 { 16800000, 594000000, 495, 14, 1, 8},
299 { 19200000, 594000000, 495, 16, 1, 8},
300 { 26000000, 594000000, 594, 26, 1, 8},
302 { 12000000, 1000000000, 1000, 12, 1, 12},
303 { 13000000, 1000000000, 1000, 13, 1, 12},
304 { 19200000, 1000000000, 625, 12, 1, 8},
305 { 26000000, 1000000000, 1000, 26, 1, 12},
307 { 0, 0, 0, 0, 0, 0 },
310 DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
311 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
312 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
314 DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
315 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
317 DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
318 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
319 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
322 DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
323 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
325 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
326 { 12000000, 480000000, 960, 12, 2, 12},
327 { 13000000, 480000000, 960, 13, 2, 12},
328 { 16800000, 480000000, 400, 7, 2, 5},
329 { 19200000, 480000000, 200, 4, 2, 3},
330 { 26000000, 480000000, 960, 26, 2, 12},
331 { 0, 0, 0, 0, 0, 0 },
334 DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
335 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
336 1000, tegra30_pll_ops, 0, NULL, pll_ref);
338 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
340 { 12000000, 1700000000, 850, 6, 1, 8},
341 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
342 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
343 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
344 { 26000000, 1700000000, 850, 13, 1, 8},
347 { 12000000, 1600000000, 800, 6, 1, 8},
348 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
349 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
350 { 19200000, 1600000000, 500, 6, 1, 8},
351 { 26000000, 1600000000, 800, 13, 1, 8},
354 { 12000000, 1500000000, 750, 6, 1, 8},
355 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
356 { 16800000, 1500000000, 625, 7, 1, 8},
357 { 19200000, 1500000000, 625, 8, 1, 8},
358 { 26000000, 1500000000, 750, 13, 1, 8},
361 { 12000000, 1400000000, 700, 6, 1, 8},
362 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
363 { 16800000, 1400000000, 1000, 12, 1, 8},
364 { 19200000, 1400000000, 875, 12, 1, 8},
365 { 26000000, 1400000000, 700, 13, 1, 8},
368 { 12000000, 1300000000, 975, 9, 1, 8},
369 { 13000000, 1300000000, 1000, 10, 1, 8},
370 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
371 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
372 { 26000000, 1300000000, 650, 13, 1, 8},
375 { 12000000, 1200000000, 1000, 10, 1, 8},
376 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
377 { 16800000, 1200000000, 1000, 14, 1, 8},
378 { 19200000, 1200000000, 1000, 16, 1, 8},
379 { 26000000, 1200000000, 600, 13, 1, 8},
382 { 12000000, 1100000000, 825, 9, 1, 8},
383 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
384 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
385 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
386 { 26000000, 1100000000, 550, 13, 1, 8},
389 { 12000000, 1000000000, 1000, 12, 1, 8},
390 { 13000000, 1000000000, 1000, 13, 1, 8},
391 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
392 { 19200000, 1000000000, 625, 12, 1, 8},
393 { 26000000, 1000000000, 1000, 26, 1, 8},
395 { 0, 0, 0, 0, 0, 0 },
398 DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
399 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
400 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
402 DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
403 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
405 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
406 /* PLLE special case: use cpcon field to store cml divider value */
407 { 12000000, 100000000, 150, 1, 18, 11},
408 { 216000000, 100000000, 200, 18, 24, 13},
409 { 0, 0, 0, 0, 0, 0 },
412 DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
413 12000000, 12000000, 1200000000, 2400000000U,
414 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
417 static const char *mux_plle[] = {
421 static struct clk *mux_plle_p[] = {
425 static struct clk tegra_cml0;
426 static struct clk_tegra tegra_cml0_hw = {
431 .fixed_rate = 100000000,
436 DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
437 mux_plle_p, &tegra_pll_e);
439 static struct clk tegra_cml1;
440 static struct clk_tegra tegra_cml1_hw = {
445 .fixed_rate = 100000000,
450 DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
451 mux_plle_p, &tegra_pll_e);
453 static struct clk tegra_pciex;
454 static struct clk_tegra tegra_pciex_hw = {
459 .fixed_rate = 100000000,
460 .reset = tegra30_periph_clk_reset,
465 DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
466 mux_plle_p, &tegra_pll_e);
468 #define SYNC_SOURCE(_name) \
469 static struct clk tegra_##_name##_sync; \
470 static struct clk_tegra tegra_##_name##_sync_hw = { \
472 .clk = &tegra_##_name##_sync, \
474 .max_rate = 24000000, \
475 .fixed_rate = 24000000, \
477 static struct clk tegra_##_name##_sync = { \
478 .name = #_name "_sync", \
479 .hw = &tegra_##_name##_sync_hw.hw, \
480 .ops = &tegra_sync_source_ops, \
481 .flags = CLK_IS_ROOT, \
484 SYNC_SOURCE(spdif_in);
492 static struct clk *tegra_sync_source_list[] = {
493 &tegra_spdif_in_sync,
502 static const char *mux_audio_sync_clk[] = {
512 #define AUDIO_SYNC_CLK(_name, _index) \
513 static struct clk tegra_##_name; \
514 static struct clk_tegra tegra_##_name##_hw = { \
516 .clk = &tegra_##_name, \
518 .max_rate = 24000000, \
519 .reg = 0x4A0 + (_index) * 4, \
521 static struct clk tegra_##_name = { \
523 .ops = &tegra_audio_sync_clk_ops, \
524 .hw = &tegra_##_name##_hw.hw, \
525 .parent_names = mux_audio_sync_clk, \
526 .parents = tegra_sync_source_list, \
527 .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
530 AUDIO_SYNC_CLK(audio0, 0);
531 AUDIO_SYNC_CLK(audio1, 1);
532 AUDIO_SYNC_CLK(audio2, 2);
533 AUDIO_SYNC_CLK(audio3, 3);
534 AUDIO_SYNC_CLK(audio4, 4);
535 AUDIO_SYNC_CLK(audio5, 5);
537 static struct clk *tegra_clk_audio_list[] = {
543 &tegra_audio5, /* SPDIF */
546 #define AUDIO_SYNC_2X_CLK(_name, _index) \
547 static const char *_name##_parent_names[] = { \
550 static struct clk *_name##_parents[] = { \
553 static struct clk tegra_##_name##_2x; \
554 static struct clk_tegra tegra_##_name##_2x_hw = { \
556 .clk = &tegra_##_name##_2x, \
558 .flags = PERIPH_NO_RESET, \
559 .max_rate = 48000000, \
561 .reg_shift = 24 + (_index), \
563 .clk_num = 113 + (_index), \
566 static struct clk tegra_##_name##_2x = { \
567 .name = #_name "_2x", \
568 .ops = &tegra30_clk_double_ops, \
569 .hw = &tegra_##_name##_2x_hw.hw, \
570 .parent_names = _name##_parent_names, \
571 .parents = _name##_parents, \
572 .parent = &tegra_##_name, \
576 AUDIO_SYNC_2X_CLK(audio0, 0);
577 AUDIO_SYNC_2X_CLK(audio1, 1);
578 AUDIO_SYNC_2X_CLK(audio2, 2);
579 AUDIO_SYNC_2X_CLK(audio3, 3);
580 AUDIO_SYNC_2X_CLK(audio4, 4);
581 AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
583 static struct clk *tegra_clk_audio_2x_list[] = {
589 &tegra_audio5_2x, /* SPDIF */
592 #define MUX_I2S_SPDIF(_id) \
593 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
599 static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
606 MUX_I2S_SPDIF(audio0);
607 MUX_I2S_SPDIF(audio1);
608 MUX_I2S_SPDIF(audio2);
609 MUX_I2S_SPDIF(audio3);
610 MUX_I2S_SPDIF(audio4);
611 MUX_I2S_SPDIF(audio5); /* SPDIF */
613 static struct clk tegra_extern1;
614 static struct clk tegra_extern2;
615 static struct clk tegra_extern3;
617 /* External clock outputs (through PMC) */
618 #define MUX_EXTERN_OUT(_id) \
619 static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
625 static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
629 &tegra_extern##_id, \
636 #define CLK_OUT_CLK(_name, _index) \
637 static struct clk tegra_##_name; \
638 static struct clk_tegra tegra_##_name##_hw = { \
640 .clk = &tegra_##_name, \
644 .con_id = "extern" #_index, \
646 .flags = MUX_CLK_OUT, \
647 .fixed_rate = 216000000, \
650 .clk_num = (_index - 1) * 8 + 2, \
653 static struct clk tegra_##_name = { \
655 .ops = &tegra_clk_out_ops, \
656 .hw = &tegra_##_name##_hw.hw, \
657 .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
658 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
659 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
662 CLK_OUT_CLK(clk_out_1, 1);
663 CLK_OUT_CLK(clk_out_2, 2);
664 CLK_OUT_CLK(clk_out_3, 3);
666 static struct clk *tegra_clk_out_list[] = {
672 static const char *mux_sclk[] = {
683 static struct clk *mux_sclk_p[] = {
694 static struct clk tegra_clk_sclk;
695 static struct clk_tegra tegra_clk_sclk_hw = {
697 .clk = &tegra_clk_sclk,
700 .max_rate = 334000000,
701 .min_rate = 40000000,
704 static struct clk tegra_clk_sclk = {
706 .ops = &tegra30_super_ops,
707 .hw = &tegra_clk_sclk_hw.hw,
708 .parent_names = mux_sclk,
709 .parents = mux_sclk_p,
710 .num_parents = ARRAY_SIZE(mux_sclk),
713 static const char *mux_blink[] = {
717 static struct clk *mux_blink_p[] = {
721 static struct clk tegra_clk_blink;
722 static struct clk_tegra tegra_clk_blink_hw = {
724 .clk = &tegra_clk_blink,
729 static struct clk tegra_clk_blink = {
731 .ops = &tegra30_blink_clk_ops,
732 .hw = &tegra_clk_blink_hw.hw,
733 .parent = &tegra_clk_32k,
734 .parent_names = mux_blink,
735 .parents = mux_blink_p,
736 .num_parents = ARRAY_SIZE(mux_blink),
739 static const char *mux_pllm_pllc_pllp_plla[] = {
746 static const char *mux_pllp_pllc_pllm_clkm[] = {
753 static const char *mux_pllp_clkm[] = {
760 static const char *mux_pllp_plld_pllc_clkm[] = {
767 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
777 static const char *mux_plla_pllc_pllp_clkm[] = {
784 static const char *mux_pllp_pllc_clk32_clkm[] = {
791 static const char *mux_pllp_pllc_clkm_clk32[] = {
798 static const char *mux_pllp_pllc_pllm[] = {
804 static const char *mux_clk_m[] = {
808 static const char *mux_pllp_out3[] = {
812 static const char *mux_plld_out0[] = {
816 static const char *mux_plld_out0_plld2_out0[] = {
821 static const char *mux_clk_32k[] = {
825 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
833 static const char *mux_cclk_g[] = {
845 static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
852 static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
859 static struct clk *mux_pllp_clkm_p[] = {
866 static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
873 static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
883 static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
890 static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
897 static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
904 static struct clk *mux_pllp_pllc_pllm_p[] = {
910 static struct clk *mux_clk_m_p[] = {
914 static struct clk *mux_pllp_out3_p[] = {
918 static struct clk *mux_plld_out0_p[] = {
922 static struct clk *mux_plld_out0_plld2_out0_p[] = {
927 static struct clk *mux_clk_32k_p[] = {
931 static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
939 static struct clk *mux_cclk_g_p[] = {
951 static struct clk tegra_clk_cclk_g;
952 static struct clk_tegra tegra_clk_cclk_g_hw = {
954 .clk = &tegra_clk_cclk_g,
956 .flags = DIV_U71 | DIV_U71_INT,
958 .max_rate = 1700000000,
960 static struct clk tegra_clk_cclk_g = {
962 .ops = &tegra30_super_ops,
963 .hw = &tegra_clk_cclk_g_hw.hw,
964 .parent_names = mux_cclk_g,
965 .parents = mux_cclk_g_p,
966 .num_parents = ARRAY_SIZE(mux_cclk_g),
969 static const char *mux_twd[] = {
973 static struct clk *mux_twd_p[] = {
977 static struct clk tegra30_clk_twd;
978 static struct clk_tegra tegra30_clk_twd_hw = {
980 .clk = &tegra30_clk_twd,
982 .max_rate = 1400000000,
987 static struct clk tegra30_clk_twd = {
989 .ops = &tegra30_twd_ops,
990 .hw = &tegra30_clk_twd_hw.hw,
991 .parent = &tegra_clk_cclk_g,
992 .parent_names = mux_twd,
993 .parents = mux_twd_p,
994 .num_parents = ARRAY_SIZE(mux_twd),
997 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
998 _max, _inputs, _flags) \
999 static struct clk tegra_##_name; \
1000 static struct clk_tegra tegra_##_name##_hw = { \
1002 .clk = &tegra_##_name, \
1012 .clk_num = _clk_num, \
1014 .reset = &tegra30_periph_clk_reset, \
1016 static struct clk tegra_##_name = { \
1018 .ops = &tegra30_periph_clk_ops, \
1019 .hw = &tegra_##_name##_hw.hw, \
1020 .parent_names = _inputs, \
1021 .parents = _inputs##_p, \
1022 .num_parents = ARRAY_SIZE(_inputs), \
1025 PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
1026 PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1027 PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1028 PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
1029 PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
1030 PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1031 PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1032 PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
1033 PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1034 PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1035 PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1036 PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1037 PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1038 PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1039 PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
1040 PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1041 PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1042 PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1043 PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1044 PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1045 PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1046 PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1047 PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
1048 PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1049 PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1050 PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1051 PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1052 PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1053 PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1054 PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1055 PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1056 PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
1057 PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1058 PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1059 PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1060 PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1061 PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1062 PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1063 PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1064 PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
1065 PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
1066 PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
1067 PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1068 PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
1069 PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1070 PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1071 PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1072 PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1073 PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1074 PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1075 PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1076 PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1077 PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1078 PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1079 PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1080 PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1081 PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1082 PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1083 PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1084 PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1085 PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1086 PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1087 PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
1088 PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1089 PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1090 PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1091 PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1092 PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1093 PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
1094 PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
1095 PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1096 PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1097 PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1098 PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1099 PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1100 PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1101 PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
1102 PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
1103 PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
1104 PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
1105 PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
1106 PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
1107 PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1108 PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1109 PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1110 PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1111 PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
1112 PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
1113 PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1115 static struct clk tegra_dsib;
1116 static struct clk_tegra tegra_dsib_hw = {
1121 .dev_id = "tegradc.1",
1125 .flags = MUX | PLLD,
1126 .max_rate = 500000000,
1130 .reset = &tegra30_periph_clk_reset,
1132 static struct clk tegra_dsib = {
1134 .ops = &tegra30_dsib_clk_ops,
1135 .hw = &tegra_dsib_hw.hw,
1136 .parent_names = mux_plld_out0_plld2_out0,
1137 .parents = mux_plld_out0_plld2_out0_p,
1138 .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1141 struct clk *tegra_list_clks[] = {
1163 &tegra_hda2codec_2x,
1234 #define CLK_DUPLICATE(_name, _dev, _con) \
1243 /* Some clocks may be used by different drivers depending on the board
1244 * configuration. List those here to register them twice in the clock lookup
1245 * table under two names.
1247 struct clk_duplicate tegra_clk_duplicates[] = {
1248 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1249 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1250 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1251 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1252 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1253 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1254 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1255 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1256 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1257 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1258 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1259 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1260 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1261 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1262 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1263 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1264 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1265 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1266 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1267 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1268 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1269 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1270 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1271 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1272 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1273 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1274 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1275 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1276 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1277 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1278 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1279 CLK_DUPLICATE("twd", "smp_twd", NULL),
1280 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1281 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1282 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1283 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1284 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1285 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1286 CLK_DUPLICATE("dam0", NULL, "dam0"),
1287 CLK_DUPLICATE("dam1", NULL, "dam1"),
1288 CLK_DUPLICATE("dam2", NULL, "dam2"),
1289 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1292 struct clk *tegra_ptr_clks[] = {
1326 static void tegra30_init_one_clock(struct clk *c)
1328 struct clk_tegra *clk = to_clk_tegra(c->hw);
1329 __clk_init(NULL, c);
1330 INIT_LIST_HEAD(&clk->shared_bus_list);
1331 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1332 clk->lookup.con_id = c->name;
1333 clk->lookup.clk = c;
1334 clkdev_add(&clk->lookup);
1338 void __init tegra30_init_clocks(void)
1343 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1344 tegra30_init_one_clock(tegra_ptr_clks[i]);
1346 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1347 tegra30_init_one_clock(tegra_list_clks[i]);
1349 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1350 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1352 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1353 tegra_clk_duplicates[i].name);
1357 tegra_clk_duplicates[i].lookup.clk = c;
1358 clkdev_add(&tegra_clk_duplicates[i].lookup);
1361 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1362 tegra30_init_one_clock(tegra_sync_source_list[i]);
1363 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1364 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1365 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1366 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1368 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1369 tegra30_init_one_clock(tegra_clk_out_list[i]);