2 * Copyright (C) ST-Ericsson SA 2011
4 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/of_address.h>
11 #include <asm/hardware/cache-l2x0.h>
13 #include "db8500-regs.h"
16 static int __init ux500_l2x0_unlock(void)
19 struct device_node *np;
20 void __iomem *l2x0_base;
22 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
23 l2x0_base = of_iomap(np, 0);
29 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
30 * apparently locks both caches before jumping to the kernel. The
31 * l2x0 core will not touch the unlock registers if the l2x0 is
32 * already enabled, so we do it right here instead. The PL310 has
33 * 8 sets of registers, one per possible CPU.
35 for (i = 0; i < 8; i++) {
36 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
37 i * L2X0_LOCKDOWN_STRIDE);
38 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
39 i * L2X0_LOCKDOWN_STRIDE);
45 static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
48 * We can't write to secure registers as we are in non-secure
49 * mode, until we have some SMI service available.
53 static int __init ux500_l2x0_init(void)
55 /* Multiplatform guard */
56 if (!((cpu_is_u8500_family() || cpu_is_ux540_family())))
59 /* Unlock before init */
61 outer_cache.write_sec = ux500_l2c310_write_sec;
66 early_initcall(ux500_l2x0_init);