2 * Copyright (C) 2002 ARM Ltd.
3 * Copyright (C) 2008 STMicroelctronics.
4 * Copyright (C) 2009 ST-Ericsson.
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
7 * This file is based on arm realview platform
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/errno.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
19 #include <linux/irqchip/arm-gic.h>
21 #include <asm/cacheflush.h>
22 #include <asm/smp_plat.h>
23 #include <asm/smp_scu.h>
25 #include <mach/hardware.h>
26 #include <mach/setup.h>
30 /* This is called from headsmp.S to wakeup the secondary core */
31 extern void u8500_secondary_startup(void);
34 * Write pen_release in a way that is guaranteed to be visible to all
35 * observers, irrespective of whether they're taking part in coherency
36 * or not. This is necessary for the hotplug code to work reliably.
38 static void write_pen_release(int val)
42 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
43 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
46 static void __iomem *scu_base_addr(void)
48 if (cpu_is_u8500_family() || cpu_is_ux540_family())
49 return __io_address(U8500_SCU_BASE);
56 static DEFINE_SPINLOCK(boot_lock);
58 static void __cpuinit ux500_secondary_init(unsigned int cpu)
61 * if any interrupts are already enabled for the primary
62 * core (e.g. timer irq), then they will not have been enabled
65 gic_secondary_init(0);
68 * let the primary processor know we're out of the
69 * pen, then head off into the C entry point
71 write_pen_release(-1);
74 * Synchronise with the boot thread.
76 spin_lock(&boot_lock);
77 spin_unlock(&boot_lock);
80 static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
82 unsigned long timeout;
85 * set synchronisation state between this boot processor
86 * and the secondary one
88 spin_lock(&boot_lock);
91 * The secondary processor is waiting to be released from
92 * the holding pen - release it, then wait for it to flag
93 * that it has been released by resetting pen_release.
95 write_pen_release(cpu_logical_map(cpu));
97 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
99 timeout = jiffies + (1 * HZ);
100 while (time_before(jiffies, timeout)) {
101 if (pen_release == -1)
106 * now the secondary core is starting up let it run its
107 * calibrations, then wait for it to finish
109 spin_unlock(&boot_lock);
111 return pen_release != -1 ? -ENOSYS : 0;
114 static void __init wakeup_secondary(void)
116 void __iomem *backupram;
118 if (cpu_is_u8500_family() || cpu_is_ux540_family())
119 backupram = __io_address(U8500_BACKUPRAM0_BASE);
124 * write the address of secondary startup into the backup ram register
125 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
126 * backup ram register at offset 0x1FF0, which is what boot rom code
127 * is waiting for. This would wake up the secondary core from WFE
129 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
130 __raw_writel(virt_to_phys(u8500_secondary_startup),
131 backupram + UX500_CPU1_JUMPADDR_OFFSET);
133 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
134 __raw_writel(0xA1FEED01,
135 backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
137 /* make sure write buffer is drained */
142 * Initialise the CPU possible map early - this describes the CPUs
143 * which may be present or become present in the system.
145 static void __init ux500_smp_init_cpus(void)
147 void __iomem *scu_base = scu_base_addr();
148 unsigned int i, ncores;
150 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
153 if (ncores > nr_cpu_ids) {
154 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
159 for (i = 0; i < ncores; i++)
160 set_cpu_possible(i, true);
163 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
166 scu_enable(scu_base_addr());
170 struct smp_operations ux500_smp_ops __initdata = {
171 .smp_init_cpus = ux500_smp_init_cpus,
172 .smp_prepare_cpus = ux500_smp_prepare_cpus,
173 .smp_secondary_init = ux500_secondary_init,
174 .smp_boot_secondary = ux500_boot_secondary,
175 #ifdef CONFIG_HOTPLUG_CPU
176 .cpu_die = ux500_cpu_die,