4 * Copyright (c) 2011-2013 Xilinx Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * You should have received a copy of the GNU General Public
12 * License along with this program; if not, write to the Free
13 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
18 #include <linux/mfd/syscon.h>
19 #include <linux/of_address.h>
20 #include <linux/regmap.h>
21 #include <linux/clk/zynq.h>
24 /* register offsets */
25 #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
26 #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
27 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
28 #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
29 #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
31 #define SLCR_UNLOCK_MAGIC 0xDF0D
32 #define SLCR_A9_CPU_CLKSTOP 0x10
33 #define SLCR_A9_CPU_RST 0x1
34 #define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
35 #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
37 static void __iomem *zynq_slcr_base;
38 static struct regmap *zynq_slcr_regmap;
41 * zynq_slcr_write - Write to a register in SLCR block
43 * @val: Value to write to the register
44 * @offset: Register offset in SLCR block
46 * Return: a negative value on error, 0 on success
48 static int zynq_slcr_write(u32 val, u32 offset)
50 return regmap_write(zynq_slcr_regmap, offset, val);
54 * zynq_slcr_read - Read a register in SLCR block
56 * @val: Pointer to value to be read from SLCR
57 * @offset: Register offset in SLCR block
59 * Return: a negative value on error, 0 on success
61 static int zynq_slcr_read(u32 *val, u32 offset)
63 return regmap_read(zynq_slcr_regmap, offset, val);
67 * zynq_slcr_unlock - Unlock SLCR registers
69 * Return: a negative value on error, 0 on success
71 static inline int zynq_slcr_unlock(void)
73 zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
79 * zynq_slcr_get_device_id - Read device code id
81 * Return: Device code id
83 u32 zynq_slcr_get_device_id(void)
87 zynq_slcr_read(&val, SLCR_PSS_IDCODE);
88 val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
89 val &= SLCR_PSS_IDCODE_DEVICE_MASK;
95 * zynq_slcr_system_reset - Reset the entire system.
97 void zynq_slcr_system_reset(void)
102 * Unlock the SLCR then reset the system.
103 * Note that this seems to require raw i/o
104 * functions or there's a lockup?
109 * Clear 0x0F000000 bits of reboot status register to workaround
110 * the FSBL not loading the bitstream after soft-reboot
111 * This is a temporary solution until we know more.
113 zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
114 zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
115 zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
119 * zynq_slcr_cpu_start - Start cpu
122 void zynq_slcr_cpu_start(int cpu)
126 zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
127 reg &= ~(SLCR_A9_CPU_RST << cpu);
128 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
129 reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
130 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
132 zynq_slcr_cpu_state_write(cpu, false);
136 * zynq_slcr_cpu_stop - Stop cpu
139 void zynq_slcr_cpu_stop(int cpu)
143 zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
144 reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
145 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
149 * zynq_slcr_cpu_state - Read/write cpu state
152 * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
153 * 0 means cpu is running, 1 cpu is going to die.
155 * Return: true if cpu is running, false if cpu is going to die
157 bool zynq_slcr_cpu_state_read(int cpu)
161 state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
162 state &= 1 << (31 - cpu);
168 * zynq_slcr_cpu_state - Read/write cpu state
170 * @die: cpu state - true if cpu is going to die
172 * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
173 * 0 means cpu is running, 1 cpu is going to die.
175 void zynq_slcr_cpu_state_write(int cpu, bool die)
179 state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
180 mask = 1 << (31 - cpu);
185 writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
189 * zynq_early_slcr_init - Early slcr init function
191 * Return: 0 on success, negative errno otherwise.
193 * Called very early during boot from platform code to unlock SLCR.
195 int __init zynq_early_slcr_init(void)
197 struct device_node *np;
199 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
201 pr_err("%s: no slcr node found\n", __func__);
205 zynq_slcr_base = of_iomap(np, 0);
206 if (!zynq_slcr_base) {
207 pr_err("%s: Unable to map I/O memory\n", __func__);
211 np->data = (__force void *)zynq_slcr_base;
213 zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
214 if (IS_ERR(zynq_slcr_regmap)) {
215 pr_err("%s: failed to find zynq-slcr\n", __func__);
219 /* unlock the SLCR so that registers can be changed */
222 pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);