1 comment "Processor Type"
3 # Select CPU types depending on the architecture selected. This selects
4 # which CPUs we support in the kernel image, and the compiler instruction
9 bool "Support ARM7TDMI processor"
14 select CPU_PABRT_LEGACY
16 A 32-bit RISC microprocessor based on the ARM7 processor core
17 which has no memory control unit and cache.
19 Say Y if you want support for the ARM7TDMI processor.
24 bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
29 select CPU_COPY_V4WT if MMU
31 select CPU_PABRT_LEGACY
32 select CPU_TLB_V4WT if MMU
34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
35 MMU built around an ARM7TDMI core.
37 Say Y if you want support for the ARM720T processor.
42 bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
48 select CPU_PABRT_LEGACY
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
51 write buffer and MPU(Protection Unit) built around
54 Say Y if you want support for the ARM740T processor.
59 bool "Support ARM9TDMI processor"
64 select CPU_PABRT_LEGACY
66 A 32-bit RISC microprocessor based on the ARM9 processor core
67 which has no memory control unit and cache.
69 Say Y if you want support for the ARM9TDMI processor.
74 bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
79 select CPU_COPY_V4WB if MMU
81 select CPU_PABRT_LEGACY
82 select CPU_TLB_V4WBI if MMU
84 The ARM920T is licensed to be produced by numerous vendors,
85 and is used in the Cirrus EP93xx and the Samsung S3C2410.
87 Say Y if you want support for the ARM920T processor.
92 bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
97 select CPU_COPY_V4WB if MMU
99 select CPU_PABRT_LEGACY
100 select CPU_TLB_V4WBI if MMU
102 The ARM922T is a version of the ARM920T, but with smaller
103 instruction and data caches. It is used in Altera's
104 Excalibur XA device family and Micrel's KS8695 Centaur.
106 Say Y if you want support for the ARM922T processor.
111 bool "Support ARM925T processor" if ARCH_OMAP1
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
116 select CPU_COPY_V4WB if MMU
118 select CPU_PABRT_LEGACY
119 select CPU_TLB_V4WBI if MMU
121 The ARM925T is a mix between the ARM920T and ARM926T, but with
122 different instruction and data caches. It is used in TI's OMAP
125 Say Y if you want support for the ARM925T processor.
130 bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB)
132 select CPU_ABRT_EV5TJ
133 select CPU_CACHE_VIVT
134 select CPU_COPY_V4WB if MMU
136 select CPU_PABRT_LEGACY
137 select CPU_TLB_V4WBI if MMU
139 This is a variant of the ARM920. It has slightly different
140 instruction sequences for cache and TLB operations. Curiously,
141 there is no documentation on it at the ARM corporate website.
143 Say Y if you want support for the ARM926T processor.
152 select CPU_CACHE_VIVT
153 select CPU_COPY_FA if MMU
155 select CPU_PABRT_LEGACY
156 select CPU_TLB_FA if MMU
158 The FA526 is a version of the ARMv4 compatible processor with
159 Branch Target Buffer, Unified TLB and cache line size 16.
161 Say Y if you want support for the FA526 processor.
166 bool "Support ARM940T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
169 select CPU_ABRT_NOMMU
170 select CPU_CACHE_VIVT
172 select CPU_PABRT_LEGACY
174 ARM940T is a member of the ARM9TDMI family of general-
175 purpose microprocessors with MPU and separate 4KB
176 instruction and 4KB data cases, each with a 4-word line
179 Say Y if you want support for the ARM940T processor.
184 bool "Support ARM946E-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
187 select CPU_ABRT_NOMMU
188 select CPU_CACHE_VIVT
190 select CPU_PABRT_LEGACY
192 ARM946E-S is a member of the ARM9E-S family of high-
193 performance, 32-bit system-on-chip processor solutions.
194 The TCM and ARMv5TE 32-bit instruction set is supported.
196 Say Y if you want support for the ARM946E-S processor.
199 # ARM1020 - needs validating
201 bool "Support ARM1020T (rev 0) processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
204 select CPU_CACHE_V4WT
205 select CPU_CACHE_VIVT
206 select CPU_COPY_V4WB if MMU
208 select CPU_PABRT_LEGACY
209 select CPU_TLB_V4WBI if MMU
211 The ARM1020 is the 32K cached version of the ARM10 processor,
212 with an addition of a floating-point unit.
214 Say Y if you want support for the ARM1020 processor.
217 # ARM1020E - needs validating
219 bool "Support ARM1020E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
223 select CPU_CACHE_V4WT
224 select CPU_CACHE_VIVT
225 select CPU_COPY_V4WB if MMU
227 select CPU_PABRT_LEGACY
228 select CPU_TLB_V4WBI if MMU
232 bool "Support ARM1022E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
235 select CPU_CACHE_VIVT
236 select CPU_COPY_V4WB if MMU # can probably do better
238 select CPU_PABRT_LEGACY
239 select CPU_TLB_V4WBI if MMU
241 The ARM1022E is an implementation of the ARMv5TE architecture
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243 embedded trace macrocell, and a floating-point unit.
245 Say Y if you want support for the ARM1022E processor.
250 bool "Support ARM1026EJ-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253 select CPU_CACHE_VIVT
254 select CPU_COPY_V4WB if MMU # can probably do better
256 select CPU_PABRT_LEGACY
257 select CPU_TLB_V4WBI if MMU
259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260 based upon the ARM10 integer core.
262 Say Y if you want support for the ARM1026EJ-S processor.
268 select CPU_32v3 if ARCH_RPC
269 select CPU_32v4 if !ARCH_RPC
271 select CPU_CACHE_V4WB
272 select CPU_CACHE_VIVT
273 select CPU_COPY_V4WB if MMU
275 select CPU_PABRT_LEGACY
276 select CPU_TLB_V4WB if MMU
278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279 is available at five speeds ranging from 100 MHz to 233 MHz.
280 More information is available at
281 <http://developer.intel.com/design/strong/sa110.htm>.
283 Say Y if you want support for the SA-110 processor.
291 select CPU_CACHE_V4WB
292 select CPU_CACHE_VIVT
294 select CPU_PABRT_LEGACY
295 select CPU_TLB_V4WB if MMU
302 select CPU_CACHE_VIVT
304 select CPU_PABRT_LEGACY
305 select CPU_TLB_V4WBI if MMU
307 # XScale Core Version 3
312 select CPU_CACHE_VIVT
314 select CPU_PABRT_LEGACY
315 select CPU_TLB_V4WBI if MMU
318 # Marvell PJ1 (Mohawk)
323 select CPU_CACHE_VIVT
324 select CPU_COPY_V4WB if MMU
326 select CPU_PABRT_LEGACY
327 select CPU_TLB_V4WBI if MMU
334 select CPU_CACHE_VIVT
335 select CPU_COPY_FEROCEON if MMU
337 select CPU_PABRT_LEGACY
338 select CPU_TLB_FEROCEON if MMU
340 config CPU_FEROCEON_OLD_ID
341 bool "Accept early Feroceon cores with an ARM926 ID"
342 depends on CPU_FEROCEON && !CPU_ARM926T
345 This enables the usage of some old Feroceon cores
346 for which the CPU ID is equal to the ARM926 ID.
347 Relevant for Feroceon-1850 and early Feroceon-2850.
361 bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
365 select CPU_CACHE_VIPT
366 select CPU_COPY_V6 if MMU
368 select CPU_HAS_ASID if MMU
370 select CPU_TLB_V6 if MMU
374 bool "Support ARM V6K processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
379 select CPU_CACHE_VIPT
380 select CPU_COPY_V6 if MMU
382 select CPU_HAS_ASID if MMU
384 select CPU_TLB_V6 if MMU
388 bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
393 select CPU_CACHE_VIPT
394 select CPU_COPY_V6 if MMU
395 select CPU_CP15_MMU if MMU
396 select CPU_CP15_MPU if !MMU
397 select CPU_HAS_ASID if MMU
399 select CPU_TLB_V7 if MMU
405 select CPU_ABRT_NOMMU
407 select CPU_PABRT_LEGACY
412 # There are no CPUs available with MMU that don't implement an ARM ISA:
415 Select this if your CPU doesn't support the 32 bit ARM instructions.
417 # Figure out what processor architecture version we should be using.
418 # This defines the compiler instruction set which depends on the machine type.
421 select CPU_USE_DOMAINS if MMU
422 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
423 select NEED_KUSER_HELPERS
424 select TLS_REG_EMUL if SMP || !MMU
428 select CPU_USE_DOMAINS if MMU
429 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
430 select NEED_KUSER_HELPERS
431 select TLS_REG_EMUL if SMP || !MMU
435 select CPU_USE_DOMAINS if MMU
436 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
437 select NEED_KUSER_HELPERS
438 select TLS_REG_EMUL if SMP || !MMU
442 select CPU_USE_DOMAINS if MMU
443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select NEED_KUSER_HELPERS
445 select TLS_REG_EMUL if SMP || !MMU
449 select TLS_REG_EMUL if !CPU_32v6K && !MMU
461 config CPU_ABRT_NOMMU
476 config CPU_ABRT_EV5TJ
485 config CPU_PABRT_LEGACY
498 config CPU_CACHE_V4WT
501 config CPU_CACHE_V4WB
513 config CPU_CACHE_VIVT
516 config CPU_CACHE_VIPT
523 # The copy-page model
530 config CPU_COPY_FEROCEON
539 # This selects the TLB model
543 ARM Architecture Version 4 TLB with writethrough cache.
548 ARM Architecture Version 4 TLB with writeback cache.
553 ARM Architecture Version 4 TLB with writeback cache and invalidate
554 instruction cache entry.
556 config CPU_TLB_FEROCEON
559 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
564 Faraday ARM FA526 architecture, unified TLB with writeback cache
565 and invalidate instruction cache entry. Branch target buffer is
574 config VERIFY_PERMISSION_FAULT
581 This indicates whether the CPU has the ASID register; used to
582 tag TLB and possibly cache entries.
587 Processor has the CP15 register.
593 Processor has the CP15 register, which has MMU related registers.
599 Processor has the CP15 register, which has MPU related registers.
601 config CPU_USE_DOMAINS
604 This option enables or disables the use of domain switching
605 via the set_fs() function.
607 config CPU_V7M_NUM_IRQ
608 int "Number of external interrupts connected to the NVIC"
610 default 90 if ARCH_STM32
611 default 38 if ARCH_EFM32
612 default 112 if SOC_VF610
615 This option indicates the number of interrupts connected to the NVIC.
616 The value can be larger than the real number of interrupts supported
617 by the system, but must not be lower.
618 The default value is 240, corresponding to the maximum number of
619 interrupts supported by the NVIC on Cortex-M family.
621 If unsure, keep default value.
624 # CPU supports 36-bit I/O
629 comment "Processor Features"
632 bool "Support for the Large Physical Address Extension"
633 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
634 !CPU_32v4 && !CPU_32v3
636 Say Y if you have an ARMv7 processor supporting the LPAE page
637 table format and you would like to access memory beyond the
638 4GB limit. The resulting kernel image will not run on
639 processors without the LPA extension.
643 config ARCH_PHYS_ADDR_T_64BIT
646 config ARCH_DMA_ADDR_T_64BIT
650 bool "Support Thumb user binaries" if !CPU_THUMBONLY
651 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
652 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
653 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
654 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
655 CPU_V7 || CPU_FEROCEON || CPU_V7M
658 Say Y if you want to include kernel support for running user space
661 The Thumb instruction set is a compressed form of the standard ARM
662 instruction set resulting in smaller binaries at the expense of
663 slightly less efficient code.
665 If you don't know what this all is, saying Y is a safe choice.
668 bool "Enable ThumbEE CPU extension"
671 Say Y here if you have a CPU with the ThumbEE extension and code to
672 make use of it. Say N for code that can run on CPUs without ThumbEE.
679 Enable the kernel to make use of the ARM Virtualization
680 Extensions to install hypervisors without run-time firmware
683 A compliant bootloader is required in order to make maximum
684 use of this feature. Refer to Documentation/arm/Booting for
688 bool "Emulate SWP/SWPB instructions" if !SMP
691 select HAVE_PROC_CPU if PROC_FS
693 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
694 ARMv7 multiprocessing extensions introduce the ability to disable
695 these instructions, triggering an undefined instruction exception
696 when executed. Say Y here to enable software emulation of these
697 instructions for userspace (not kernel) using LDREX/STREX.
698 Also creates /proc/cpu/swp_emulation for statistics.
700 In some older versions of glibc [<=2.8] SWP is used during futex
701 trylock() operations with the assumption that the code will not
702 be preempted. This invalid assumption may be more likely to fail
703 with SWP emulation enabled, leading to deadlock of the user
706 NOTE: when accessing uncached shared regions, LDREX/STREX rely
707 on an external transaction monitoring block called a global
708 monitor to maintain update atomicity. If your system does not
709 implement a global monitor, this option can cause programs that
710 perform SWP operations to uncached memory to deadlock.
714 config CPU_BIG_ENDIAN
715 bool "Build big-endian kernel"
716 depends on ARCH_SUPPORTS_BIG_ENDIAN
718 Say Y if you plan on running a kernel in big-endian mode.
719 Note that your board must be properly built and your board
720 port must properly enable any big-endian related features
721 of your chipset/board/processor.
723 config CPU_ENDIAN_BE8
725 depends on CPU_BIG_ENDIAN
726 default CPU_V6 || CPU_V6K || CPU_V7
728 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
730 config CPU_ENDIAN_BE32
732 depends on CPU_BIG_ENDIAN
733 default !CPU_ENDIAN_BE8
735 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
737 config CPU_HIGH_VECTOR
738 depends on !MMU && CPU_CP15 && !CPU_ARM740T
739 bool "Select the High exception vector"
741 Say Y here to select high exception vector(0xFFFF0000~).
742 The exception vector can vary depending on the platform
743 design in nommu mode. If your platform needs to select
744 high exception vector, say Y.
745 Otherwise or if you are unsure, say N, and the low exception
746 vector (0x00000000~) will be used.
748 config CPU_ICACHE_DISABLE
749 bool "Disable I-Cache (I-bit)"
750 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
752 Say Y here to disable the processor instruction cache. Unless
753 you have a reason not to or are unsure, say N.
755 config CPU_DCACHE_DISABLE
756 bool "Disable D-Cache (C-bit)"
757 depends on CPU_CP15 && !SMP
759 Say Y here to disable the processor data cache. Unless
760 you have a reason not to or are unsure, say N.
762 config CPU_DCACHE_SIZE
764 depends on CPU_ARM740T || CPU_ARM946E
765 default 0x00001000 if CPU_ARM740T
766 default 0x00002000 # default size for ARM946E-S
768 Some cores are synthesizable to have various sized cache. For
769 ARM946E-S case, it can vary from 0KB to 1MB.
770 To support such cache operations, it is efficient to know the size
772 If your SoC is configured to have a different size, define the value
773 here with proper conditions.
775 config CPU_DCACHE_WRITETHROUGH
776 bool "Force write through D-cache"
777 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
778 default y if CPU_ARM925T
780 Say Y here to use the data cache in writethrough mode. Unless you
781 specifically require this or are unsure, say N.
783 config CPU_CACHE_ROUND_ROBIN
784 bool "Round robin I and D cache replacement algorithm"
785 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
787 Say Y here to use the predictable round-robin cache replacement
788 policy. Unless you specifically require this or are unsure, say N.
790 config CPU_BPREDICT_DISABLE
791 bool "Disable branch prediction"
792 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
794 Say Y here to disable branch prediction. If unsure, say N.
798 select NEED_KUSER_HELPERS
800 An SMP system using a pre-ARMv6 processor (there are apparently
801 a few prototypes like that in existence) and therefore access to
802 that required register must be emulated.
804 config NEEDS_SYSCALL_FOR_CMPXCHG
806 select NEED_KUSER_HELPERS
808 SMP on a pre-ARMv6 processor? Well OK then.
809 Forget about fast user space cmpxchg support.
810 It is just not possible.
812 config NEED_KUSER_HELPERS
816 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
820 Warning: disabling this option may break user programs.
822 Provide kuser helpers in the vector page. The kernel provides
823 helper code to userspace in read only form at a fixed location
824 in the high vector page to allow userspace to be independent of
825 the CPU type fitted to the system. This permits binaries to be
826 run on ARMv4 through to ARMv7 without modification.
828 See Documentation/arm/kernel_user_helpers.txt for details.
830 However, the fixed address nature of these helpers can be used
831 by ROP (return orientated programming) authors when creating
834 If all of the binaries and libraries which run on your platform
835 are built specifically for your platform, and make no use of
836 these helpers, then you can turn this option off to hinder
837 such exploits. However, in that case, if a binary or library
838 relying on those helpers is run, it will receive a SIGILL signal,
839 which will terminate the program.
841 Say N here only if you are absolutely certain that you do not
842 need these helpers; otherwise, the safe option is to say Y.
845 bool "Enable VDSO for acceleration of some system calls"
846 depends on AEABI && MMU && CPU_V7
847 default y if ARM_ARCH_TIMER
848 select GENERIC_TIME_VSYSCALL
850 Place in the process address space an ELF shared object
851 providing fast implementations of gettimeofday and
852 clock_gettime. Systems that implement the ARM architected
853 timer will receive maximum benefit.
855 You must have glibc 2.22 or later for programs to seamlessly
856 take advantage of this.
858 config DMA_CACHE_RWFO
859 bool "Enable read/write for ownership DMA cache maintenance"
860 depends on CPU_V6K && SMP
863 The Snoop Control Unit on ARM11MPCore does not detect the
864 cache maintenance operations and the dma_{map,unmap}_area()
865 functions may leave stale cache entries on other CPUs. By
866 enabling this option, Read or Write For Ownership in the ARMv6
867 DMA cache maintenance functions is performed. These LDR/STR
868 instructions change the cache line state to shared or modified
869 so that the cache operation has the desired effect.
871 Note that the workaround is only valid on processors that do
872 not perform speculative loads into the D-cache. For such
873 processors, if cache maintenance operations are not broadcast
874 in hardware, other workarounds are needed (e.g. cache
875 maintenance broadcasting in software via FIQ).
880 config OUTER_CACHE_SYNC
883 The outer cache has a outer_cache_fns.sync function pointer
884 that can be used to drain the write buffer of the outer cache.
886 config CACHE_FEROCEON_L2
887 bool "Enable the Feroceon L2 cache controller"
888 depends on ARCH_MV78XX0 || ARCH_MVEBU
892 This option enables the Feroceon L2 cache controller.
894 config CACHE_FEROCEON_L2_WRITETHROUGH
895 bool "Force Feroceon L2 cache write through"
896 depends on CACHE_FEROCEON_L2
898 Say Y here to use the Feroceon L2 cache in writethrough mode.
899 Unless you specifically require this, say N for writeback mode.
901 config MIGHT_HAVE_CACHE_L2X0
904 This option should be selected by machines which have a L2x0
905 or PL310 cache controller, but where its use is optional.
907 The only effect of this option is to make CACHE_L2X0 and
908 related options available to the user for configuration.
910 Boards or SoCs which always require the cache controller
911 support to be present should select CACHE_L2X0 directly
912 instead of this option, thus preventing the user from
913 inadvertently configuring a broken kernel.
916 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
917 default MIGHT_HAVE_CACHE_L2X0
919 select OUTER_CACHE_SYNC
921 This option enables the L2x0 PrimeCell.
925 config PL310_ERRATA_588369
926 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
928 The PL310 L2 cache controller implements three types of Clean &
929 Invalidate maintenance operations: by Physical Address
930 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
931 They are architecturally defined to behave as the execution of a
932 clean operation followed immediately by an invalidate operation,
933 both performing to the same memory location. This functionality
934 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
935 as clean lines are not invalidated as a result of these operations.
937 config PL310_ERRATA_727915
938 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
940 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
941 operation (offset 0x7FC). This operation runs in background so that
942 PL310 can handle normal accesses while it is in progress. Under very
943 rare circumstances, due to this erratum, write data can be lost when
944 PL310 treats a cacheable write transaction during a Clean &
945 Invalidate by Way operation. Revisions prior to r3p1 are affected by
946 this errata (fixed in r3p1).
948 config PL310_ERRATA_753970
949 bool "PL310 errata: cache sync operation may be faulty"
951 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
953 Under some condition the effect of cache sync operation on
954 the store buffer still remains when the operation completes.
955 This means that the store buffer is always asked to drain and
956 this prevents it from merging any further writes. The workaround
957 is to replace the normal offset of cache sync operation (0x730)
958 by another offset targeting an unmapped PL310 register 0x740.
959 This has the same effect as the cache sync operation: store buffer
960 drain and waiting for all buffers empty.
962 config PL310_ERRATA_769419
963 bool "PL310 errata: no automatic Store Buffer drain"
965 On revisions of the PL310 prior to r3p2, the Store Buffer does
966 not automatically drain. This can cause normal, non-cacheable
967 writes to be retained when the memory system is idle, leading
968 to suboptimal I/O performance for drivers using coherent DMA.
969 This option adds a write barrier to the cpu_idle loop so that,
970 on systems with an outer cache, the store buffer is drained
976 bool "Enable the Tauros2 L2 cache controller"
977 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
981 This option enables the Tauros2 L2 cache controller (as
985 bool "Enable the L2 cache on XScale3"
990 This option enables the L2 cache on XScale3.
992 config ARM_L1_CACHE_SHIFT_6
996 Setting ARM L1 cache line size to 64 Bytes.
998 config ARM_L1_CACHE_SHIFT
1000 default 6 if ARM_L1_CACHE_SHIFT_6
1003 config ARM_DMA_MEM_BUFFERABLE
1004 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
1005 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
1006 MACH_REALVIEW_PB11MP)
1007 default y if CPU_V6 || CPU_V6K || CPU_V7
1009 Historically, the kernel has used strongly ordered mappings to
1010 provide DMA coherent memory. With the advent of ARMv7, mapping
1011 memory with differing types results in unpredictable behaviour,
1012 so on these CPUs, this option is forced on.
1014 Multiple mappings with differing attributes is also unpredictable
1015 on ARMv6 CPUs, but since they do not have aggressive speculative
1016 prefetch, no harm appears to occur.
1018 However, drivers may be missing the necessary barriers for ARMv6,
1019 and therefore turning this on may result in unpredictable driver
1020 behaviour. Therefore, we offer this as an option.
1022 You are recommended say 'Y' here and debug any affected drivers.
1024 config ARCH_HAS_BARRIERS
1027 This option allows the use of custom mandatory barriers
1028 included via the mach/barriers.h file.
1030 config ARCH_SUPPORTS_BIG_ENDIAN
1033 This option specifies the architecture can support big endian
1036 config ARM_KERNMEM_PERMS
1037 bool "Restrict kernel memory permissions"
1040 If this is set, kernel memory other than kernel text (and rodata)
1041 will be made non-executable. The tradeoff is that each region is
1042 padded to section-size (1MiB) boundaries (because their permissions
1043 are different and splitting the 1M pages into 4K ones causes TLB
1044 performance problems), wasting memory.
1047 bool "Make kernel text and rodata read-only"
1048 depends on ARM_KERNMEM_PERMS
1051 If this is set, kernel text and rodata will be made read-only. This
1052 is to help catch accidental or malicious attempts to change the
1053 kernel's executable code. Additionally splits rodata from kernel
1054 text so it can be made explicitly non-executable. This creates
1055 another section-size padded region, so it can waste more memory
1056 space while gaining the read-only protections.