1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
25 Say Y if you want support for the ARM610 processor.
30 bool "Support ARM7TDMI processor"
35 A 32-bit RISC microprocessor based on the ARM7 processor core
36 which has no memory control unit and cache.
38 Say Y if you want support for the ARM7TDMI processor.
43 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
44 default y if ARCH_CLPS7500
49 select CPU_COPY_V3 if MMU
50 select CPU_TLB_V3 if MMU
52 A 32-bit RISC microprocessor based on the ARM7 processor core
53 designed by Advanced RISC Machines Ltd. The ARM710 is the
54 successor to the ARM610 processor. It was released in
55 July 1994 by VLSI Technology Inc.
57 Say Y if you want support for the ARM710 processor.
62 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
63 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
69 select CPU_COPY_V4WT if MMU
70 select CPU_TLB_V4WT if MMU
72 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
73 MMU built around an ARM7TDMI core.
75 Say Y if you want support for the ARM720T processor.
80 bool "Support ARM740T processor" if ARCH_INTEGRATOR
83 select CPU_CACHE_V3 # although the core is v4t
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
90 Say Y if you want support for the ARM740T processor.
95 bool "Support ARM9TDMI processor"
100 A 32-bit RISC microprocessor based on the ARM9 processor core
101 which has no memory control unit and cache.
103 Say Y if you want support for the ARM9TDMI processor.
108 bool "Support ARM920T processor"
109 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
110 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
113 select CPU_CACHE_V4WT
114 select CPU_CACHE_VIVT
116 select CPU_COPY_V4WB if MMU
117 select CPU_TLB_V4WBI if MMU
119 The ARM920T is licensed to be produced by numerous vendors,
120 and is used in the Maverick EP9312 and the Samsung S3C2410.
122 More information on the Maverick EP9312 at
123 <http://linuxdevices.com/products/PD2382866068.html>.
125 Say Y if you want support for the ARM920T processor.
130 bool "Support ARM922T processor" if ARCH_INTEGRATOR
131 depends on ARCH_LH7A40X || ARCH_INTEGRATOR
132 default y if ARCH_LH7A40X
135 select CPU_CACHE_V4WT
136 select CPU_CACHE_VIVT
138 select CPU_COPY_V4WB if MMU
139 select CPU_TLB_V4WBI if MMU
141 The ARM922T is a version of the ARM920T, but with smaller
142 instruction and data caches. It is used in Altera's
143 Excalibur XA device family.
145 Say Y if you want support for the ARM922T processor.
150 bool "Support ARM925T processor" if ARCH_OMAP1
151 depends on ARCH_OMAP15XX
152 default y if ARCH_OMAP15XX
155 select CPU_CACHE_V4WT
156 select CPU_CACHE_VIVT
158 select CPU_COPY_V4WB if MMU
159 select CPU_TLB_V4WBI if MMU
161 The ARM925T is a mix between the ARM920T and ARM926T, but with
162 different instruction and data caches. It is used in TI's OMAP
165 Say Y if you want support for the ARM925T processor.
170 bool "Support ARM926T processor"
171 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
172 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
174 select CPU_ABRT_EV5TJ
175 select CPU_CACHE_VIVT
177 select CPU_COPY_V4WB if MMU
178 select CPU_TLB_V4WBI if MMU
180 This is a variant of the ARM920. It has slightly different
181 instruction sequences for cache and TLB operations. Curiously,
182 there is no documentation on it at the ARM corporate website.
184 Say Y if you want support for the ARM926T processor.
189 bool "Support ARM940T processor" if ARCH_INTEGRATOR
192 select CPU_CACHE_VIVT
195 ARM940T is a member of the ARM9TDMI family of general-
196 purpose microprocessors with MPU and seperate 4KB
197 instruction and 4KB data cases, each with a 4-word line
200 Say Y if you want support for the ARM940T processor.
203 # ARM1020 - needs validating
205 bool "Support ARM1020T (rev 0) processor"
206 depends on ARCH_INTEGRATOR
209 select CPU_CACHE_V4WT
210 select CPU_CACHE_VIVT
212 select CPU_COPY_V4WB if MMU
213 select CPU_TLB_V4WBI if MMU
215 The ARM1020 is the 32K cached version of the ARM10 processor,
216 with an addition of a floating-point unit.
218 Say Y if you want support for the ARM1020 processor.
221 # ARM1020E - needs validating
223 bool "Support ARM1020E processor"
224 depends on ARCH_INTEGRATOR
227 select CPU_CACHE_V4WT
228 select CPU_CACHE_VIVT
230 select CPU_COPY_V4WB if MMU
231 select CPU_TLB_V4WBI if MMU
236 bool "Support ARM1022E processor"
237 depends on ARCH_INTEGRATOR
240 select CPU_CACHE_VIVT
242 select CPU_COPY_V4WB if MMU # can probably do better
243 select CPU_TLB_V4WBI if MMU
245 The ARM1022E is an implementation of the ARMv5TE architecture
246 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
247 embedded trace macrocell, and a floating-point unit.
249 Say Y if you want support for the ARM1022E processor.
254 bool "Support ARM1026EJ-S processor"
255 depends on ARCH_INTEGRATOR
257 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
258 select CPU_CACHE_VIVT
260 select CPU_COPY_V4WB if MMU # can probably do better
261 select CPU_TLB_V4WBI if MMU
263 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
264 based upon the ARM10 integer core.
266 Say Y if you want support for the ARM1026EJ-S processor.
271 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
272 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
273 select CPU_32v3 if ARCH_RPC
274 select CPU_32v4 if !ARCH_RPC
276 select CPU_CACHE_V4WB
277 select CPU_CACHE_VIVT
279 select CPU_COPY_V4WB if MMU
280 select CPU_TLB_V4WB if MMU
282 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
283 is available at five speeds ranging from 100 MHz to 233 MHz.
284 More information is available at
285 <http://developer.intel.com/design/strong/sa110.htm>.
287 Say Y if you want support for the SA-110 processor.
293 depends on ARCH_SA1100
297 select CPU_CACHE_V4WB
298 select CPU_CACHE_VIVT
300 select CPU_TLB_V4WB if MMU
305 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
309 select CPU_CACHE_VIVT
311 select CPU_TLB_V4WBI if MMU
313 # XScale Core Version 3
316 depends on ARCH_IXP23XX
320 select CPU_CACHE_VIVT
322 select CPU_TLB_V4WBI if MMU
327 bool "Support ARM V6 processor"
328 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
332 select CPU_CACHE_VIPT
334 select CPU_COPY_V6 if MMU
335 select CPU_TLB_V6 if MMU
339 bool "Support ARM V6K processor extensions" if !SMP
343 Say Y here if your ARMv6 processor supports the 'K' extension.
344 This enables the kernel to use some instructions not present
345 on previous processors, and as such a kernel build with this
346 enabled will not boot on processors with do not support these
349 # Figure out what processor architecture version we should be using.
350 # This defines the compiler instruction set which depends on the machine type.
353 select TLS_REG_EMUL if SMP || !MMU
354 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
358 select TLS_REG_EMUL if SMP || !MMU
359 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
363 select TLS_REG_EMUL if SMP || !MMU
364 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
368 select TLS_REG_EMUL if SMP || !MMU
369 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
387 config CPU_ABRT_EV5TJ
400 config CPU_CACHE_V4WT
403 config CPU_CACHE_V4WB
409 config CPU_CACHE_VIVT
412 config CPU_CACHE_VIPT
416 # The copy-page model
429 # This selects the TLB model
433 ARM Architecture Version 3 TLB.
438 ARM Architecture Version 4 TLB with writethrough cache.
443 ARM Architecture Version 4 TLB with writeback cache.
448 ARM Architecture Version 4 TLB with writeback cache and invalidate
449 instruction cache entry.
459 Processor has the CP15 register.
465 Processor has the CP15 register, which has MMU related registers.
471 Processor has the CP15 register, which has MPU related registers.
474 # CPU supports 36-bit I/O
479 comment "Processor Features"
482 bool "Support Thumb user binaries"
483 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
486 Say Y if you want to include kernel support for running user space
489 The Thumb instruction set is a compressed form of the standard ARM
490 instruction set resulting in smaller binaries at the expense of
491 slightly less efficient code.
493 If you don't know what this all is, saying Y is a safe choice.
495 config CPU_BIG_ENDIAN
496 bool "Build big-endian kernel"
497 depends on ARCH_SUPPORTS_BIG_ENDIAN
499 Say Y if you plan on running a kernel in big-endian mode.
500 Note that your board must be properly built and your board
501 port must properly enable any big-endian related features
502 of your chipset/board/processor.
504 config CPU_ICACHE_DISABLE
505 bool "Disable I-Cache (I-bit)"
506 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
508 Say Y here to disable the processor instruction cache. Unless
509 you have a reason not to or are unsure, say N.
511 config CPU_DCACHE_DISABLE
512 bool "Disable D-Cache (C-bit)"
515 Say Y here to disable the processor data cache. Unless
516 you have a reason not to or are unsure, say N.
518 config CPU_DCACHE_WRITETHROUGH
519 bool "Force write through D-cache"
520 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
521 default y if CPU_ARM925T
523 Say Y here to use the data cache in writethrough mode. Unless you
524 specifically require this or are unsure, say N.
526 config CPU_CACHE_ROUND_ROBIN
527 bool "Round robin I and D cache replacement algorithm"
528 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
530 Say Y here to use the predictable round-robin cache replacement
531 policy. Unless you specifically require this or are unsure, say N.
533 config CPU_BPREDICT_DISABLE
534 bool "Disable branch prediction"
535 depends on CPU_ARM1020 || CPU_V6
537 Say Y here to disable branch prediction. If unsure, say N.
542 An SMP system using a pre-ARMv6 processor (there are apparently
543 a few prototypes like that in existence) and therefore access to
544 that required register must be emulated.
548 depends on !TLS_REG_EMUL
549 default y if SMP || CPU_32v7
551 This selects support for the CP15 thread register.
552 It is defined to be available on some ARMv6 processors (including
553 all SMP capable ARMv6's) or later processors. User space may
554 assume directly accessing that register and always obtain the
555 expected value only on ARMv7 and above.
557 config NEEDS_SYSCALL_FOR_CMPXCHG
560 SMP on a pre-ARMv6 processor? Well OK then.
561 Forget about fast user space cmpxchg support.
562 It is just not possible.