2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
4 * Copyright (C) 2007 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
26 #define CACHE_LINE_SIZE 32
28 static void __iomem *l2x0_base;
29 static DEFINE_SPINLOCK(l2x0_lock);
30 static uint32_t l2x0_way_mask; /* Bitmask of active ways */
31 static uint32_t l2x0_size;
32 static u32 l2x0_cache_id;
33 static unsigned int l2x0_sets;
34 static unsigned int l2x0_ways;
36 static inline bool is_pl310_rev(int rev)
38 return (l2x0_cache_id &
39 (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) ==
40 (L2X0_CACHE_ID_PART_L310 | rev);
43 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
45 /* wait for cache operation by line or way to complete */
46 while (readl_relaxed(reg) & mask)
50 #ifdef CONFIG_CACHE_PL310
51 static inline void cache_wait(void __iomem *reg, unsigned long mask)
53 /* cache operations by line are atomic on PL310 */
56 #define cache_wait cache_wait_way
59 static inline void cache_sync(void)
61 void __iomem *base = l2x0_base;
63 #ifdef CONFIG_ARM_ERRATA_753970
64 /* write to an unmmapped register */
65 writel_relaxed(0, base + L2X0_DUMMY_REG);
67 writel_relaxed(0, base + L2X0_CACHE_SYNC);
69 cache_wait(base + L2X0_CACHE_SYNC, 1);
72 static inline void l2x0_clean_line(unsigned long addr)
74 void __iomem *base = l2x0_base;
75 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
76 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
79 static inline void l2x0_inv_line(unsigned long addr)
81 void __iomem *base = l2x0_base;
82 cache_wait(base + L2X0_INV_LINE_PA, 1);
83 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
86 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
88 #define debug_writel(val) outer_cache.set_debug(val)
90 static void l2x0_set_debug(unsigned long val)
92 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
95 /* Optimised out for non-errata case */
96 static inline void debug_writel(unsigned long val)
100 #define l2x0_set_debug NULL
103 #ifdef CONFIG_PL310_ERRATA_588369
104 static inline void l2x0_flush_line(unsigned long addr)
106 void __iomem *base = l2x0_base;
108 /* Clean by PA followed by Invalidate by PA */
109 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
110 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
111 cache_wait(base + L2X0_INV_LINE_PA, 1);
112 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
116 static inline void l2x0_flush_line(unsigned long addr)
118 void __iomem *base = l2x0_base;
119 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
120 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
124 static void l2x0_cache_sync(void)
128 spin_lock_irqsave(&l2x0_lock, flags);
130 spin_unlock_irqrestore(&l2x0_lock, flags);
133 #ifdef CONFIG_PL310_ERRATA_727915
134 static void l2x0_for_each_set_way(void __iomem *reg)
140 for (way = 0; way < l2x0_ways; way++) {
141 spin_lock_irqsave(&l2x0_lock, flags);
142 for (set = 0; set < l2x0_sets; set++)
143 writel_relaxed((way << 28) | (set << 5), reg);
145 spin_unlock_irqrestore(&l2x0_lock, flags);
150 static void __l2x0_flush_all(void)
153 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
154 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
159 static void l2x0_flush_all(void)
163 #ifdef CONFIG_PL310_ERRATA_727915
164 if (is_pl310_rev(REV_PL310_R2P0)) {
165 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX);
171 spin_lock_irqsave(&l2x0_lock, flags);
173 spin_unlock_irqrestore(&l2x0_lock, flags);
176 static void l2x0_clean_all(void)
180 #ifdef CONFIG_PL310_ERRATA_727915
181 if (is_pl310_rev(REV_PL310_R2P0)) {
182 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX);
188 spin_lock_irqsave(&l2x0_lock, flags);
190 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
191 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
194 spin_unlock_irqrestore(&l2x0_lock, flags);
197 static void l2x0_inv_all(void)
201 /* invalidate all ways */
202 spin_lock_irqsave(&l2x0_lock, flags);
203 /* Invalidating when L2 is enabled is a nono */
204 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
205 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
206 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
208 spin_unlock_irqrestore(&l2x0_lock, flags);
211 static void l2x0_inv_range(unsigned long start, unsigned long end)
213 void __iomem *base = l2x0_base;
216 spin_lock_irqsave(&l2x0_lock, flags);
217 if (start & (CACHE_LINE_SIZE - 1)) {
218 start &= ~(CACHE_LINE_SIZE - 1);
220 l2x0_flush_line(start);
222 start += CACHE_LINE_SIZE;
225 if (end & (CACHE_LINE_SIZE - 1)) {
226 end &= ~(CACHE_LINE_SIZE - 1);
228 l2x0_flush_line(end);
232 while (start < end) {
233 unsigned long blk_end = start + min(end - start, 4096UL);
235 while (start < blk_end) {
236 l2x0_inv_line(start);
237 start += CACHE_LINE_SIZE;
241 spin_unlock_irqrestore(&l2x0_lock, flags);
242 spin_lock_irqsave(&l2x0_lock, flags);
245 cache_wait(base + L2X0_INV_LINE_PA, 1);
247 spin_unlock_irqrestore(&l2x0_lock, flags);
250 static void l2x0_clean_range(unsigned long start, unsigned long end)
252 void __iomem *base = l2x0_base;
255 if ((end - start) >= l2x0_size) {
260 spin_lock_irqsave(&l2x0_lock, flags);
261 start &= ~(CACHE_LINE_SIZE - 1);
262 while (start < end) {
263 unsigned long blk_end = start + min(end - start, 4096UL);
265 while (start < blk_end) {
266 l2x0_clean_line(start);
267 start += CACHE_LINE_SIZE;
271 spin_unlock_irqrestore(&l2x0_lock, flags);
272 spin_lock_irqsave(&l2x0_lock, flags);
275 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
277 spin_unlock_irqrestore(&l2x0_lock, flags);
280 static void l2x0_flush_range(unsigned long start, unsigned long end)
282 void __iomem *base = l2x0_base;
285 if ((end - start) >= l2x0_size) {
290 spin_lock_irqsave(&l2x0_lock, flags);
291 start &= ~(CACHE_LINE_SIZE - 1);
292 while (start < end) {
293 unsigned long blk_end = start + min(end - start, 4096UL);
296 while (start < blk_end) {
297 l2x0_flush_line(start);
298 start += CACHE_LINE_SIZE;
303 spin_unlock_irqrestore(&l2x0_lock, flags);
304 spin_lock_irqsave(&l2x0_lock, flags);
307 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
309 spin_unlock_irqrestore(&l2x0_lock, flags);
312 static void l2x0_disable(void)
316 spin_lock_irqsave(&l2x0_lock, flags);
318 writel_relaxed(0, l2x0_base + L2X0_CTRL);
320 spin_unlock_irqrestore(&l2x0_lock, flags);
323 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
331 l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
332 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
337 /* Determine the number of ways */
338 switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) {
339 case L2X0_CACHE_ID_PART_L310:
346 case L2X0_CACHE_ID_PART_L210:
347 l2x0_ways = (aux >> 13) & 0xf;
351 /* Assume unknown chips have 8 ways */
353 type = "L2x0 series";
357 l2x0_way_mask = (1 << l2x0_ways) - 1;
360 * L2 cache Size = Way size * Number of ways
362 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
363 way_size = SZ_1K << (way_size + 3);
364 l2x0_size = l2x0_ways * way_size;
365 l2x0_sets = way_size / CACHE_LINE_SIZE;
368 * Check if l2x0 controller is already enabled.
369 * If you are booting from non-secure mode
370 * accessing the below registers will fault.
372 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
374 /* l2x0 controller is disabled */
375 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
380 writel_relaxed(1, l2x0_base + L2X0_CTRL);
383 outer_cache.inv_range = l2x0_inv_range;
384 outer_cache.clean_range = l2x0_clean_range;
385 outer_cache.flush_range = l2x0_flush_range;
386 outer_cache.sync = l2x0_cache_sync;
387 outer_cache.flush_all = l2x0_flush_all;
388 outer_cache.inv_all = l2x0_inv_all;
389 outer_cache.disable = l2x0_disable;
390 outer_cache.set_debug = l2x0_set_debug;
392 printk(KERN_INFO "%s cache controller enabled\n", type);
393 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
394 l2x0_ways, l2x0_cache_id, aux, l2x0_size);