2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/module.h>
14 #include <linux/gfp.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dma-contiguous.h>
21 #include <linux/highmem.h>
22 #include <linux/memblock.h>
23 #include <linux/slab.h>
24 #include <linux/iommu.h>
26 #include <linux/vmalloc.h>
27 #include <linux/sizes.h>
29 #include <asm/memory.h>
30 #include <asm/highmem.h>
31 #include <asm/cacheflush.h>
32 #include <asm/tlbflush.h>
33 #include <asm/mach/arch.h>
34 #include <asm/dma-iommu.h>
35 #include <asm/mach/map.h>
36 #include <asm/system_info.h>
37 #include <asm/dma-contiguous.h>
42 * The DMA API is built upon the notion of "buffer ownership". A buffer
43 * is either exclusively owned by the CPU (and therefore may be accessed
44 * by it) or exclusively owned by the DMA device. These helper functions
45 * represent the transitions between these two ownership states.
47 * Note, however, that on later ARMs, this notion does not work due to
48 * speculative prefetches. We model our approach on the assumption that
49 * the CPU does do speculative prefetches, which means we clean caches
50 * before transfers and delay cache invalidation until transfer completion.
53 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
54 size_t, enum dma_data_direction);
55 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
56 size_t, enum dma_data_direction);
59 * arm_dma_map_page - map a portion of a page for streaming DMA
60 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
61 * @page: page that buffer resides in
62 * @offset: offset into page for start of buffer
63 * @size: size of buffer to map
64 * @dir: DMA transfer direction
66 * Ensure that any data held in the cache is appropriately discarded
69 * The device owns this memory once this call has completed. The CPU
70 * can regain ownership by calling dma_unmap_page().
72 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
73 unsigned long offset, size_t size, enum dma_data_direction dir,
74 struct dma_attrs *attrs)
76 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
77 __dma_page_cpu_to_dev(page, offset, size, dir);
78 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
81 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
82 unsigned long offset, size_t size, enum dma_data_direction dir,
83 struct dma_attrs *attrs)
85 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
89 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
90 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
91 * @handle: DMA address of buffer
92 * @size: size of buffer (same as passed to dma_map_page)
93 * @dir: DMA transfer direction (same as passed to dma_map_page)
95 * Unmap a page streaming mode DMA translation. The handle and size
96 * must match what was provided in the previous dma_map_page() call.
97 * All other usages are undefined.
99 * After this call, reads by the CPU to the buffer are guaranteed to see
100 * whatever the device wrote there.
102 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
103 size_t size, enum dma_data_direction dir,
104 struct dma_attrs *attrs)
106 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
107 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
108 handle & ~PAGE_MASK, size, dir);
111 static void arm_dma_sync_single_for_cpu(struct device *dev,
112 dma_addr_t handle, size_t size, enum dma_data_direction dir)
114 unsigned int offset = handle & (PAGE_SIZE - 1);
115 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
116 __dma_page_dev_to_cpu(page, offset, size, dir);
119 static void arm_dma_sync_single_for_device(struct device *dev,
120 dma_addr_t handle, size_t size, enum dma_data_direction dir)
122 unsigned int offset = handle & (PAGE_SIZE - 1);
123 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
124 __dma_page_cpu_to_dev(page, offset, size, dir);
127 struct dma_map_ops arm_dma_ops = {
128 .alloc = arm_dma_alloc,
129 .free = arm_dma_free,
130 .mmap = arm_dma_mmap,
131 .get_sgtable = arm_dma_get_sgtable,
132 .map_page = arm_dma_map_page,
133 .unmap_page = arm_dma_unmap_page,
134 .map_sg = arm_dma_map_sg,
135 .unmap_sg = arm_dma_unmap_sg,
136 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
137 .sync_single_for_device = arm_dma_sync_single_for_device,
138 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
139 .sync_sg_for_device = arm_dma_sync_sg_for_device,
140 .set_dma_mask = arm_dma_set_mask,
142 EXPORT_SYMBOL(arm_dma_ops);
144 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
145 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
146 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
147 dma_addr_t handle, struct dma_attrs *attrs);
149 struct dma_map_ops arm_coherent_dma_ops = {
150 .alloc = arm_coherent_dma_alloc,
151 .free = arm_coherent_dma_free,
152 .mmap = arm_dma_mmap,
153 .get_sgtable = arm_dma_get_sgtable,
154 .map_page = arm_coherent_dma_map_page,
155 .map_sg = arm_dma_map_sg,
156 .set_dma_mask = arm_dma_set_mask,
158 EXPORT_SYMBOL(arm_coherent_dma_ops);
160 static u64 get_coherent_dma_mask(struct device *dev)
162 u64 mask = (u64)arm_dma_limit;
165 mask = dev->coherent_dma_mask;
168 * Sanity check the DMA mask - it must be non-zero, and
169 * must be able to be satisfied by a DMA allocation.
172 dev_warn(dev, "coherent DMA mask is unset\n");
176 if ((~mask) & (u64)arm_dma_limit) {
177 dev_warn(dev, "coherent DMA mask %#llx is smaller "
178 "than system GFP_DMA mask %#llx\n",
179 mask, (u64)arm_dma_limit);
187 static void __dma_clear_buffer(struct page *page, size_t size)
190 * Ensure that the allocated pages are zeroed, and that any data
191 * lurking in the kernel direct-mapped region is invalidated.
193 if (PageHighMem(page)) {
194 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
195 phys_addr_t end = base + size;
197 void *ptr = kmap_atomic(page);
198 memset(ptr, 0, PAGE_SIZE);
199 dmac_flush_range(ptr, ptr + PAGE_SIZE);
204 outer_flush_range(base, end);
206 void *ptr = page_address(page);
207 memset(ptr, 0, size);
208 dmac_flush_range(ptr, ptr + size);
209 outer_flush_range(__pa(ptr), __pa(ptr) + size);
214 * Allocate a DMA buffer for 'dev' of size 'size' using the
215 * specified gfp mask. Note that 'size' must be page aligned.
217 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
219 unsigned long order = get_order(size);
220 struct page *page, *p, *e;
222 page = alloc_pages(gfp, order);
227 * Now split the huge page and free the excess pages
229 split_page(page, order);
230 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
233 __dma_clear_buffer(page, size);
239 * Free a DMA buffer. 'size' must be page aligned.
241 static void __dma_free_buffer(struct page *page, size_t size)
243 struct page *e = page + (size >> PAGE_SHIFT);
252 #ifdef CONFIG_HUGETLB_PAGE
253 #warning ARM Coherent DMA allocator does not (yet) support huge TLB
256 static void *__alloc_from_contiguous(struct device *dev, size_t size,
257 pgprot_t prot, struct page **ret_page,
258 #ifdef CONFIG_ARCH_ROCKCHIP
259 struct dma_attrs *attrs,
263 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
264 pgprot_t prot, struct page **ret_page,
268 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
272 * DMA allocation can be mapped to user space, so lets
273 * set VM_USERMAP flags too.
275 return dma_common_contiguous_remap(page, size,
276 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
280 static void __dma_free_remap(void *cpu_addr, size_t size)
282 dma_common_free_remap(cpu_addr, size,
283 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
286 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
291 unsigned long *bitmap;
292 unsigned long nr_pages;
297 static struct dma_pool atomic_pool = {
298 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
301 static int __init early_coherent_pool(char *p)
303 atomic_pool.size = memparse(p, &p);
306 early_param("coherent_pool", early_coherent_pool);
308 void __init init_dma_coherent_pool_size(unsigned long size)
311 * Catch any attempt to set the pool size too late.
313 BUG_ON(atomic_pool.vaddr);
316 * Set architecture specific coherent pool size only if
317 * it has not been changed by kernel command line parameter.
319 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
320 atomic_pool.size = size;
324 * Initialise the coherent pool for atomic allocations.
326 static int __init atomic_pool_init(void)
328 struct dma_pool *pool = &atomic_pool;
329 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
330 gfp_t gfp = GFP_KERNEL | GFP_DMA;
331 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
332 unsigned long *bitmap;
336 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
338 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
342 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
346 if (IS_ENABLED(CONFIG_DMA_CMA))
347 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
348 #ifdef CONFIG_ARCH_ROCKCHIP
353 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
358 for (i = 0; i < nr_pages; i++)
361 spin_lock_init(&pool->lock);
364 pool->bitmap = bitmap;
365 pool->nr_pages = nr_pages;
366 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
367 (unsigned)pool->size / 1024);
375 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
376 (unsigned)pool->size / 1024);
380 * CMA is activated by core_initcall, so we must be called after it.
382 postcore_initcall(atomic_pool_init);
384 struct dma_contig_early_reserve {
389 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
391 static int dma_mmu_remap_num __initdata;
393 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
395 dma_mmu_remap[dma_mmu_remap_num].base = base;
396 dma_mmu_remap[dma_mmu_remap_num].size = size;
400 void __init dma_contiguous_remap(void)
403 for (i = 0; i < dma_mmu_remap_num; i++) {
404 phys_addr_t start = dma_mmu_remap[i].base;
405 phys_addr_t end = start + dma_mmu_remap[i].size;
409 if (end > arm_lowmem_limit)
410 end = arm_lowmem_limit;
414 map.pfn = __phys_to_pfn(start);
415 map.virtual = __phys_to_virt(start);
416 map.length = end - start;
417 map.type = MT_MEMORY_DMA_READY;
420 * Clear previous low-memory mapping
422 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
424 pmd_clear(pmd_off_k(addr));
426 iotable_init(&map, 1);
430 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
433 struct page *page = virt_to_page(addr);
434 pgprot_t prot = *(pgprot_t *)data;
436 set_pte_ext(pte, mk_pte(page, prot), 0);
440 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
442 unsigned long start = (unsigned long) page_address(page);
443 unsigned end = start + size;
445 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
447 flush_tlb_kernel_range(start, end);
450 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
451 pgprot_t prot, struct page **ret_page,
456 page = __dma_alloc_buffer(dev, size, gfp);
460 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
462 __dma_free_buffer(page, size);
470 static void *__alloc_from_pool(size_t size, struct page **ret_page)
472 struct dma_pool *pool = &atomic_pool;
473 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
477 unsigned long align_mask;
480 WARN(1, "coherent pool not initialised!\n");
485 * Align the region allocation - allocations from pool are rather
486 * small, so align them to their order in pages, minimum is a page
487 * size. This helps reduce fragmentation of the DMA space.
489 align_mask = (1 << get_order(size)) - 1;
491 spin_lock_irqsave(&pool->lock, flags);
492 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
493 0, count, align_mask);
494 if (pageno < pool->nr_pages) {
495 bitmap_set(pool->bitmap, pageno, count);
496 ptr = pool->vaddr + PAGE_SIZE * pageno;
497 *ret_page = pool->pages[pageno];
499 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
500 "Please increase it with coherent_pool= kernel parameter!\n",
501 (unsigned)pool->size / 1024);
503 spin_unlock_irqrestore(&pool->lock, flags);
508 static bool __in_atomic_pool(void *start, size_t size)
510 struct dma_pool *pool = &atomic_pool;
511 void *end = start + size;
512 void *pool_start = pool->vaddr;
513 void *pool_end = pool->vaddr + pool->size;
515 if (start < pool_start || start >= pool_end)
521 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
522 start, end - 1, pool_start, pool_end - 1);
527 static int __free_from_pool(void *start, size_t size)
529 struct dma_pool *pool = &atomic_pool;
530 unsigned long pageno, count;
533 if (!__in_atomic_pool(start, size))
536 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
537 count = size >> PAGE_SHIFT;
539 spin_lock_irqsave(&pool->lock, flags);
540 bitmap_clear(pool->bitmap, pageno, count);
541 spin_unlock_irqrestore(&pool->lock, flags);
546 static void *__alloc_from_contiguous(struct device *dev, size_t size,
547 pgprot_t prot, struct page **ret_page,
548 #ifdef CONFIG_ARCH_ROCKCHIP
549 struct dma_attrs *attrs,
553 unsigned long order = get_order(size);
554 size_t count = size >> PAGE_SHIFT;
558 page = dma_alloc_from_contiguous(dev, count, order);
562 __dma_clear_buffer(page, size);
564 #ifdef CONFIG_ARCH_ROCKCHIP
565 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
566 return (*ret_page=page);
569 if (PageHighMem(page)) {
570 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
572 dma_release_from_contiguous(dev, page, count);
576 __dma_remap(page, size, prot);
577 ptr = page_address(page);
583 #ifdef CONFIG_ARCH_ROCKCHIP
584 static void __free_from_contiguous(struct device *dev, struct page *page,
585 void *cpu_addr, size_t size,
586 struct dma_attrs *attrs)
588 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
589 if (PageHighMem(page))
590 __dma_free_remap(cpu_addr, size);
592 __dma_remap(page, size, pgprot_kernel);
594 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
597 static void __free_from_contiguous(struct device *dev, struct page *page,
598 void *cpu_addr, size_t size)
600 if (PageHighMem(page))
601 __dma_free_remap(cpu_addr, size);
603 __dma_remap(page, size, pgprot_kernel);
604 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
608 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
610 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
611 pgprot_writecombine(prot) :
612 pgprot_dmacoherent(prot);
618 #else /* !CONFIG_MMU */
622 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
623 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
624 #define __alloc_from_pool(size, ret_page) NULL
625 #ifdef CONFIG_ARCH_ROCKCHIP
626 #define __alloc_from_contiguous(dev, size, prot, ret, attrs, c) NULL
628 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
630 #define __free_from_pool(cpu_addr, size) 0
631 #ifdef CONFIG_ARCH_ROCKCHIP
632 #define __free_from_contiguous(dev, page, cpu_addr, size, attrs) do { } while (0)
634 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
636 #define __dma_free_remap(cpu_addr, size) do { } while (0)
638 #endif /* CONFIG_MMU */
640 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
641 struct page **ret_page)
644 page = __dma_alloc_buffer(dev, size, gfp);
649 return page_address(page);
654 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
655 #ifdef CONFIG_ARCH_ROCKCHIP
656 gfp_t gfp, pgprot_t prot, bool is_coherent,
657 struct dma_attrs *attrs, const void *caller)
659 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
662 u64 mask = get_coherent_dma_mask(dev);
663 struct page *page = NULL;
666 #ifdef CONFIG_DMA_API_DEBUG
667 u64 limit = (mask + 1) & ~mask;
668 if (limit && size >= limit) {
669 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
678 if (mask < 0xffffffffULL)
682 * Following is a work-around (a.k.a. hack) to prevent pages
683 * with __GFP_COMP being passed to split_page() which cannot
684 * handle them. The real problem is that this flag probably
685 * should be 0 on ARM as it is not supported on this
686 * platform; see CONFIG_HUGETLBFS.
688 gfp &= ~(__GFP_COMP);
690 *handle = DMA_ERROR_CODE;
691 size = PAGE_ALIGN(size);
693 if (is_coherent || nommu())
694 addr = __alloc_simple_buffer(dev, size, gfp, &page);
695 else if (!(gfp & __GFP_WAIT))
696 addr = __alloc_from_pool(size, &page);
697 else if (!IS_ENABLED(CONFIG_DMA_CMA))
698 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
700 #ifdef CONFIG_ARCH_ROCKCHIP
701 addr = __alloc_from_contiguous(dev, size, prot, &page, attrs, caller);
703 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
707 *handle = pfn_to_dma(dev, page_to_pfn(page));
713 * Allocate DMA-coherent memory space and return both the kernel remapped
714 * virtual and bus address for that space.
716 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
717 gfp_t gfp, struct dma_attrs *attrs)
719 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
722 if (dma_alloc_from_coherent(dev, size, handle, &memory))
725 return __dma_alloc(dev, size, handle, gfp, prot, false,
726 #ifdef CONFIG_ARCH_ROCKCHIP
729 __builtin_return_address(0));
732 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
733 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
735 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
738 if (dma_alloc_from_coherent(dev, size, handle, &memory))
741 return __dma_alloc(dev, size, handle, gfp, prot, true,
742 #ifdef CONFIG_ARCH_ROCKCHIP
745 __builtin_return_address(0));
749 * Create userspace mapping for the DMA-coherent memory.
751 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
752 void *cpu_addr, dma_addr_t dma_addr, size_t size,
753 struct dma_attrs *attrs)
757 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
758 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
759 unsigned long pfn = dma_to_pfn(dev, dma_addr);
760 unsigned long off = vma->vm_pgoff;
762 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
764 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
767 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
768 ret = remap_pfn_range(vma, vma->vm_start,
770 vma->vm_end - vma->vm_start,
773 #endif /* CONFIG_MMU */
779 * Free a buffer as defined by the above mapping.
781 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
782 dma_addr_t handle, struct dma_attrs *attrs,
785 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
787 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
790 size = PAGE_ALIGN(size);
792 if (is_coherent || nommu()) {
793 __dma_free_buffer(page, size);
794 } else if (__free_from_pool(cpu_addr, size)) {
796 } else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
797 __dma_free_remap(cpu_addr, size);
798 __dma_free_buffer(page, size);
801 * Non-atomic allocations cannot be freed with IRQs disabled
803 WARN_ON(irqs_disabled());
804 #ifdef CONFIG_ARCH_ROCKCHIP
805 __free_from_contiguous(dev, page, cpu_addr, size, attrs);
807 __free_from_contiguous(dev, page, cpu_addr, size);
812 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
813 dma_addr_t handle, struct dma_attrs *attrs)
815 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
818 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
819 dma_addr_t handle, struct dma_attrs *attrs)
821 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
824 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
825 void *cpu_addr, dma_addr_t handle, size_t size,
826 struct dma_attrs *attrs)
828 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
831 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
835 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
839 static void dma_cache_maint_page(struct page *page, unsigned long offset,
840 size_t size, enum dma_data_direction dir,
841 void (*op)(const void *, size_t, int))
846 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
850 * A single sg entry may refer to multiple physically contiguous
851 * pages. But we still need to process highmem pages individually.
852 * If highmem is not configured then the bulk of this loop gets
859 page = pfn_to_page(pfn);
861 if (PageHighMem(page)) {
862 if (len + offset > PAGE_SIZE)
863 len = PAGE_SIZE - offset;
865 if (cache_is_vipt_nonaliasing()) {
866 vaddr = kmap_atomic(page);
867 op(vaddr + offset, len, dir);
868 kunmap_atomic(vaddr);
870 vaddr = kmap_high_get(page);
872 op(vaddr + offset, len, dir);
877 vaddr = page_address(page) + offset;
887 * Make an area consistent for devices.
888 * Note: Drivers should NOT use this function directly, as it will break
889 * platforms with CONFIG_DMABOUNCE.
890 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
892 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
893 size_t size, enum dma_data_direction dir)
897 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
899 paddr = page_to_phys(page) + off;
900 if (dir == DMA_FROM_DEVICE) {
901 outer_inv_range(paddr, paddr + size);
903 outer_clean_range(paddr, paddr + size);
905 /* FIXME: non-speculating: flush on bidirectional mappings? */
908 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
909 size_t size, enum dma_data_direction dir)
911 unsigned long paddr = page_to_phys(page) + off;
913 /* FIXME: non-speculating: not required */
914 /* don't bother invalidating if DMA to device */
915 if (dir != DMA_TO_DEVICE)
916 outer_inv_range(paddr, paddr + size);
918 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
921 * Mark the D-cache clean for this page to avoid extra flushing.
923 if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
924 set_bit(PG_dcache_clean, &page->flags);
928 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
929 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
930 * @sg: list of buffers
931 * @nents: number of buffers to map
932 * @dir: DMA transfer direction
934 * Map a set of buffers described by scatterlist in streaming mode for DMA.
935 * This is the scatter-gather version of the dma_map_single interface.
936 * Here the scatter gather list elements are each tagged with the
937 * appropriate dma address and length. They are obtained via
938 * sg_dma_{address,length}.
940 * Device ownership issues as mentioned for dma_map_single are the same
943 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
944 enum dma_data_direction dir, struct dma_attrs *attrs)
946 struct dma_map_ops *ops = get_dma_ops(dev);
947 struct scatterlist *s;
950 for_each_sg(sg, s, nents, i) {
951 #ifdef CONFIG_NEED_SG_DMA_LENGTH
952 s->dma_length = s->length;
954 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
955 s->length, dir, attrs);
956 if (dma_mapping_error(dev, s->dma_address))
962 for_each_sg(sg, s, i, j)
963 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
968 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
969 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
970 * @sg: list of buffers
971 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
972 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
974 * Unmap a set of streaming mode DMA translations. Again, CPU access
975 * rules concerning calls here are the same as for dma_unmap_single().
977 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
978 enum dma_data_direction dir, struct dma_attrs *attrs)
980 struct dma_map_ops *ops = get_dma_ops(dev);
981 struct scatterlist *s;
985 for_each_sg(sg, s, nents, i)
986 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
990 * arm_dma_sync_sg_for_cpu
991 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
992 * @sg: list of buffers
993 * @nents: number of buffers to map (returned from dma_map_sg)
994 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
996 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
997 int nents, enum dma_data_direction dir)
999 struct dma_map_ops *ops = get_dma_ops(dev);
1000 struct scatterlist *s;
1003 for_each_sg(sg, s, nents, i)
1004 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1009 * arm_dma_sync_sg_for_device
1010 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1011 * @sg: list of buffers
1012 * @nents: number of buffers to map (returned from dma_map_sg)
1013 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1015 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1016 int nents, enum dma_data_direction dir)
1018 struct dma_map_ops *ops = get_dma_ops(dev);
1019 struct scatterlist *s;
1022 for_each_sg(sg, s, nents, i)
1023 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1028 * Return whether the given device DMA address mask can be supported
1029 * properly. For example, if your device can only drive the low 24-bits
1030 * during bus mastering, then you would pass 0x00ffffff as the mask
1033 int dma_supported(struct device *dev, u64 mask)
1035 if (mask < (u64)arm_dma_limit)
1039 EXPORT_SYMBOL(dma_supported);
1041 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1043 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1046 *dev->dma_mask = dma_mask;
1051 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1053 static int __init dma_debug_do_init(void)
1055 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1058 fs_initcall(dma_debug_do_init);
1060 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1064 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1067 unsigned int order = get_order(size);
1068 unsigned int align = 0;
1069 unsigned int count, start;
1070 unsigned long flags;
1072 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1073 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1075 count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
1076 (1 << mapping->order) - 1) >> mapping->order;
1078 if (order > mapping->order)
1079 align = (1 << (order - mapping->order)) - 1;
1081 spin_lock_irqsave(&mapping->lock, flags);
1082 start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
1084 if (start > mapping->bits) {
1085 spin_unlock_irqrestore(&mapping->lock, flags);
1086 return DMA_ERROR_CODE;
1089 bitmap_set(mapping->bitmap, start, count);
1090 spin_unlock_irqrestore(&mapping->lock, flags);
1092 return mapping->base + (start << (mapping->order + PAGE_SHIFT));
1095 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1096 dma_addr_t addr, size_t size)
1098 unsigned int start = (addr - mapping->base) >>
1099 (mapping->order + PAGE_SHIFT);
1100 unsigned int count = ((size >> PAGE_SHIFT) +
1101 (1 << mapping->order) - 1) >> mapping->order;
1102 unsigned long flags;
1104 spin_lock_irqsave(&mapping->lock, flags);
1105 bitmap_clear(mapping->bitmap, start, count);
1106 spin_unlock_irqrestore(&mapping->lock, flags);
1109 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1110 gfp_t gfp, struct dma_attrs *attrs)
1112 struct page **pages;
1113 int count = size >> PAGE_SHIFT;
1114 int array_size = count * sizeof(struct page *);
1117 if (array_size <= PAGE_SIZE)
1118 pages = kzalloc(array_size, gfp);
1120 pages = vzalloc(array_size);
1124 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1126 unsigned long order = get_order(size);
1129 page = dma_alloc_from_contiguous(dev, count, order);
1133 __dma_clear_buffer(page, size);
1135 for (i = 0; i < count; i++)
1136 pages[i] = page + i;
1142 * IOMMU can map any pages, so himem can also be used here
1144 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1147 int j, order = __fls(count);
1149 pages[i] = alloc_pages(gfp, order);
1150 while (!pages[i] && order)
1151 pages[i] = alloc_pages(gfp, --order);
1156 split_page(pages[i], order);
1159 pages[i + j] = pages[i] + j;
1162 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1164 count -= 1 << order;
1171 __free_pages(pages[i], 0);
1172 if (array_size <= PAGE_SIZE)
1179 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1180 size_t size, struct dma_attrs *attrs)
1182 int count = size >> PAGE_SHIFT;
1183 int array_size = count * sizeof(struct page *);
1186 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1187 dma_release_from_contiguous(dev, pages[0], count);
1189 for (i = 0; i < count; i++)
1191 __free_pages(pages[i], 0);
1194 if (array_size <= PAGE_SIZE)
1202 * Create a CPU mapping for a specified pages
1205 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1208 return dma_common_pages_remap(pages, size,
1209 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1214 * Create a mapping in device IO address space for specified pages
1217 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1219 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1220 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1221 dma_addr_t dma_addr, iova;
1222 int i, ret = DMA_ERROR_CODE;
1224 dma_addr = __alloc_iova(mapping, size);
1225 if (dma_addr == DMA_ERROR_CODE)
1229 for (i = 0; i < count; ) {
1230 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1231 phys_addr_t phys = page_to_phys(pages[i]);
1232 unsigned int len, j;
1234 for (j = i + 1; j < count; j++, next_pfn++)
1235 if (page_to_pfn(pages[j]) != next_pfn)
1238 len = (j - i) << PAGE_SHIFT;
1239 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1247 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1248 __free_iova(mapping, dma_addr, size);
1249 return DMA_ERROR_CODE;
1252 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1254 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1257 * add optional in-page offset from iova to size and align
1258 * result to page size
1260 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1263 iommu_unmap(mapping->domain, iova, size);
1264 __free_iova(mapping, iova, size);
1268 static struct page **__atomic_get_pages(void *addr)
1270 struct dma_pool *pool = &atomic_pool;
1271 struct page **pages = pool->pages;
1272 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1274 return pages + offs;
1277 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1279 struct vm_struct *area;
1281 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1282 return __atomic_get_pages(cpu_addr);
1284 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1287 area = find_vm_area(cpu_addr);
1288 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1293 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1299 addr = __alloc_from_pool(size, &page);
1303 *handle = __iommu_create_mapping(dev, &page, size);
1304 if (*handle == DMA_ERROR_CODE)
1310 __free_from_pool(addr, size);
1314 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1315 dma_addr_t handle, size_t size)
1317 __iommu_remove_mapping(dev, handle, size);
1318 __free_from_pool(cpu_addr, size);
1321 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1322 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1324 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
1325 struct page **pages;
1328 *handle = DMA_ERROR_CODE;
1329 size = PAGE_ALIGN(size);
1331 if (!(gfp & __GFP_WAIT))
1332 return __iommu_alloc_atomic(dev, size, handle);
1334 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1338 *handle = __iommu_create_mapping(dev, pages, size);
1339 if (*handle == DMA_ERROR_CODE)
1342 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1345 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1346 __builtin_return_address(0));
1353 __iommu_remove_mapping(dev, *handle, size);
1355 __iommu_free_buffer(dev, pages, size, attrs);
1359 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1360 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1361 struct dma_attrs *attrs)
1363 unsigned long uaddr = vma->vm_start;
1364 unsigned long usize = vma->vm_end - vma->vm_start;
1365 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1367 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1373 int ret = vm_insert_page(vma, uaddr, *pages++);
1375 pr_err("Remapping memory failed: %d\n", ret);
1380 } while (usize > 0);
1386 * free a page as defined by the above mapping.
1387 * Must not be called with IRQs disabled.
1389 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1390 dma_addr_t handle, struct dma_attrs *attrs)
1392 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1393 size = PAGE_ALIGN(size);
1396 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1400 if (__in_atomic_pool(cpu_addr, size)) {
1401 __iommu_free_atomic(dev, cpu_addr, handle, size);
1405 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1406 dma_common_free_remap(cpu_addr, size,
1407 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1410 __iommu_remove_mapping(dev, handle, size);
1411 __iommu_free_buffer(dev, pages, size, attrs);
1414 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1415 void *cpu_addr, dma_addr_t dma_addr,
1416 size_t size, struct dma_attrs *attrs)
1418 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1419 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1424 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1429 * Map a part of the scatter-gather list into contiguous io address space
1431 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1432 size_t size, dma_addr_t *handle,
1433 enum dma_data_direction dir, struct dma_attrs *attrs,
1436 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1437 dma_addr_t iova, iova_base;
1440 struct scatterlist *s;
1442 size = PAGE_ALIGN(size);
1443 *handle = DMA_ERROR_CODE;
1445 iova_base = iova = __alloc_iova(mapping, size);
1446 if (iova == DMA_ERROR_CODE)
1449 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1450 phys_addr_t phys = page_to_phys(sg_page(s));
1451 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1454 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1455 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1457 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1460 count += len >> PAGE_SHIFT;
1463 *handle = iova_base;
1467 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1468 __free_iova(mapping, iova_base, size);
1472 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1473 enum dma_data_direction dir, struct dma_attrs *attrs,
1476 struct scatterlist *s = sg, *dma = sg, *start = sg;
1478 unsigned int offset = s->offset;
1479 unsigned int size = s->offset + s->length;
1480 unsigned int max = dma_get_max_seg_size(dev);
1482 for (i = 1; i < nents; i++) {
1485 s->dma_address = DMA_ERROR_CODE;
1488 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1489 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1490 dir, attrs, is_coherent) < 0)
1493 dma->dma_address += offset;
1494 dma->dma_length = size - offset;
1496 size = offset = s->offset;
1503 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1507 dma->dma_address += offset;
1508 dma->dma_length = size - offset;
1513 for_each_sg(sg, s, count, i)
1514 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1519 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1520 * @dev: valid struct device pointer
1521 * @sg: list of buffers
1522 * @nents: number of buffers to map
1523 * @dir: DMA transfer direction
1525 * Map a set of i/o coherent buffers described by scatterlist in streaming
1526 * mode for DMA. The scatter gather list elements are merged together (if
1527 * possible) and tagged with the appropriate dma address and length. They are
1528 * obtained via sg_dma_{address,length}.
1530 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1531 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1533 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1537 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1538 * @dev: valid struct device pointer
1539 * @sg: list of buffers
1540 * @nents: number of buffers to map
1541 * @dir: DMA transfer direction
1543 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1544 * The scatter gather list elements are merged together (if possible) and
1545 * tagged with the appropriate dma address and length. They are obtained via
1546 * sg_dma_{address,length}.
1548 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1549 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1551 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1554 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1555 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1558 struct scatterlist *s;
1561 for_each_sg(sg, s, nents, i) {
1563 __iommu_remove_mapping(dev, sg_dma_address(s),
1566 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1567 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1573 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1574 * @dev: valid struct device pointer
1575 * @sg: list of buffers
1576 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1577 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1579 * Unmap a set of streaming mode DMA translations. Again, CPU access
1580 * rules concerning calls here are the same as for dma_unmap_single().
1582 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1583 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1585 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1589 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1590 * @dev: valid struct device pointer
1591 * @sg: list of buffers
1592 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1593 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1595 * Unmap a set of streaming mode DMA translations. Again, CPU access
1596 * rules concerning calls here are the same as for dma_unmap_single().
1598 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1599 enum dma_data_direction dir, struct dma_attrs *attrs)
1601 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1605 * arm_iommu_sync_sg_for_cpu
1606 * @dev: valid struct device pointer
1607 * @sg: list of buffers
1608 * @nents: number of buffers to map (returned from dma_map_sg)
1609 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1611 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1612 int nents, enum dma_data_direction dir)
1614 struct scatterlist *s;
1617 for_each_sg(sg, s, nents, i)
1618 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1623 * arm_iommu_sync_sg_for_device
1624 * @dev: valid struct device pointer
1625 * @sg: list of buffers
1626 * @nents: number of buffers to map (returned from dma_map_sg)
1627 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1629 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1630 int nents, enum dma_data_direction dir)
1632 struct scatterlist *s;
1635 for_each_sg(sg, s, nents, i)
1636 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1641 * arm_coherent_iommu_map_page
1642 * @dev: valid struct device pointer
1643 * @page: page that buffer resides in
1644 * @offset: offset into page for start of buffer
1645 * @size: size of buffer to map
1646 * @dir: DMA transfer direction
1648 * Coherent IOMMU aware version of arm_dma_map_page()
1650 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1651 unsigned long offset, size_t size, enum dma_data_direction dir,
1652 struct dma_attrs *attrs)
1654 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1655 dma_addr_t dma_addr;
1656 int ret, len = PAGE_ALIGN(size + offset);
1658 dma_addr = __alloc_iova(mapping, len);
1659 if (dma_addr == DMA_ERROR_CODE)
1662 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
1666 return dma_addr + offset;
1668 __free_iova(mapping, dma_addr, len);
1669 return DMA_ERROR_CODE;
1673 * arm_iommu_map_page
1674 * @dev: valid struct device pointer
1675 * @page: page that buffer resides in
1676 * @offset: offset into page for start of buffer
1677 * @size: size of buffer to map
1678 * @dir: DMA transfer direction
1680 * IOMMU aware version of arm_dma_map_page()
1682 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1683 unsigned long offset, size_t size, enum dma_data_direction dir,
1684 struct dma_attrs *attrs)
1686 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1687 __dma_page_cpu_to_dev(page, offset, size, dir);
1689 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1693 * arm_coherent_iommu_unmap_page
1694 * @dev: valid struct device pointer
1695 * @handle: DMA address of buffer
1696 * @size: size of buffer (same as passed to dma_map_page)
1697 * @dir: DMA transfer direction (same as passed to dma_map_page)
1699 * Coherent IOMMU aware version of arm_dma_unmap_page()
1701 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1702 size_t size, enum dma_data_direction dir,
1703 struct dma_attrs *attrs)
1705 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1706 dma_addr_t iova = handle & PAGE_MASK;
1707 int offset = handle & ~PAGE_MASK;
1708 int len = PAGE_ALIGN(size + offset);
1713 iommu_unmap(mapping->domain, iova, len);
1714 __free_iova(mapping, iova, len);
1718 * arm_iommu_unmap_page
1719 * @dev: valid struct device pointer
1720 * @handle: DMA address of buffer
1721 * @size: size of buffer (same as passed to dma_map_page)
1722 * @dir: DMA transfer direction (same as passed to dma_map_page)
1724 * IOMMU aware version of arm_dma_unmap_page()
1726 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1727 size_t size, enum dma_data_direction dir,
1728 struct dma_attrs *attrs)
1730 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1731 dma_addr_t iova = handle & PAGE_MASK;
1732 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1733 int offset = handle & ~PAGE_MASK;
1734 int len = PAGE_ALIGN(size + offset);
1739 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1740 __dma_page_dev_to_cpu(page, offset, size, dir);
1742 iommu_unmap(mapping->domain, iova, len);
1743 __free_iova(mapping, iova, len);
1746 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1747 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1749 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1750 dma_addr_t iova = handle & PAGE_MASK;
1751 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1752 unsigned int offset = handle & ~PAGE_MASK;
1757 __dma_page_dev_to_cpu(page, offset, size, dir);
1760 static void arm_iommu_sync_single_for_device(struct device *dev,
1761 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1763 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1764 dma_addr_t iova = handle & PAGE_MASK;
1765 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1766 unsigned int offset = handle & ~PAGE_MASK;
1771 __dma_page_cpu_to_dev(page, offset, size, dir);
1774 struct dma_map_ops iommu_ops = {
1775 .alloc = arm_iommu_alloc_attrs,
1776 .free = arm_iommu_free_attrs,
1777 .mmap = arm_iommu_mmap_attrs,
1778 .get_sgtable = arm_iommu_get_sgtable,
1780 .map_page = arm_iommu_map_page,
1781 .unmap_page = arm_iommu_unmap_page,
1782 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1783 .sync_single_for_device = arm_iommu_sync_single_for_device,
1785 .map_sg = arm_iommu_map_sg,
1786 .unmap_sg = arm_iommu_unmap_sg,
1787 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1788 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1790 .set_dma_mask = arm_dma_set_mask,
1793 struct dma_map_ops iommu_coherent_ops = {
1794 .alloc = arm_iommu_alloc_attrs,
1795 .free = arm_iommu_free_attrs,
1796 .mmap = arm_iommu_mmap_attrs,
1797 .get_sgtable = arm_iommu_get_sgtable,
1799 .map_page = arm_coherent_iommu_map_page,
1800 .unmap_page = arm_coherent_iommu_unmap_page,
1802 .map_sg = arm_coherent_iommu_map_sg,
1803 .unmap_sg = arm_coherent_iommu_unmap_sg,
1805 .set_dma_mask = arm_dma_set_mask,
1809 * arm_iommu_create_mapping
1810 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1811 * @base: start address of the valid IO address space
1812 * @size: size of the valid IO address space
1813 * @order: accuracy of the IO addresses allocations
1815 * Creates a mapping structure which holds information about used/unused
1816 * IO address ranges, which is required to perform memory allocation and
1817 * mapping with IOMMU aware functions.
1819 * The client device need to be attached to the mapping with
1820 * arm_iommu_attach_device function.
1822 struct dma_iommu_mapping *
1823 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
1826 unsigned int count = size >> (PAGE_SHIFT + order);
1827 unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
1828 struct dma_iommu_mapping *mapping;
1832 return ERR_PTR(-EINVAL);
1834 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1838 mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1839 if (!mapping->bitmap)
1842 mapping->base = base;
1843 mapping->bits = BITS_PER_BYTE * bitmap_size;
1844 mapping->order = order;
1845 spin_lock_init(&mapping->lock);
1847 mapping->domain = iommu_domain_alloc(bus);
1848 if (!mapping->domain)
1851 kref_init(&mapping->kref);
1854 kfree(mapping->bitmap);
1858 return ERR_PTR(err);
1860 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1862 static void release_iommu_mapping(struct kref *kref)
1864 struct dma_iommu_mapping *mapping =
1865 container_of(kref, struct dma_iommu_mapping, kref);
1867 iommu_domain_free(mapping->domain);
1868 kfree(mapping->bitmap);
1872 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1875 kref_put(&mapping->kref, release_iommu_mapping);
1877 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1880 * arm_iommu_attach_device
1881 * @dev: valid struct device pointer
1882 * @mapping: io address space mapping structure (returned from
1883 * arm_iommu_create_mapping)
1885 * Attaches specified io address space mapping to the provided device,
1886 * this replaces the dma operations (dma_map_ops pointer) with the
1887 * IOMMU aware version. More than one client might be attached to
1888 * the same io address space mapping.
1890 int arm_iommu_attach_device(struct device *dev,
1891 struct dma_iommu_mapping *mapping)
1895 err = iommu_attach_device(mapping->domain, dev);
1899 kref_get(&mapping->kref);
1900 dev->archdata.mapping = mapping;
1901 set_dma_ops(dev, &iommu_ops);
1903 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
1906 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
1909 * arm_iommu_detach_device
1910 * @dev: valid struct device pointer
1912 * Detaches the provided device from a previously attached map.
1913 * This voids the dma operations (dma_map_ops pointer)
1915 void arm_iommu_detach_device(struct device *dev)
1917 struct dma_iommu_mapping *mapping;
1919 mapping = to_dma_iommu_mapping(dev);
1921 dev_warn(dev, "Not attached\n");
1925 iommu_detach_device(mapping->domain, dev);
1926 kref_put(&mapping->kref, release_iommu_mapping);
1928 set_dma_ops(dev, NULL);
1930 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
1932 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);