2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/genalloc.h>
16 #include <linux/gfp.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include <linux/init.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-contiguous.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 #include <linux/iommu.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sizes.h>
30 #include <linux/cma.h>
32 #include <asm/memory.h>
33 #include <asm/highmem.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mach/arch.h>
37 #include <asm/dma-iommu.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_info.h>
40 #include <asm/dma-contiguous.h>
45 * The DMA API is built upon the notion of "buffer ownership". A buffer
46 * is either exclusively owned by the CPU (and therefore may be accessed
47 * by it) or exclusively owned by the DMA device. These helper functions
48 * represent the transitions between these two ownership states.
50 * Note, however, that on later ARMs, this notion does not work due to
51 * speculative prefetches. We model our approach on the assumption that
52 * the CPU does do speculative prefetches, which means we clean caches
53 * before transfers and delay cache invalidation until transfer completion.
56 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
57 size_t, enum dma_data_direction);
58 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
59 size_t, enum dma_data_direction);
62 * arm_dma_map_page - map a portion of a page for streaming DMA
63 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
64 * @page: page that buffer resides in
65 * @offset: offset into page for start of buffer
66 * @size: size of buffer to map
67 * @dir: DMA transfer direction
69 * Ensure that any data held in the cache is appropriately discarded
72 * The device owns this memory once this call has completed. The CPU
73 * can regain ownership by calling dma_unmap_page().
75 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
76 unsigned long offset, size_t size, enum dma_data_direction dir,
77 struct dma_attrs *attrs)
79 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
80 __dma_page_cpu_to_dev(page, offset, size, dir);
81 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
84 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
85 unsigned long offset, size_t size, enum dma_data_direction dir,
86 struct dma_attrs *attrs)
88 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
92 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
93 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
94 * @handle: DMA address of buffer
95 * @size: size of buffer (same as passed to dma_map_page)
96 * @dir: DMA transfer direction (same as passed to dma_map_page)
98 * Unmap a page streaming mode DMA translation. The handle and size
99 * must match what was provided in the previous dma_map_page() call.
100 * All other usages are undefined.
102 * After this call, reads by the CPU to the buffer are guaranteed to see
103 * whatever the device wrote there.
105 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
106 size_t size, enum dma_data_direction dir,
107 struct dma_attrs *attrs)
109 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
110 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
111 handle & ~PAGE_MASK, size, dir);
114 static void arm_dma_sync_single_for_cpu(struct device *dev,
115 dma_addr_t handle, size_t size, enum dma_data_direction dir)
117 unsigned int offset = handle & (PAGE_SIZE - 1);
118 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
119 __dma_page_dev_to_cpu(page, offset, size, dir);
122 static void arm_dma_sync_single_for_device(struct device *dev,
123 dma_addr_t handle, size_t size, enum dma_data_direction dir)
125 unsigned int offset = handle & (PAGE_SIZE - 1);
126 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
127 __dma_page_cpu_to_dev(page, offset, size, dir);
130 struct dma_map_ops arm_dma_ops = {
131 .alloc = arm_dma_alloc,
132 .free = arm_dma_free,
133 .mmap = arm_dma_mmap,
134 .get_sgtable = arm_dma_get_sgtable,
135 .map_page = arm_dma_map_page,
136 .unmap_page = arm_dma_unmap_page,
137 .map_sg = arm_dma_map_sg,
138 .unmap_sg = arm_dma_unmap_sg,
139 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
140 .sync_single_for_device = arm_dma_sync_single_for_device,
141 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
142 .sync_sg_for_device = arm_dma_sync_sg_for_device,
143 .set_dma_mask = arm_dma_set_mask,
145 EXPORT_SYMBOL(arm_dma_ops);
147 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
148 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
149 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
150 dma_addr_t handle, struct dma_attrs *attrs);
152 struct dma_map_ops arm_coherent_dma_ops = {
153 .alloc = arm_coherent_dma_alloc,
154 .free = arm_coherent_dma_free,
155 .mmap = arm_dma_mmap,
156 .get_sgtable = arm_dma_get_sgtable,
157 .map_page = arm_coherent_dma_map_page,
158 .map_sg = arm_dma_map_sg,
159 .set_dma_mask = arm_dma_set_mask,
161 EXPORT_SYMBOL(arm_coherent_dma_ops);
163 static int __dma_supported(struct device *dev, u64 mask, bool warn)
165 unsigned long max_dma_pfn;
168 * If the mask allows for more memory than we can address,
169 * and we actually have that much memory, then we must
170 * indicate that DMA to this device is not supported.
172 if (sizeof(mask) != sizeof(dma_addr_t) &&
173 mask > (dma_addr_t)~0 &&
174 dma_to_pfn(dev, ~0) < max_pfn - 1) {
176 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
178 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
183 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
186 * Translate the device's DMA mask to a PFN limit. This
187 * PFN number includes the page which we can DMA to.
189 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
191 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
193 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
201 static u64 get_coherent_dma_mask(struct device *dev)
203 u64 mask = (u64)DMA_BIT_MASK(32);
206 mask = dev->coherent_dma_mask;
209 * Sanity check the DMA mask - it must be non-zero, and
210 * must be able to be satisfied by a DMA allocation.
213 dev_warn(dev, "coherent DMA mask is unset\n");
217 if (!__dma_supported(dev, mask, true))
224 static void __dma_clear_buffer(struct page *page, size_t size)
227 * Ensure that the allocated pages are zeroed, and that any data
228 * lurking in the kernel direct-mapped region is invalidated.
230 if (PageHighMem(page)) {
231 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
232 phys_addr_t end = base + size;
234 void *ptr = kmap_atomic(page);
235 memset(ptr, 0, PAGE_SIZE);
236 dmac_flush_range(ptr, ptr + PAGE_SIZE);
241 outer_flush_range(base, end);
243 void *ptr = page_address(page);
244 memset(ptr, 0, size);
245 dmac_flush_range(ptr, ptr + size);
246 outer_flush_range(__pa(ptr), __pa(ptr) + size);
251 * Allocate a DMA buffer for 'dev' of size 'size' using the
252 * specified gfp mask. Note that 'size' must be page aligned.
254 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
256 unsigned long order = get_order(size);
257 struct page *page, *p, *e;
259 page = alloc_pages(gfp, order);
264 * Now split the huge page and free the excess pages
266 split_page(page, order);
267 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
270 __dma_clear_buffer(page, size);
276 * Free a DMA buffer. 'size' must be page aligned.
278 static void __dma_free_buffer(struct page *page, size_t size)
280 struct page *e = page + (size >> PAGE_SHIFT);
290 static void *__alloc_from_contiguous(struct device *dev, size_t size,
291 pgprot_t prot, struct page **ret_page,
292 const void *caller, bool want_vaddr);
294 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
295 pgprot_t prot, struct page **ret_page,
296 const void *caller, bool want_vaddr);
299 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
303 * DMA allocation can be mapped to user space, so lets
304 * set VM_USERMAP flags too.
306 return dma_common_contiguous_remap(page, size,
307 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
311 static void __dma_free_remap(void *cpu_addr, size_t size)
313 dma_common_free_remap(cpu_addr, size,
314 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
317 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
318 static struct gen_pool *atomic_pool;
320 static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
322 static int __init early_coherent_pool(char *p)
324 atomic_pool_size = memparse(p, &p);
327 early_param("coherent_pool", early_coherent_pool);
329 void __init init_dma_coherent_pool_size(unsigned long size)
332 * Catch any attempt to set the pool size too late.
337 * Set architecture specific coherent pool size only if
338 * it has not been changed by kernel command line parameter.
340 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
341 atomic_pool_size = size;
345 * Initialise the coherent pool for atomic allocations.
347 static int __init atomic_pool_init(void)
349 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
350 gfp_t gfp = GFP_KERNEL | GFP_DMA;
354 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
358 if (dev_get_cma_area(NULL))
359 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
360 &page, atomic_pool_init, true);
362 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
363 &page, atomic_pool_init, true);
367 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
369 atomic_pool_size, -1);
371 goto destroy_genpool;
373 gen_pool_set_algo(atomic_pool,
374 gen_pool_first_fit_order_align,
376 pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n",
377 atomic_pool_size / 1024);
382 gen_pool_destroy(atomic_pool);
385 pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n",
386 atomic_pool_size / 1024);
390 * CMA is activated by core_initcall, so we must be called after it.
392 postcore_initcall(atomic_pool_init);
394 struct dma_contig_early_reserve {
399 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
401 static int dma_mmu_remap_num __initdata;
403 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
405 dma_mmu_remap[dma_mmu_remap_num].base = base;
406 dma_mmu_remap[dma_mmu_remap_num].size = size;
410 void __init dma_contiguous_remap(void)
413 for (i = 0; i < dma_mmu_remap_num; i++) {
414 phys_addr_t start = dma_mmu_remap[i].base;
415 phys_addr_t end = start + dma_mmu_remap[i].size;
419 if (end > arm_lowmem_limit)
420 end = arm_lowmem_limit;
424 map.pfn = __phys_to_pfn(start);
425 map.virtual = __phys_to_virt(start);
426 map.length = end - start;
427 map.type = MT_MEMORY_DMA_READY;
430 * Clear previous low-memory mapping to ensure that the
431 * TLB does not see any conflicting entries, then flush
432 * the TLB of the old entries before creating new mappings.
434 * This ensures that any speculatively loaded TLB entries
435 * (even though they may be rare) can not cause any problems,
436 * and ensures that this code is architecturally compliant.
438 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
440 pmd_clear(pmd_off_k(addr));
442 flush_tlb_kernel_range(__phys_to_virt(start),
443 __phys_to_virt(end));
445 iotable_init(&map, 1);
449 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
452 struct page *page = virt_to_page(addr);
453 pgprot_t prot = *(pgprot_t *)data;
455 set_pte_ext(pte, mk_pte(page, prot), 0);
459 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
461 unsigned long start = (unsigned long) page_address(page);
462 unsigned end = start + size;
464 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
465 flush_tlb_kernel_range(start, end);
468 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
469 pgprot_t prot, struct page **ret_page,
470 const void *caller, bool want_vaddr)
474 page = __dma_alloc_buffer(dev, size, gfp);
480 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
482 __dma_free_buffer(page, size);
491 static void *__alloc_from_pool(size_t size, struct page **ret_page)
497 WARN(1, "coherent pool not initialised!\n");
501 val = gen_pool_alloc(atomic_pool, size);
503 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
505 *ret_page = phys_to_page(phys);
512 static bool __in_atomic_pool(void *start, size_t size)
514 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
517 static int __free_from_pool(void *start, size_t size)
519 if (!__in_atomic_pool(start, size))
522 gen_pool_free(atomic_pool, (unsigned long)start, size);
527 static void *__alloc_from_contiguous(struct device *dev, size_t size,
528 pgprot_t prot, struct page **ret_page,
529 const void *caller, bool want_vaddr)
531 unsigned long order = get_order(size);
532 size_t count = size >> PAGE_SHIFT;
536 page = dma_alloc_from_contiguous(dev, count, order);
540 __dma_clear_buffer(page, size);
545 if (PageHighMem(page)) {
546 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
548 dma_release_from_contiguous(dev, page, count);
552 __dma_remap(page, size, prot);
553 ptr = page_address(page);
561 static void __free_from_contiguous(struct device *dev, struct page *page,
562 void *cpu_addr, size_t size, bool want_vaddr)
565 if (PageHighMem(page))
566 __dma_free_remap(cpu_addr, size);
568 __dma_remap(page, size, PAGE_KERNEL);
570 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
573 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
575 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
576 pgprot_writecombine(prot) :
577 pgprot_dmacoherent(prot);
583 #else /* !CONFIG_MMU */
587 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
588 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL
589 #define __alloc_from_pool(size, ret_page) NULL
590 #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL
591 #define __free_from_pool(cpu_addr, size) 0
592 #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0)
593 #define __dma_free_remap(cpu_addr, size) do { } while (0)
595 #endif /* CONFIG_MMU */
597 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
598 struct page **ret_page)
601 page = __dma_alloc_buffer(dev, size, gfp);
606 return page_address(page);
611 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
612 gfp_t gfp, pgprot_t prot, bool is_coherent,
613 struct dma_attrs *attrs, const void *caller)
615 u64 mask = get_coherent_dma_mask(dev);
616 struct page *page = NULL;
620 #ifdef CONFIG_DMA_API_DEBUG
621 u64 limit = (mask + 1) & ~mask;
622 if (limit && size >= limit) {
623 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
632 if (mask < 0xffffffffULL)
636 * Following is a work-around (a.k.a. hack) to prevent pages
637 * with __GFP_COMP being passed to split_page() which cannot
638 * handle them. The real problem is that this flag probably
639 * should be 0 on ARM as it is not supported on this
640 * platform; see CONFIG_HUGETLBFS.
642 gfp &= ~(__GFP_COMP);
644 *handle = DMA_ERROR_CODE;
645 size = PAGE_ALIGN(size);
646 want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
648 if (is_coherent || nommu())
649 addr = __alloc_simple_buffer(dev, size, gfp, &page);
650 else if (!(gfp & __GFP_WAIT))
651 addr = __alloc_from_pool(size, &page);
652 else if (!dev_get_cma_area(dev))
653 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller, want_vaddr);
655 addr = __alloc_from_contiguous(dev, size, prot, &page, caller, want_vaddr);
658 *handle = pfn_to_dma(dev, page_to_pfn(page));
660 return want_vaddr ? addr : page;
664 * Allocate DMA-coherent memory space and return both the kernel remapped
665 * virtual and bus address for that space.
667 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
668 gfp_t gfp, struct dma_attrs *attrs)
670 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
673 if (dma_alloc_from_coherent(dev, size, handle, &memory))
676 return __dma_alloc(dev, size, handle, gfp, prot, false,
677 attrs, __builtin_return_address(0));
680 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
681 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
683 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
686 if (dma_alloc_from_coherent(dev, size, handle, &memory))
689 return __dma_alloc(dev, size, handle, gfp, prot, true,
690 attrs, __builtin_return_address(0));
694 * Create userspace mapping for the DMA-coherent memory.
696 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
697 void *cpu_addr, dma_addr_t dma_addr, size_t size,
698 struct dma_attrs *attrs)
702 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
703 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
704 unsigned long pfn = dma_to_pfn(dev, dma_addr);
705 unsigned long off = vma->vm_pgoff;
707 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
709 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
712 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
713 ret = remap_pfn_range(vma, vma->vm_start,
715 vma->vm_end - vma->vm_start,
718 #endif /* CONFIG_MMU */
724 * Free a buffer as defined by the above mapping.
726 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
727 dma_addr_t handle, struct dma_attrs *attrs,
730 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
731 bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
733 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
736 size = PAGE_ALIGN(size);
738 if (is_coherent || nommu()) {
739 __dma_free_buffer(page, size);
740 } else if (__free_from_pool(cpu_addr, size)) {
742 } else if (!dev_get_cma_area(dev)) {
744 __dma_free_remap(cpu_addr, size);
745 __dma_free_buffer(page, size);
748 * Non-atomic allocations cannot be freed with IRQs disabled
750 WARN_ON(irqs_disabled());
751 __free_from_contiguous(dev, page, cpu_addr, size, want_vaddr);
755 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
756 dma_addr_t handle, struct dma_attrs *attrs)
758 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
761 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
762 dma_addr_t handle, struct dma_attrs *attrs)
764 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
767 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
768 void *cpu_addr, dma_addr_t handle, size_t size,
769 struct dma_attrs *attrs)
771 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
774 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
778 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
782 static void dma_cache_maint_page(struct page *page, unsigned long offset,
783 size_t size, enum dma_data_direction dir,
784 void (*op)(const void *, size_t, int))
789 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
793 * A single sg entry may refer to multiple physically contiguous
794 * pages. But we still need to process highmem pages individually.
795 * If highmem is not configured then the bulk of this loop gets
802 page = pfn_to_page(pfn);
804 if (PageHighMem(page)) {
805 if (len + offset > PAGE_SIZE)
806 len = PAGE_SIZE - offset;
808 if (cache_is_vipt_nonaliasing()) {
809 vaddr = kmap_atomic(page);
810 op(vaddr + offset, len, dir);
811 kunmap_atomic(vaddr);
813 vaddr = kmap_high_get(page);
815 op(vaddr + offset, len, dir);
820 vaddr = page_address(page) + offset;
830 * Make an area consistent for devices.
831 * Note: Drivers should NOT use this function directly, as it will break
832 * platforms with CONFIG_DMABOUNCE.
833 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
835 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
836 size_t size, enum dma_data_direction dir)
840 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
842 paddr = page_to_phys(page) + off;
843 if (dir == DMA_FROM_DEVICE) {
844 outer_inv_range(paddr, paddr + size);
846 outer_clean_range(paddr, paddr + size);
848 /* FIXME: non-speculating: flush on bidirectional mappings? */
851 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
852 size_t size, enum dma_data_direction dir)
854 phys_addr_t paddr = page_to_phys(page) + off;
856 /* FIXME: non-speculating: not required */
857 /* in any case, don't bother invalidating if DMA to device */
858 if (dir != DMA_TO_DEVICE) {
859 outer_inv_range(paddr, paddr + size);
861 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
865 * Mark the D-cache clean for these pages to avoid extra flushing.
867 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
871 pfn = page_to_pfn(page) + off / PAGE_SIZE;
875 left -= PAGE_SIZE - off;
877 while (left >= PAGE_SIZE) {
878 page = pfn_to_page(pfn++);
879 set_bit(PG_dcache_clean, &page->flags);
886 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
887 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
888 * @sg: list of buffers
889 * @nents: number of buffers to map
890 * @dir: DMA transfer direction
892 * Map a set of buffers described by scatterlist in streaming mode for DMA.
893 * This is the scatter-gather version of the dma_map_single interface.
894 * Here the scatter gather list elements are each tagged with the
895 * appropriate dma address and length. They are obtained via
896 * sg_dma_{address,length}.
898 * Device ownership issues as mentioned for dma_map_single are the same
901 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
902 enum dma_data_direction dir, struct dma_attrs *attrs)
904 struct dma_map_ops *ops = get_dma_ops(dev);
905 struct scatterlist *s;
908 for_each_sg(sg, s, nents, i) {
909 #ifdef CONFIG_NEED_SG_DMA_LENGTH
910 s->dma_length = s->length;
912 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
913 s->length, dir, attrs);
914 if (dma_mapping_error(dev, s->dma_address))
920 for_each_sg(sg, s, i, j)
921 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
926 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
927 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
928 * @sg: list of buffers
929 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
930 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
932 * Unmap a set of streaming mode DMA translations. Again, CPU access
933 * rules concerning calls here are the same as for dma_unmap_single().
935 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
936 enum dma_data_direction dir, struct dma_attrs *attrs)
938 struct dma_map_ops *ops = get_dma_ops(dev);
939 struct scatterlist *s;
943 for_each_sg(sg, s, nents, i)
944 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
948 * arm_dma_sync_sg_for_cpu
949 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
950 * @sg: list of buffers
951 * @nents: number of buffers to map (returned from dma_map_sg)
952 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
954 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
955 int nents, enum dma_data_direction dir)
957 struct dma_map_ops *ops = get_dma_ops(dev);
958 struct scatterlist *s;
961 for_each_sg(sg, s, nents, i)
962 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
967 * arm_dma_sync_sg_for_device
968 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
969 * @sg: list of buffers
970 * @nents: number of buffers to map (returned from dma_map_sg)
971 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
973 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
974 int nents, enum dma_data_direction dir)
976 struct dma_map_ops *ops = get_dma_ops(dev);
977 struct scatterlist *s;
980 for_each_sg(sg, s, nents, i)
981 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
986 * Return whether the given device DMA address mask can be supported
987 * properly. For example, if your device can only drive the low 24-bits
988 * during bus mastering, then you would pass 0x00ffffff as the mask
991 int dma_supported(struct device *dev, u64 mask)
993 return __dma_supported(dev, mask, false);
995 EXPORT_SYMBOL(dma_supported);
997 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
999 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1002 *dev->dma_mask = dma_mask;
1007 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1009 static int __init dma_debug_do_init(void)
1011 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1014 fs_initcall(dma_debug_do_init);
1016 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1020 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1022 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1025 unsigned int order = get_order(size);
1026 unsigned int align = 0;
1027 unsigned int count, start;
1028 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1029 unsigned long flags;
1033 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1034 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1036 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1037 align = (1 << order) - 1;
1039 spin_lock_irqsave(&mapping->lock, flags);
1040 for (i = 0; i < mapping->nr_bitmaps; i++) {
1041 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1042 mapping->bits, 0, count, align);
1044 if (start > mapping->bits)
1047 bitmap_set(mapping->bitmaps[i], start, count);
1052 * No unused range found. Try to extend the existing mapping
1053 * and perform a second attempt to reserve an IO virtual
1054 * address range of size bytes.
1056 if (i == mapping->nr_bitmaps) {
1057 if (extend_iommu_mapping(mapping)) {
1058 spin_unlock_irqrestore(&mapping->lock, flags);
1059 return DMA_ERROR_CODE;
1062 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1063 mapping->bits, 0, count, align);
1065 if (start > mapping->bits) {
1066 spin_unlock_irqrestore(&mapping->lock, flags);
1067 return DMA_ERROR_CODE;
1070 bitmap_set(mapping->bitmaps[i], start, count);
1072 spin_unlock_irqrestore(&mapping->lock, flags);
1074 iova = mapping->base + (mapping_size * i);
1075 iova += start << PAGE_SHIFT;
1080 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1081 dma_addr_t addr, size_t size)
1083 unsigned int start, count;
1084 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1085 unsigned long flags;
1086 dma_addr_t bitmap_base;
1092 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1093 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1095 bitmap_base = mapping->base + mapping_size * bitmap_index;
1097 start = (addr - bitmap_base) >> PAGE_SHIFT;
1099 if (addr + size > bitmap_base + mapping_size) {
1101 * The address range to be freed reaches into the iova
1102 * range of the next bitmap. This should not happen as
1103 * we don't allow this in __alloc_iova (at the
1108 count = size >> PAGE_SHIFT;
1110 spin_lock_irqsave(&mapping->lock, flags);
1111 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1112 spin_unlock_irqrestore(&mapping->lock, flags);
1115 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1116 gfp_t gfp, struct dma_attrs *attrs)
1118 struct page **pages;
1119 int count = size >> PAGE_SHIFT;
1120 int array_size = count * sizeof(struct page *);
1123 if (array_size <= PAGE_SIZE)
1124 pages = kzalloc(array_size, GFP_KERNEL);
1126 pages = vzalloc(array_size);
1130 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1132 unsigned long order = get_order(size);
1135 page = dma_alloc_from_contiguous(dev, count, order);
1139 __dma_clear_buffer(page, size);
1141 for (i = 0; i < count; i++)
1142 pages[i] = page + i;
1148 * IOMMU can map any pages, so himem can also be used here
1150 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1155 for (order = __fls(count); order > 0; --order) {
1157 * We do not want OOM killer to be invoked as long
1158 * as we can fall back to single pages, so we force
1159 * __GFP_NORETRY for orders higher than zero.
1161 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
1168 * Fall back to single page allocation.
1169 * Might invoke OOM killer as last resort.
1171 pages[i] = alloc_pages(gfp, 0);
1177 split_page(pages[i], order);
1180 pages[i + j] = pages[i] + j;
1183 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1185 count -= 1 << order;
1192 __free_pages(pages[i], 0);
1193 if (array_size <= PAGE_SIZE)
1200 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1201 size_t size, struct dma_attrs *attrs)
1203 int count = size >> PAGE_SHIFT;
1204 int array_size = count * sizeof(struct page *);
1207 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1208 dma_release_from_contiguous(dev, pages[0], count);
1210 for (i = 0; i < count; i++)
1212 __free_pages(pages[i], 0);
1215 if (array_size <= PAGE_SIZE)
1223 * Create a CPU mapping for a specified pages
1226 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1229 return dma_common_pages_remap(pages, size,
1230 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1234 * Create a mapping in device IO address space for specified pages
1237 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1239 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1240 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1241 dma_addr_t dma_addr, iova;
1242 int i, ret = DMA_ERROR_CODE;
1244 dma_addr = __alloc_iova(mapping, size);
1245 if (dma_addr == DMA_ERROR_CODE)
1249 for (i = 0; i < count; ) {
1250 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1251 phys_addr_t phys = page_to_phys(pages[i]);
1252 unsigned int len, j;
1254 for (j = i + 1; j < count; j++, next_pfn++)
1255 if (page_to_pfn(pages[j]) != next_pfn)
1258 len = (j - i) << PAGE_SHIFT;
1259 ret = iommu_map(mapping->domain, iova, phys, len,
1260 IOMMU_READ|IOMMU_WRITE);
1268 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1269 __free_iova(mapping, dma_addr, size);
1270 return DMA_ERROR_CODE;
1273 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1275 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1278 * add optional in-page offset from iova to size and align
1279 * result to page size
1281 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1284 iommu_unmap(mapping->domain, iova, size);
1285 __free_iova(mapping, iova, size);
1289 static struct page **__atomic_get_pages(void *addr)
1294 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1295 page = phys_to_page(phys);
1297 return (struct page **)page;
1300 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1302 struct vm_struct *area;
1304 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1305 return __atomic_get_pages(cpu_addr);
1307 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1310 area = find_vm_area(cpu_addr);
1311 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1316 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1322 addr = __alloc_from_pool(size, &page);
1326 *handle = __iommu_create_mapping(dev, &page, size);
1327 if (*handle == DMA_ERROR_CODE)
1333 __free_from_pool(addr, size);
1337 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1338 dma_addr_t handle, size_t size)
1340 __iommu_remove_mapping(dev, handle, size);
1341 __free_from_pool(cpu_addr, size);
1344 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1345 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1347 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1348 struct page **pages;
1351 *handle = DMA_ERROR_CODE;
1352 size = PAGE_ALIGN(size);
1354 if (!(gfp & __GFP_WAIT))
1355 return __iommu_alloc_atomic(dev, size, handle);
1358 * Following is a work-around (a.k.a. hack) to prevent pages
1359 * with __GFP_COMP being passed to split_page() which cannot
1360 * handle them. The real problem is that this flag probably
1361 * should be 0 on ARM as it is not supported on this
1362 * platform; see CONFIG_HUGETLBFS.
1364 gfp &= ~(__GFP_COMP);
1366 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1370 *handle = __iommu_create_mapping(dev, pages, size);
1371 if (*handle == DMA_ERROR_CODE)
1374 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1377 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1378 __builtin_return_address(0));
1385 __iommu_remove_mapping(dev, *handle, size);
1387 __iommu_free_buffer(dev, pages, size, attrs);
1391 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1392 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1393 struct dma_attrs *attrs)
1395 unsigned long uaddr = vma->vm_start;
1396 unsigned long usize = vma->vm_end - vma->vm_start;
1397 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1399 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1405 int ret = vm_insert_page(vma, uaddr, *pages++);
1407 pr_err("Remapping memory failed: %d\n", ret);
1412 } while (usize > 0);
1418 * free a page as defined by the above mapping.
1419 * Must not be called with IRQs disabled.
1421 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1422 dma_addr_t handle, struct dma_attrs *attrs)
1424 struct page **pages;
1425 size = PAGE_ALIGN(size);
1427 if (__in_atomic_pool(cpu_addr, size)) {
1428 __iommu_free_atomic(dev, cpu_addr, handle, size);
1432 pages = __iommu_get_pages(cpu_addr, attrs);
1434 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1438 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1439 dma_common_free_remap(cpu_addr, size,
1440 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1443 __iommu_remove_mapping(dev, handle, size);
1444 __iommu_free_buffer(dev, pages, size, attrs);
1447 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1448 void *cpu_addr, dma_addr_t dma_addr,
1449 size_t size, struct dma_attrs *attrs)
1451 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1452 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1457 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1461 static int __dma_direction_to_prot(enum dma_data_direction dir)
1466 case DMA_BIDIRECTIONAL:
1467 prot = IOMMU_READ | IOMMU_WRITE;
1472 case DMA_FROM_DEVICE:
1483 * Map a part of the scatter-gather list into contiguous io address space
1485 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1486 size_t size, dma_addr_t *handle,
1487 enum dma_data_direction dir, struct dma_attrs *attrs,
1490 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1491 dma_addr_t iova, iova_base;
1494 struct scatterlist *s;
1497 size = PAGE_ALIGN(size);
1498 *handle = DMA_ERROR_CODE;
1500 iova_base = iova = __alloc_iova(mapping, size);
1501 if (iova == DMA_ERROR_CODE)
1504 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1505 phys_addr_t phys = page_to_phys(sg_page(s));
1506 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1509 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1510 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1512 prot = __dma_direction_to_prot(dir);
1514 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1517 count += len >> PAGE_SHIFT;
1520 *handle = iova_base;
1524 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1525 __free_iova(mapping, iova_base, size);
1529 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1530 enum dma_data_direction dir, struct dma_attrs *attrs,
1533 struct scatterlist *s = sg, *dma = sg, *start = sg;
1535 unsigned int offset = s->offset;
1536 unsigned int size = s->offset + s->length;
1537 unsigned int max = dma_get_max_seg_size(dev);
1539 for (i = 1; i < nents; i++) {
1542 s->dma_address = DMA_ERROR_CODE;
1545 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1546 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1547 dir, attrs, is_coherent) < 0)
1550 dma->dma_address += offset;
1551 dma->dma_length = size - offset;
1553 size = offset = s->offset;
1560 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1564 dma->dma_address += offset;
1565 dma->dma_length = size - offset;
1570 for_each_sg(sg, s, count, i)
1571 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1576 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1577 * @dev: valid struct device pointer
1578 * @sg: list of buffers
1579 * @nents: number of buffers to map
1580 * @dir: DMA transfer direction
1582 * Map a set of i/o coherent buffers described by scatterlist in streaming
1583 * mode for DMA. The scatter gather list elements are merged together (if
1584 * possible) and tagged with the appropriate dma address and length. They are
1585 * obtained via sg_dma_{address,length}.
1587 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1588 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1590 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1594 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1595 * @dev: valid struct device pointer
1596 * @sg: list of buffers
1597 * @nents: number of buffers to map
1598 * @dir: DMA transfer direction
1600 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1601 * The scatter gather list elements are merged together (if possible) and
1602 * tagged with the appropriate dma address and length. They are obtained via
1603 * sg_dma_{address,length}.
1605 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1606 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1608 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1611 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1612 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1615 struct scatterlist *s;
1618 for_each_sg(sg, s, nents, i) {
1620 __iommu_remove_mapping(dev, sg_dma_address(s),
1623 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1624 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1630 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1631 * @dev: valid struct device pointer
1632 * @sg: list of buffers
1633 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1634 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1636 * Unmap a set of streaming mode DMA translations. Again, CPU access
1637 * rules concerning calls here are the same as for dma_unmap_single().
1639 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1640 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1642 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1646 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1647 * @dev: valid struct device pointer
1648 * @sg: list of buffers
1649 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1650 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1652 * Unmap a set of streaming mode DMA translations. Again, CPU access
1653 * rules concerning calls here are the same as for dma_unmap_single().
1655 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1656 enum dma_data_direction dir, struct dma_attrs *attrs)
1658 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1662 * arm_iommu_sync_sg_for_cpu
1663 * @dev: valid struct device pointer
1664 * @sg: list of buffers
1665 * @nents: number of buffers to map (returned from dma_map_sg)
1666 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1668 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1669 int nents, enum dma_data_direction dir)
1671 struct scatterlist *s;
1674 for_each_sg(sg, s, nents, i)
1675 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1680 * arm_iommu_sync_sg_for_device
1681 * @dev: valid struct device pointer
1682 * @sg: list of buffers
1683 * @nents: number of buffers to map (returned from dma_map_sg)
1684 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1686 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1687 int nents, enum dma_data_direction dir)
1689 struct scatterlist *s;
1692 for_each_sg(sg, s, nents, i)
1693 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1698 * arm_coherent_iommu_map_page
1699 * @dev: valid struct device pointer
1700 * @page: page that buffer resides in
1701 * @offset: offset into page for start of buffer
1702 * @size: size of buffer to map
1703 * @dir: DMA transfer direction
1705 * Coherent IOMMU aware version of arm_dma_map_page()
1707 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1708 unsigned long offset, size_t size, enum dma_data_direction dir,
1709 struct dma_attrs *attrs)
1711 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1712 dma_addr_t dma_addr;
1713 int ret, prot, len = PAGE_ALIGN(size + offset);
1715 dma_addr = __alloc_iova(mapping, len);
1716 if (dma_addr == DMA_ERROR_CODE)
1719 prot = __dma_direction_to_prot(dir);
1721 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1725 return dma_addr + offset;
1727 __free_iova(mapping, dma_addr, len);
1728 return DMA_ERROR_CODE;
1732 * arm_iommu_map_page
1733 * @dev: valid struct device pointer
1734 * @page: page that buffer resides in
1735 * @offset: offset into page for start of buffer
1736 * @size: size of buffer to map
1737 * @dir: DMA transfer direction
1739 * IOMMU aware version of arm_dma_map_page()
1741 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1742 unsigned long offset, size_t size, enum dma_data_direction dir,
1743 struct dma_attrs *attrs)
1745 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1746 __dma_page_cpu_to_dev(page, offset, size, dir);
1748 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1752 * arm_coherent_iommu_unmap_page
1753 * @dev: valid struct device pointer
1754 * @handle: DMA address of buffer
1755 * @size: size of buffer (same as passed to dma_map_page)
1756 * @dir: DMA transfer direction (same as passed to dma_map_page)
1758 * Coherent IOMMU aware version of arm_dma_unmap_page()
1760 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1761 size_t size, enum dma_data_direction dir,
1762 struct dma_attrs *attrs)
1764 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1765 dma_addr_t iova = handle & PAGE_MASK;
1766 int offset = handle & ~PAGE_MASK;
1767 int len = PAGE_ALIGN(size + offset);
1772 iommu_unmap(mapping->domain, iova, len);
1773 __free_iova(mapping, iova, len);
1777 * arm_iommu_unmap_page
1778 * @dev: valid struct device pointer
1779 * @handle: DMA address of buffer
1780 * @size: size of buffer (same as passed to dma_map_page)
1781 * @dir: DMA transfer direction (same as passed to dma_map_page)
1783 * IOMMU aware version of arm_dma_unmap_page()
1785 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1786 size_t size, enum dma_data_direction dir,
1787 struct dma_attrs *attrs)
1789 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1790 dma_addr_t iova = handle & PAGE_MASK;
1791 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1792 int offset = handle & ~PAGE_MASK;
1793 int len = PAGE_ALIGN(size + offset);
1798 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1799 __dma_page_dev_to_cpu(page, offset, size, dir);
1801 iommu_unmap(mapping->domain, iova, len);
1802 __free_iova(mapping, iova, len);
1805 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1806 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1808 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1809 dma_addr_t iova = handle & PAGE_MASK;
1810 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1811 unsigned int offset = handle & ~PAGE_MASK;
1816 __dma_page_dev_to_cpu(page, offset, size, dir);
1819 static void arm_iommu_sync_single_for_device(struct device *dev,
1820 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1822 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1823 dma_addr_t iova = handle & PAGE_MASK;
1824 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1825 unsigned int offset = handle & ~PAGE_MASK;
1830 __dma_page_cpu_to_dev(page, offset, size, dir);
1833 struct dma_map_ops iommu_ops = {
1834 .alloc = arm_iommu_alloc_attrs,
1835 .free = arm_iommu_free_attrs,
1836 .mmap = arm_iommu_mmap_attrs,
1837 .get_sgtable = arm_iommu_get_sgtable,
1839 .map_page = arm_iommu_map_page,
1840 .unmap_page = arm_iommu_unmap_page,
1841 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1842 .sync_single_for_device = arm_iommu_sync_single_for_device,
1844 .map_sg = arm_iommu_map_sg,
1845 .unmap_sg = arm_iommu_unmap_sg,
1846 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1847 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1849 .set_dma_mask = arm_dma_set_mask,
1852 struct dma_map_ops iommu_coherent_ops = {
1853 .alloc = arm_iommu_alloc_attrs,
1854 .free = arm_iommu_free_attrs,
1855 .mmap = arm_iommu_mmap_attrs,
1856 .get_sgtable = arm_iommu_get_sgtable,
1858 .map_page = arm_coherent_iommu_map_page,
1859 .unmap_page = arm_coherent_iommu_unmap_page,
1861 .map_sg = arm_coherent_iommu_map_sg,
1862 .unmap_sg = arm_coherent_iommu_unmap_sg,
1864 .set_dma_mask = arm_dma_set_mask,
1868 * arm_iommu_create_mapping
1869 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1870 * @base: start address of the valid IO address space
1871 * @size: maximum size of the valid IO address space
1873 * Creates a mapping structure which holds information about used/unused
1874 * IO address ranges, which is required to perform memory allocation and
1875 * mapping with IOMMU aware functions.
1877 * The client device need to be attached to the mapping with
1878 * arm_iommu_attach_device function.
1880 struct dma_iommu_mapping *
1881 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
1883 unsigned int bits = size >> PAGE_SHIFT;
1884 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1885 struct dma_iommu_mapping *mapping;
1889 /* currently only 32-bit DMA address space is supported */
1890 if (size > DMA_BIT_MASK(32) + 1)
1891 return ERR_PTR(-ERANGE);
1894 return ERR_PTR(-EINVAL);
1896 if (bitmap_size > PAGE_SIZE) {
1897 extensions = bitmap_size / PAGE_SIZE;
1898 bitmap_size = PAGE_SIZE;
1901 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1905 mapping->bitmap_size = bitmap_size;
1906 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
1908 if (!mapping->bitmaps)
1911 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1912 if (!mapping->bitmaps[0])
1915 mapping->nr_bitmaps = 1;
1916 mapping->extensions = extensions;
1917 mapping->base = base;
1918 mapping->bits = BITS_PER_BYTE * bitmap_size;
1920 spin_lock_init(&mapping->lock);
1922 mapping->domain = iommu_domain_alloc(bus);
1923 if (!mapping->domain)
1926 kref_init(&mapping->kref);
1929 kfree(mapping->bitmaps[0]);
1931 kfree(mapping->bitmaps);
1935 return ERR_PTR(err);
1937 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1939 static void release_iommu_mapping(struct kref *kref)
1942 struct dma_iommu_mapping *mapping =
1943 container_of(kref, struct dma_iommu_mapping, kref);
1945 iommu_domain_free(mapping->domain);
1946 for (i = 0; i < mapping->nr_bitmaps; i++)
1947 kfree(mapping->bitmaps[i]);
1948 kfree(mapping->bitmaps);
1952 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
1956 if (mapping->nr_bitmaps > mapping->extensions)
1959 next_bitmap = mapping->nr_bitmaps;
1960 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
1962 if (!mapping->bitmaps[next_bitmap])
1965 mapping->nr_bitmaps++;
1970 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1973 kref_put(&mapping->kref, release_iommu_mapping);
1975 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1977 static int __arm_iommu_attach_device(struct device *dev,
1978 struct dma_iommu_mapping *mapping)
1982 err = iommu_attach_device(mapping->domain, dev);
1986 kref_get(&mapping->kref);
1987 to_dma_iommu_mapping(dev) = mapping;
1989 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
1994 * arm_iommu_attach_device
1995 * @dev: valid struct device pointer
1996 * @mapping: io address space mapping structure (returned from
1997 * arm_iommu_create_mapping)
1999 * Attaches specified io address space mapping to the provided device.
2000 * This replaces the dma operations (dma_map_ops pointer) with the
2001 * IOMMU aware version.
2003 * More than one client might be attached to the same io address space
2006 int arm_iommu_attach_device(struct device *dev,
2007 struct dma_iommu_mapping *mapping)
2011 err = __arm_iommu_attach_device(dev, mapping);
2015 set_dma_ops(dev, &iommu_ops);
2018 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2020 static void __arm_iommu_detach_device(struct device *dev)
2022 struct dma_iommu_mapping *mapping;
2024 mapping = to_dma_iommu_mapping(dev);
2026 dev_warn(dev, "Not attached\n");
2030 iommu_detach_device(mapping->domain, dev);
2031 kref_put(&mapping->kref, release_iommu_mapping);
2032 to_dma_iommu_mapping(dev) = NULL;
2034 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2038 * arm_iommu_detach_device
2039 * @dev: valid struct device pointer
2041 * Detaches the provided device from a previously attached map.
2042 * This voids the dma operations (dma_map_ops pointer)
2044 void arm_iommu_detach_device(struct device *dev)
2046 __arm_iommu_detach_device(dev);
2047 set_dma_ops(dev, NULL);
2049 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
2051 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
2053 return coherent ? &iommu_coherent_ops : &iommu_ops;
2056 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2057 struct iommu_ops *iommu)
2059 struct dma_iommu_mapping *mapping;
2064 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2065 if (IS_ERR(mapping)) {
2066 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
2067 size, dev_name(dev));
2071 if (__arm_iommu_attach_device(dev, mapping)) {
2072 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
2074 arm_iommu_release_mapping(mapping);
2081 static void arm_teardown_iommu_dma_ops(struct device *dev)
2083 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2088 __arm_iommu_detach_device(dev);
2089 arm_iommu_release_mapping(mapping);
2094 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2095 struct iommu_ops *iommu)
2100 static void arm_teardown_iommu_dma_ops(struct device *dev) { }
2102 #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops
2104 #endif /* CONFIG_ARM_DMA_USE_IOMMU */
2106 static struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
2108 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;
2111 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
2112 struct iommu_ops *iommu, bool coherent)
2114 struct dma_map_ops *dma_ops;
2116 dev->archdata.dma_coherent = coherent;
2117 if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu))
2118 dma_ops = arm_get_iommu_dma_map_ops(coherent);
2120 dma_ops = arm_get_dma_map_ops(coherent);
2122 set_dma_ops(dev, dma_ops);
2125 void arch_teardown_dma_ops(struct device *dev)
2127 arm_teardown_iommu_dma_ops(dev);