arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sizes.h>
  20
  21 #include <asm/cp15.h>
  22 #include <asm/cputype.h>
  23 #include <asm/sections.h>
  24 #include <asm/cachetype.h>
  25 #include <asm/setup.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/tlb.h>
  28 #include <asm/highmem.h>
  29 #include <asm/system_info.h>
  30 #include <asm/traps.h>
  31
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/pci.h>
  35
  36 #include "mm.h"
  37 #include "tcm.h"
  38
  39 /*
  40  * empty_zero_page is a special page that is used for
  41  * zero-initialized data and COW.
  42  */
  43 struct page *empty_zero_page;
  44 EXPORT_SYMBOL(empty_zero_page);
  45
  46 /*
  47  * The pmd table for the upper-most set of pages.
  48  */
  49 pmd_t *top_pmd;
  50
  51 #define CPOLICY_UNCACHED        0
  52 #define CPOLICY_BUFFERED        1
  53 #define CPOLICY_WRITETHROUGH    2
  54 #define CPOLICY_WRITEBACK       3
  55 #define CPOLICY_WRITEALLOC      4
  56
  57 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  58 static unsigned int ecc_mask __initdata = 0;
  59 pgprot_t pgprot_user;
  60 pgprot_t pgprot_kernel;
  61 pgprot_t pgprot_hyp_device;
  62 pgprot_t pgprot_s2;
  63 pgprot_t pgprot_s2_device;
  64
  65 EXPORT_SYMBOL(pgprot_user);
  66 EXPORT_SYMBOL(pgprot_kernel);
  67
  68 struct cachepolicy {
  69         const char      policy[16];
  70         unsigned int    cr_mask;
  71         pmdval_t        pmd;
  72         pteval_t        pte;
  73         pteval_t        pte_s2;
  74 };
  75
  76 #ifdef CONFIG_ARM_LPAE
  77 #define s2_policy(policy)       policy
  78 #else
  79 #define s2_policy(policy)       0
  80 #endif
  81
  82 static struct cachepolicy cache_policies[] __initdata = {
  83         {
  84                 .policy         = "uncached",
  85                 .cr_mask        = CR_W|CR_C,
  86                 .pmd            = PMD_SECT_UNCACHED,
  87                 .pte            = L_PTE_MT_UNCACHED,
  88                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  89         }, {
  90                 .policy         = "buffered",
  91                 .cr_mask        = CR_C,
  92                 .pmd            = PMD_SECT_BUFFERED,
  93                 .pte            = L_PTE_MT_BUFFERABLE,
  94                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  95         }, {
  96                 .policy         = "writethrough",
  97                 .cr_mask        = 0,
  98                 .pmd            = PMD_SECT_WT,
  99                 .pte            = L_PTE_MT_WRITETHROUGH,
 100                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
 101         }, {
 102                 .policy         = "writeback",
 103                 .cr_mask        = 0,
 104                 .pmd            = PMD_SECT_WB,
 105                 .pte            = L_PTE_MT_WRITEBACK,
 106                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 107         }, {
 108                 .policy         = "writealloc",
 109                 .cr_mask        = 0,
 110                 .pmd            = PMD_SECT_WBWA,
 111                 .pte            = L_PTE_MT_WRITEALLOC,
 112                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 113         }
 114 };
 115
 116 /*
 117  * These are useful for identifying cache coherency
 118  * problems by allowing the cache or the cache and
 119  * writebuffer to be turned off.  (Note: the write
 120  * buffer should not be on and the cache off).
 121  */
 122 static int __init early_cachepolicy(char *p)
 123 {
 124         int i;
 125
 126         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 127                 int len = strlen(cache_policies[i].policy);
 128
 129                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 130                         cachepolicy = i;
 131                         cr_alignment &= ~cache_policies[i].cr_mask;
 132                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 133                         break;
 134                 }
 135         }
 136         if (i == ARRAY_SIZE(cache_policies))
 137                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 138         /*
 139          * This restriction is partly to do with the way we boot; it is
 140          * unpredictable to have memory mapped using two different sets of
 141          * memory attributes (shared, type, and cache attribs).  We can not
 142          * change these attributes once the initial assembly has setup the
 143          * page tables.
 144          */
 145         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 146                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 147                 cachepolicy = CPOLICY_WRITEBACK;
 148         }
 149         flush_cache_all();
 150         set_cr(cr_alignment);
 151         return 0;
 152 }
 153 early_param("cachepolicy", early_cachepolicy);
 154
 155 static int __init early_nocache(char *__unused)
 156 {
 157         char *p = "buffered";
 158         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 159         early_cachepolicy(p);
 160         return 0;
 161 }
 162 early_param("nocache", early_nocache);
 163
 164 static int __init early_nowrite(char *__unused)
 165 {
 166         char *p = "uncached";
 167         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 168         early_cachepolicy(p);
 169         return 0;
 170 }
 171 early_param("nowb", early_nowrite);
 172
 173 #ifndef CONFIG_ARM_LPAE
 174 static int __init early_ecc(char *p)
 175 {
 176         if (memcmp(p, "on", 2) == 0)
 177                 ecc_mask = PMD_PROTECTION;
 178         else if (memcmp(p, "off", 3) == 0)
 179                 ecc_mask = 0;
 180         return 0;
 181 }
 182 early_param("ecc", early_ecc);
 183 #endif
 184
 185 static int __init noalign_setup(char *__unused)
 186 {
 187         cr_alignment &= ~CR_A;
 188         cr_no_alignment &= ~CR_A;
 189         set_cr(cr_alignment);
 190         return 1;
 191 }
 192 __setup("noalign", noalign_setup);
 193
 194 #ifndef CONFIG_SMP
 195 void adjust_cr(unsigned long mask, unsigned long set)
 196 {
 197         unsigned long flags;
 198
 199         mask &= ~CR_A;
 200
 201         set &= mask;
 202
 203         local_irq_save(flags);
 204
 205         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 206         cr_alignment = (cr_alignment & ~mask) | set;
 207
 208         set_cr((get_cr() & ~mask) | set);
 209
 210         local_irq_restore(flags);
 211 }
 212 #endif
 213
 214 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 215 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 216
 217 static struct mem_type mem_types[] = {
 218         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 219                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 220                                   L_PTE_SHARED,
 221                 .prot_l1        = PMD_TYPE_TABLE,
 222                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 223                 .domain         = DOMAIN_IO,
 224         },
 225         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 226                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 227                 .prot_l1        = PMD_TYPE_TABLE,
 228                 .prot_sect      = PROT_SECT_DEVICE,
 229                 .domain         = DOMAIN_IO,
 230         },
 231         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 232                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 233                 .prot_l1        = PMD_TYPE_TABLE,
 234                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 235                 .domain         = DOMAIN_IO,
 236         },
 237         [MT_DEVICE_WC] = {      /* ioremap_wc */
 238                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 239                 .prot_l1        = PMD_TYPE_TABLE,
 240                 .prot_sect      = PROT_SECT_DEVICE,
 241                 .domain         = DOMAIN_IO,
 242         },
 243         [MT_UNCACHED] = {
 244                 .prot_pte       = PROT_PTE_DEVICE,
 245                 .prot_l1        = PMD_TYPE_TABLE,
 246                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 247                 .domain         = DOMAIN_IO,
 248         },
 249         [MT_CACHECLEAN] = {
 250                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 251                 .domain    = DOMAIN_KERNEL,
 252         },
 253 #ifndef CONFIG_ARM_LPAE
 254         [MT_MINICLEAN] = {
 255                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 256                 .domain    = DOMAIN_KERNEL,
 257         },
 258 #endif
 259         [MT_LOW_VECTORS] = {
 260                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 261                                 L_PTE_RDONLY,
 262                 .prot_l1   = PMD_TYPE_TABLE,
 263                 .domain    = DOMAIN_USER,
 264         },
 265         [MT_HIGH_VECTORS] = {
 266                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 267                                 L_PTE_USER | L_PTE_RDONLY,
 268                 .prot_l1   = PMD_TYPE_TABLE,
 269                 .domain    = DOMAIN_USER,
 270         },
 271         [MT_MEMORY] = {
 272                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 273                 .prot_l1   = PMD_TYPE_TABLE,
 274                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 275                 .domain    = DOMAIN_KERNEL,
 276         },
 277         [MT_ROM] = {
 278                 .prot_sect = PMD_TYPE_SECT,
 279                 .domain    = DOMAIN_KERNEL,
 280         },
 281         [MT_MEMORY_NONCACHED] = {
 282                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 283                                 L_PTE_MT_BUFFERABLE,
 284                 .prot_l1   = PMD_TYPE_TABLE,
 285                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 286                 .domain    = DOMAIN_KERNEL,
 287         },
 288         [MT_MEMORY_DTCM] = {
 289                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 290                                 L_PTE_XN,
 291                 .prot_l1   = PMD_TYPE_TABLE,
 292                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 293                 .domain    = DOMAIN_KERNEL,
 294         },
 295         [MT_MEMORY_ITCM] = {
 296                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 297                 .prot_l1   = PMD_TYPE_TABLE,
 298                 .domain    = DOMAIN_KERNEL,
 299         },
 300         [MT_MEMORY_SO] = {
 301                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 302                                 L_PTE_MT_UNCACHED | L_PTE_XN,
 303                 .prot_l1   = PMD_TYPE_TABLE,
 304                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 305                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 306                 .domain    = DOMAIN_KERNEL,
 307         },
 308         [MT_MEMORY_DMA_READY] = {
 309                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 310                 .prot_l1   = PMD_TYPE_TABLE,
 311                 .domain    = DOMAIN_KERNEL,
 312         },
 313 };
 314
 315 const struct mem_type *get_mem_type(unsigned int type)
 316 {
 317         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 318 }
 319 EXPORT_SYMBOL(get_mem_type);
 320
 321 /*
 322  * Adjust the PMD section entries according to the CPU in use.
 323  */
 324 static void __init build_mem_type_table(void)
 325 {
 326         struct cachepolicy *cp;
 327         unsigned int cr = get_cr();
 328         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 329         pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
 330         int cpu_arch = cpu_architecture();
 331         int i;
 332
 333         if (cpu_arch < CPU_ARCH_ARMv6) {
 334 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 335                 if (cachepolicy > CPOLICY_BUFFERED)
 336                         cachepolicy = CPOLICY_BUFFERED;
 337 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 338                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 339                         cachepolicy = CPOLICY_WRITETHROUGH;
 340 #endif
 341         }
 342         if (cpu_arch < CPU_ARCH_ARMv5) {
 343                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 344                         cachepolicy = CPOLICY_WRITEBACK;
 345                 ecc_mask = 0;
 346         }
 347         if (is_smp())
 348                 cachepolicy = CPOLICY_WRITEALLOC;
 349
 350         /*
 351          * Strip out features not present on earlier architectures.
 352          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 353          * without extended page tables don't have the 'Shared' bit.
 354          */
 355         if (cpu_arch < CPU_ARCH_ARMv5)
 356                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 357                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 358         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 359                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 360                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 361
 362         /*
 363          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 364          * "update-able on write" bit on ARM610).  However, Xscale and
 365          * Xscale3 require this bit to be cleared.
 366          */
 367         if (cpu_is_xscale() || cpu_is_xsc3()) {
 368                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 369                         mem_types[i].prot_sect &= ~PMD_BIT4;
 370                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 371                 }
 372         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 373                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 374                         if (mem_types[i].prot_l1)
 375                                 mem_types[i].prot_l1 |= PMD_BIT4;
 376                         if (mem_types[i].prot_sect)
 377                                 mem_types[i].prot_sect |= PMD_BIT4;
 378                 }
 379         }
 380
 381         /*
 382          * Mark the device areas according to the CPU/architecture.
 383          */
 384         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 385                 if (!cpu_is_xsc3()) {
 386                         /*
 387                          * Mark device regions on ARMv6+ as execute-never
 388                          * to prevent speculative instruction fetches.
 389                          */
 390                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 391                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 392                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 393                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 394                 }
 395                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 396                         /*
 397                          * For ARMv7 with TEX remapping,
 398                          * - shared device is SXCB=1100
 399                          * - nonshared device is SXCB=0100
 400                          * - write combine device mem is SXCB=0001
 401                          * (Uncached Normal memory)
 402                          */
 403                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 404                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 405                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 406                 } else if (cpu_is_xsc3()) {
 407                         /*
 408                          * For Xscale3,
 409                          * - shared device is TEXCB=00101
 410                          * - nonshared device is TEXCB=01000
 411                          * - write combine device mem is TEXCB=00100
 412                          * (Inner/Outer Uncacheable in xsc3 parlance)
 413                          */
 414                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 415                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 416                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 417                 } else {
 418                         /*
 419                          * For ARMv6 and ARMv7 without TEX remapping,
 420                          * - shared device is TEXCB=00001
 421                          * - nonshared device is TEXCB=01000
 422                          * - write combine device mem is TEXCB=00100
 423                          * (Uncached Normal in ARMv6 parlance).
 424                          */
 425                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 426                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 427                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 428                 }
 429         } else {
 430                 /*
 431                  * On others, write combining is "Uncached/Buffered"
 432                  */
 433                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 434         }
 435
 436         /*
 437          * Now deal with the memory-type mappings
 438          */
 439         cp = &cache_policies[cachepolicy];
 440         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 441         s2_pgprot = cp->pte_s2;
 442         hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
 443
 444         /*
 445          * ARMv6 and above have extended page tables.
 446          */
 447         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 448 #ifndef CONFIG_ARM_LPAE
 449                 /*
 450                  * Mark cache clean areas and XIP ROM read only
 451                  * from SVC mode and no access from userspace.
 452                  */
 453                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 454                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 455                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 456 #endif
 457
 458                 if (is_smp()) {
 459                         /*
 460                          * Mark memory with the "shared" attribute
 461                          * for SMP systems
 462                          */
 463                         user_pgprot |= L_PTE_SHARED;
 464                         kern_pgprot |= L_PTE_SHARED;
 465                         vecs_pgprot |= L_PTE_SHARED;
 466                         s2_pgprot |= L_PTE_SHARED;
 467                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 468                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 469                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 470                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 471                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 472                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 473                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 474                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 475                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 476                 }
 477         }
 478
 479         /*
 480          * Non-cacheable Normal - intended for memory areas that must
 481          * not cause dirty cache line writebacks when used
 482          */
 483         if (cpu_arch >= CPU_ARCH_ARMv6) {
 484                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 485                         /* Non-cacheable Normal is XCB = 001 */
 486                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 487                                 PMD_SECT_BUFFERED;
 488                 } else {
 489                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 490                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 491                                 PMD_SECT_TEX(1);
 492                 }
 493         } else {
 494                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 495         }
 496
 497 #ifdef CONFIG_ARM_LPAE
 498         /*
 499          * Do not generate access flag faults for the kernel mappings.
 500          */
 501         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 502                 mem_types[i].prot_pte |= PTE_EXT_AF;
 503                 if (mem_types[i].prot_sect)
 504                         mem_types[i].prot_sect |= PMD_SECT_AF;
 505         }
 506         kern_pgprot |= PTE_EXT_AF;
 507         vecs_pgprot |= PTE_EXT_AF;
 508 #endif
 509
 510         for (i = 0; i < 16; i++) {
 511                 pteval_t v = pgprot_val(protection_map[i]);
 512                 protection_map[i] = __pgprot(v | user_pgprot);
 513         }
 514
 515         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 516         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 517
 518         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 519         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 520                                  L_PTE_DIRTY | kern_pgprot);
 521         pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
 522         pgprot_s2_device  = __pgprot(s2_device_pgprot);
 523         pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
 524
 525         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 526         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 527         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 528         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 529         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 530         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 531         mem_types[MT_ROM].prot_sect |= cp->pmd;
 532
 533         switch (cp->pmd) {
 534         case PMD_SECT_WT:
 535                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 536                 break;
 537         case PMD_SECT_WB:
 538         case PMD_SECT_WBWA:
 539                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 540                 break;
 541         }
 542         printk("Memory policy: ECC %sabled, Data cache %s\n",
 543                 ecc_mask ? "en" : "dis", cp->policy);
 544
 545         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 546                 struct mem_type *t = &mem_types[i];
 547                 if (t->prot_l1)
 548                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 549                 if (t->prot_sect)
 550                         t->prot_sect |= PMD_DOMAIN(t->domain);
 551         }
 552 }
 553
 554 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 555 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 556                               unsigned long size, pgprot_t vma_prot)
 557 {
 558         if (!pfn_valid(pfn))
 559                 return pgprot_noncached(vma_prot);
 560         else if (file->f_flags & O_SYNC)
 561                 return pgprot_writecombine(vma_prot);
 562         return vma_prot;
 563 }
 564 EXPORT_SYMBOL(phys_mem_access_prot);
 565 #endif
 566
 567 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 568
 569 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 570 {
 571         void *ptr = __va(memblock_alloc(sz, align));
 572         memset(ptr, 0, sz);
 573         return ptr;
 574 }
 575
 576 static void __init *early_alloc(unsigned long sz)
 577 {
 578         return early_alloc_aligned(sz, sz);
 579 }
 580
 581 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 582 {
 583         if (pmd_none(*pmd)) {
 584                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 585                 __pmd_populate(pmd, __pa(pte), prot);
 586         }
 587         BUG_ON(pmd_bad(*pmd));
 588         return pte_offset_kernel(pmd, addr);
 589 }
 590
 591 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 592                                   unsigned long end, unsigned long pfn,
 593                                   const struct mem_type *type)
 594 {
 595         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 596         do {
 597                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 598                 pfn++;
 599         } while (pte++, addr += PAGE_SIZE, addr != end);
 600 }
 601
 602 static void __init map_init_section(pmd_t *pmd, unsigned long addr,
 603                         unsigned long end, phys_addr_t phys,
 604                         const struct mem_type *type)
 605 {
 606 #ifndef CONFIG_ARM_LPAE
 607         /*
 608          * In classic MMU format, puds and pmds are folded in to
 609          * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
 610          * group of L1 entries making up one logical pointer to
 611          * an L2 table (2MB), where as PMDs refer to the individual
 612          * L1 entries (1MB). Hence increment to get the correct
 613          * offset for odd 1MB sections.
 614          * (See arch/arm/include/asm/pgtable-2level.h)
 615          */
 616         if (addr & SECTION_SIZE)
 617                 pmd++;
 618 #endif
 619         do {
 620                 *pmd = __pmd(phys | type->prot_sect);
 621                 phys += SECTION_SIZE;
 622         } while (pmd++, addr += SECTION_SIZE, addr != end);
 623
 624         flush_pmd_entry(pmd);
 625 }
 626
 627 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 628                                       unsigned long end, phys_addr_t phys,
 629                                       const struct mem_type *type)
 630 {
 631         pmd_t *pmd = pmd_offset(pud, addr);
 632         unsigned long next;
 633
 634         do {
 635                 /*
 636                  * With LPAE, we must loop over to map
 637                  * all the pmds for the given range.
 638                  */
 639                 next = pmd_addr_end(addr, end);
 640
 641                 /*
 642                  * Try a section mapping - addr, next and phys must all be
 643                  * aligned to a section boundary.
 644                  */
 645                 if (type->prot_sect &&
 646                                 ((addr | next | phys) & ~SECTION_MASK) == 0) {
 647                         map_init_section(pmd, addr, next, phys, type);
 648                 } else {
 649                         alloc_init_pte(pmd, addr, next,
 650                                                 __phys_to_pfn(phys), type);
 651                 }
 652
 653                 phys += next - addr;
 654
 655         } while (pmd++, addr = next, addr != end);
 656 }
 657
 658 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 659         unsigned long end, unsigned long phys, const struct mem_type *type)
 660 {
 661         pud_t *pud = pud_offset(pgd, addr);
 662         unsigned long next;
 663
 664         do {
 665                 next = pud_addr_end(addr, end);
 666                 alloc_init_pmd(pud, addr, next, phys, type);
 667                 phys += next - addr;
 668         } while (pud++, addr = next, addr != end);
 669 }
 670
 671 #ifndef CONFIG_ARM_LPAE
 672 static void __init create_36bit_mapping(struct map_desc *md,
 673                                         const struct mem_type *type)
 674 {
 675         unsigned long addr, length, end;
 676         phys_addr_t phys;
 677         pgd_t *pgd;
 678
 679         addr = md->virtual;
 680         phys = __pfn_to_phys(md->pfn);
 681         length = PAGE_ALIGN(md->length);
 682
 683         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 684                 printk(KERN_ERR "MM: CPU does not support supersection "
 685                        "mapping for 0x%08llx at 0x%08lx\n",
 686                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 687                 return;
 688         }
 689
 690         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 691          *      Since domain assignments can in fact be arbitrary, the
 692          *      'domain == 0' check below is required to insure that ARMv6
 693          *      supersections are only allocated for domain 0 regardless
 694          *      of the actual domain assignments in use.
 695          */
 696         if (type->domain) {
 697                 printk(KERN_ERR "MM: invalid domain in supersection "
 698                        "mapping for 0x%08llx at 0x%08lx\n",
 699                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 700                 return;
 701         }
 702
 703         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 704                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 705                        " at 0x%08lx invalid alignment\n",
 706                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 707                 return;
 708         }
 709
 710         /*
 711          * Shift bits [35:32] of address into bits [23:20] of PMD
 712          * (See ARMv6 spec).
 713          */
 714         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 715
 716         pgd = pgd_offset_k(addr);
 717         end = addr + length;
 718         do {
 719                 pud_t *pud = pud_offset(pgd, addr);
 720                 pmd_t *pmd = pmd_offset(pud, addr);
 721                 int i;
 722
 723                 for (i = 0; i < 16; i++)
 724                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 725
 726                 addr += SUPERSECTION_SIZE;
 727                 phys += SUPERSECTION_SIZE;
 728                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 729         } while (addr != end);
 730 }
 731 #endif  /* !CONFIG_ARM_LPAE */
 732
 733 /*
 734  * Create the page directory entries and any necessary
 735  * page tables for the mapping specified by `md'.  We
 736  * are able to cope here with varying sizes and address
 737  * offsets, and we take full advantage of sections and
 738  * supersections.
 739  */
 740 static void __init create_mapping(struct map_desc *md)
 741 {
 742         unsigned long addr, length, end;
 743         phys_addr_t phys;
 744         const struct mem_type *type;
 745         pgd_t *pgd;
 746
 747         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 748                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 749                        " at 0x%08lx in user region\n",
 750                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 751                 return;
 752         }
 753
 754         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 755             md->virtual >= PAGE_OFFSET &&
 756             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 757                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 758                        " at 0x%08lx out of vmalloc space\n",
 759                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 760         }
 761
 762         type = &mem_types[md->type];
 763
 764 #ifndef CONFIG_ARM_LPAE
 765         /*
 766          * Catch 36-bit addresses
 767          */
 768         if (md->pfn >= 0x100000) {
 769                 create_36bit_mapping(md, type);
 770                 return;
 771         }
 772 #endif
 773
 774         addr = md->virtual & PAGE_MASK;
 775         phys = __pfn_to_phys(md->pfn);
 776         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 777
 778         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 779                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 780                        "be mapped using pages, ignoring.\n",
 781                        (long long)__pfn_to_phys(md->pfn), addr);
 782                 return;
 783         }
 784
 785         pgd = pgd_offset_k(addr);
 786         end = addr + length;
 787         do {
 788                 unsigned long next = pgd_addr_end(addr, end);
 789
 790                 alloc_init_pud(pgd, addr, next, phys, type);
 791
 792                 phys += next - addr;
 793                 addr = next;
 794         } while (pgd++, addr != end);
 795 }
 796
 797 /*
 798  * Create the architecture specific mappings
 799  */
 800 void __init iotable_init(struct map_desc *io_desc, int nr)
 801 {
 802         struct map_desc *md;
 803         struct vm_struct *vm;
 804         struct static_vm *svm;
 805
 806         if (!nr)
 807                 return;
 808
 809         svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
 810
 811         for (md = io_desc; nr; md++, nr--) {
 812                 create_mapping(md);
 813
 814                 vm = &svm->vm;
 815                 vm->addr = (void *)(md->virtual & PAGE_MASK);
 816                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 817                 vm->phys_addr = __pfn_to_phys(md->pfn);
 818                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 819                 vm->flags |= VM_ARM_MTYPE(md->type);
 820                 vm->caller = iotable_init;
 821                 add_static_vm_early(svm++);
 822         }
 823 }
 824
 825 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
 826                                   void *caller)
 827 {
 828         struct vm_struct *vm;
 829         struct static_vm *svm;
 830
 831         svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
 832
 833         vm = &svm->vm;
 834         vm->addr = (void *)addr;
 835         vm->size = size;
 836         vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
 837         vm->caller = caller;
 838         add_static_vm_early(svm);
 839 }
 840
 841 #ifndef CONFIG_ARM_LPAE
 842
 843 /*
 844  * The Linux PMD is made of two consecutive section entries covering 2MB
 845  * (see definition in include/asm/pgtable-2level.h).  However a call to
 846  * create_mapping() may optimize static mappings by using individual
 847  * 1MB section mappings.  This leaves the actual PMD potentially half
 848  * initialized if the top or bottom section entry isn't used, leaving it
 849  * open to problems if a subsequent ioremap() or vmalloc() tries to use
 850  * the virtual space left free by that unused section entry.
 851  *
 852  * Let's avoid the issue by inserting dummy vm entries covering the unused
 853  * PMD halves once the static mappings are in place.
 854  */
 855
 856 static void __init pmd_empty_section_gap(unsigned long addr)
 857 {
 858         vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 859 }
 860
 861 static void __init fill_pmd_gaps(void)
 862 {
 863         struct static_vm *svm;
 864         struct vm_struct *vm;
 865         unsigned long addr, next = 0;
 866         pmd_t *pmd;
 867
 868         list_for_each_entry(svm, &static_vmlist, list) {
 869                 vm = &svm->vm;
 870                 addr = (unsigned long)vm->addr;
 871                 if (addr < next)
 872                         continue;
 873
 874                 /*
 875                  * Check if this vm starts on an odd section boundary.
 876                  * If so and the first section entry for this PMD is free
 877                  * then we block the corresponding virtual address.
 878                  */
 879                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 880                         pmd = pmd_off_k(addr);
 881                         if (pmd_none(*pmd))
 882                                 pmd_empty_section_gap(addr & PMD_MASK);
 883                 }
 884
 885                 /*
 886                  * Then check if this vm ends on an odd section boundary.
 887                  * If so and the second section entry for this PMD is empty
 888                  * then we block the corresponding virtual address.
 889                  */
 890                 addr += vm->size;
 891                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 892                         pmd = pmd_off_k(addr) + 1;
 893                         if (pmd_none(*pmd))
 894                                 pmd_empty_section_gap(addr);
 895                 }
 896
 897                 /* no need to look at any vm entry until we hit the next PMD */
 898                 next = (addr + PMD_SIZE - 1) & PMD_MASK;
 899         }
 900 }
 901
 902 #else
 903 #define fill_pmd_gaps() do { } while (0)
 904 #endif
 905
 906 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 907 static void __init pci_reserve_io(void)
 908 {
 909         struct static_vm *svm;
 910
 911         svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
 912         if (svm)
 913                 return;
 914
 915         vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 916 }
 917 #else
 918 #define pci_reserve_io() do { } while (0)
 919 #endif
 920
 921 #ifdef CONFIG_DEBUG_LL
 922 void __init debug_ll_io_init(void)
 923 {
 924         struct map_desc map;
 925
 926         debug_ll_addr(&map.pfn, &map.virtual);
 927         if (!map.pfn || !map.virtual)
 928                 return;
 929         map.pfn = __phys_to_pfn(map.pfn);
 930         map.virtual &= PAGE_MASK;
 931         map.length = PAGE_SIZE;
 932         map.type = MT_DEVICE;
 933         create_mapping(&map);
 934 }
 935 #endif
 936
 937 static void * __initdata vmalloc_min =
 938         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 939
 940 /*
 941  * vmalloc=size forces the vmalloc area to be exactly 'size'
 942  * bytes. This can be used to increase (or decrease) the vmalloc
 943  * area - the default is 240m.
 944  */
 945 static int __init early_vmalloc(char *arg)
 946 {
 947         unsigned long vmalloc_reserve = memparse(arg, NULL);
 948
 949         if (vmalloc_reserve < SZ_16M) {
 950                 vmalloc_reserve = SZ_16M;
 951                 printk(KERN_WARNING
 952                         "vmalloc area too small, limiting to %luMB\n",
 953                         vmalloc_reserve >> 20);
 954         }
 955
 956         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 957                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 958                 printk(KERN_WARNING
 959                         "vmalloc area is too big, limiting to %luMB\n",
 960                         vmalloc_reserve >> 20);
 961         }
 962
 963         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 964         return 0;
 965 }
 966 early_param("vmalloc", early_vmalloc);
 967
 968 phys_addr_t arm_lowmem_limit __initdata = 0;
 969
 970 void __init sanity_check_meminfo(void)
 971 {
 972         int i, j, highmem = 0;
 973
 974         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 975                 struct membank *bank = &meminfo.bank[j];
 976                 *bank = meminfo.bank[i];
 977
 978                 if (bank->start > ULONG_MAX)
 979                         highmem = 1;
 980
 981 #ifdef CONFIG_HIGHMEM
 982                 if (__va(bank->start) >= vmalloc_min ||
 983                     __va(bank->start) < (void *)PAGE_OFFSET)
 984                         highmem = 1;
 985
 986                 bank->highmem = highmem;
 987
 988                 /*
 989                  * Split those memory banks which are partially overlapping
 990                  * the vmalloc area greatly simplifying things later.
 991                  */
 992                 if (!highmem && __va(bank->start) < vmalloc_min &&
 993                     bank->size > vmalloc_min - __va(bank->start)) {
 994                         if (meminfo.nr_banks >= NR_BANKS) {
 995                                 printk(KERN_CRIT "NR_BANKS too low, "
 996                                                  "ignoring high memory\n");
 997                         } else {
 998                                 memmove(bank + 1, bank,
 999                                         (meminfo.nr_banks - i) * sizeof(*bank));
1000                                 meminfo.nr_banks++;
1001                                 i++;
1002                                 bank[1].size -= vmalloc_min - __va(bank->start);
1003                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
1004                                 bank[1].highmem = highmem = 1;
1005                                 j++;
1006                         }
1007                         bank->size = vmalloc_min - __va(bank->start);
1008                 }
1009 #else
1010                 bank->highmem = highmem;
1011
1012                 /*
1013                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
1014                  */
1015                 if (highmem) {
1016                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1017                                "(!CONFIG_HIGHMEM).\n",
1018                                (unsigned long long)bank->start,
1019                                (unsigned long long)bank->start + bank->size - 1);
1020                         continue;
1021                 }
1022
1023                 /*
1024                  * Check whether this memory bank would entirely overlap
1025                  * the vmalloc area.
1026                  */
1027                 if (__va(bank->start) >= vmalloc_min ||
1028                     __va(bank->start) < (void *)PAGE_OFFSET) {
1029                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1030                                "(vmalloc region overlap).\n",
1031                                (unsigned long long)bank->start,
1032                                (unsigned long long)bank->start + bank->size - 1);
1033                         continue;
1034                 }
1035
1036                 /*
1037                  * Check whether this memory bank would partially overlap
1038                  * the vmalloc area.
1039                  */
1040                 if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
1041                     __va(bank->start + bank->size - 1) <= __va(bank->start)) {
1042                         unsigned long newsize = vmalloc_min - __va(bank->start);
1043                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1044                                "to -%.8llx (vmalloc region overlap).\n",
1045                                (unsigned long long)bank->start,
1046                                (unsigned long long)bank->start + bank->size - 1,
1047                                (unsigned long long)bank->start + newsize - 1);
1048                         bank->size = newsize;
1049                 }
1050 #endif
1051                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1052                         arm_lowmem_limit = bank->start + bank->size;
1053
1054                 j++;
1055         }
1056 #ifdef CONFIG_HIGHMEM
1057         if (highmem) {
1058                 const char *reason = NULL;
1059
1060                 if (cache_is_vipt_aliasing()) {
1061                         /*
1062                          * Interactions between kmap and other mappings
1063                          * make highmem support with aliasing VIPT caches
1064                          * rather difficult.
1065                          */
1066                         reason = "with VIPT aliasing cache";
1067                 }
1068                 if (reason) {
1069                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1070                                 reason);
1071                         while (j > 0 && meminfo.bank[j - 1].highmem)
1072                                 j--;
1073                 }
1074         }
1075 #endif
1076         meminfo.nr_banks = j;
1077         high_memory = __va(arm_lowmem_limit - 1) + 1;
1078         memblock_set_current_limit(arm_lowmem_limit);
1079 }
1080
1081 static inline void prepare_page_table(void)
1082 {
1083         unsigned long addr;
1084         phys_addr_t end;
1085
1086         /*
1087          * Clear out all the mappings below the kernel image.
1088          */
1089         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1090                 pmd_clear(pmd_off_k(addr));
1091
1092 #ifdef CONFIG_XIP_KERNEL
1093         /* The XIP kernel is mapped in the module area -- skip over it */
1094         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1095 #endif
1096         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1097                 pmd_clear(pmd_off_k(addr));
1098
1099         /*
1100          * Find the end of the first block of lowmem.
1101          */
1102         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1103         if (end >= arm_lowmem_limit)
1104                 end = arm_lowmem_limit;
1105
1106         /*
1107          * Clear out all the kernel space mappings, except for the first
1108          * memory bank, up to the vmalloc region.
1109          */
1110         for (addr = __phys_to_virt(end);
1111              addr < VMALLOC_START; addr += PMD_SIZE)
1112                 pmd_clear(pmd_off_k(addr));
1113 }
1114
1115 #ifdef CONFIG_ARM_LPAE
1116 /* the first page is reserved for pgd */
1117 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1118                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1119 #else
1120 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1121 #endif
1122
1123 /*
1124  * Reserve the special regions of memory
1125  */
1126 void __init arm_mm_memblock_reserve(void)
1127 {
1128         /*
1129          * Reserve the page tables.  These are already in use,
1130          * and can only be in node 0.
1131          */
1132         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1133
1134 #ifdef CONFIG_SA1111
1135         /*
1136          * Because of the SA1111 DMA bug, we want to preserve our
1137          * precious DMA-able memory...
1138          */
1139         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1140 #endif
1141 }
1142
1143 /*
1144  * Set up the device mappings.  Since we clear out the page tables for all
1145  * mappings above VMALLOC_START, we will remove any debug device mappings.
1146  * This means you have to be careful how you debug this function, or any
1147  * called function.  This means you can't use any function or debugging
1148  * method which may touch any device, otherwise the kernel _will_ crash.
1149  */
1150 static void __init devicemaps_init(struct machine_desc *mdesc)
1151 {
1152         struct map_desc map;
1153         unsigned long addr;
1154         void *vectors;
1155
1156         /*
1157          * Allocate the vector page early.
1158          */
1159         vectors = early_alloc(PAGE_SIZE);
1160
1161         early_trap_init(vectors);
1162
1163         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1164                 pmd_clear(pmd_off_k(addr));
1165
1166         /*
1167          * Map the kernel if it is XIP.
1168          * It is always first in the modulearea.
1169          */
1170 #ifdef CONFIG_XIP_KERNEL
1171         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1172         map.virtual = MODULES_VADDR;
1173         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1174         map.type = MT_ROM;
1175         create_mapping(&map);
1176 #endif
1177
1178         /*
1179          * Map the cache flushing regions.
1180          */
1181 #ifdef FLUSH_BASE
1182         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1183         map.virtual = FLUSH_BASE;
1184         map.length = SZ_1M;
1185         map.type = MT_CACHECLEAN;
1186         create_mapping(&map);
1187 #endif
1188 #ifdef FLUSH_BASE_MINICACHE
1189         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1190         map.virtual = FLUSH_BASE_MINICACHE;
1191         map.length = SZ_1M;
1192         map.type = MT_MINICLEAN;
1193         create_mapping(&map);
1194 #endif
1195
1196         /*
1197          * Create a mapping for the machine vectors at the high-vectors
1198          * location (0xffff0000).  If we aren't using high-vectors, also
1199          * create a mapping at the low-vectors virtual address.
1200          */
1201         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1202         map.virtual = 0xffff0000;
1203         map.length = PAGE_SIZE;
1204         map.type = MT_HIGH_VECTORS;
1205         create_mapping(&map);
1206
1207         if (!vectors_high()) {
1208                 map.virtual = 0;
1209                 map.type = MT_LOW_VECTORS;
1210                 create_mapping(&map);
1211         }
1212
1213         /*
1214          * Ask the machine support to map in the statically mapped devices.
1215          */
1216         if (mdesc->map_io)
1217                 mdesc->map_io();
1218         fill_pmd_gaps();
1219
1220         /* Reserve fixed i/o space in VMALLOC region */
1221         pci_reserve_io();
1222
1223         /*
1224          * Finally flush the caches and tlb to ensure that we're in a
1225          * consistent state wrt the writebuffer.  This also ensures that
1226          * any write-allocated cache lines in the vector page are written
1227          * back.  After this point, we can start to touch devices again.
1228          */
1229         local_flush_tlb_all();
1230         flush_cache_all();
1231 }
1232
1233 static void __init kmap_init(void)
1234 {
1235 #ifdef CONFIG_HIGHMEM
1236         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1237                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1238 #endif
1239 }
1240
1241 static void __init map_lowmem(void)
1242 {
1243         struct memblock_region *reg;
1244
1245         /* Map all the lowmem memory banks. */
1246         for_each_memblock(memory, reg) {
1247                 phys_addr_t start = reg->base;
1248                 phys_addr_t end = start + reg->size;
1249                 struct map_desc map;
1250
1251                 if (end > arm_lowmem_limit)
1252                         end = arm_lowmem_limit;
1253                 if (start >= end)
1254                         break;
1255
1256                 map.pfn = __phys_to_pfn(start);
1257                 map.virtual = __phys_to_virt(start);
1258                 map.length = end - start;
1259                 map.type = MT_MEMORY;
1260
1261                 create_mapping(&map);
1262         }
1263 }
1264
1265 /*
1266  * paging_init() sets up the page tables, initialises the zone memory
1267  * maps, and sets up the zero page, bad page and bad page tables.
1268  */
1269 void __init paging_init(struct machine_desc *mdesc)
1270 {
1271         void *zero_page;
1272
1273         memblock_set_current_limit(arm_lowmem_limit);
1274
1275         build_mem_type_table();
1276         prepare_page_table();
1277         map_lowmem();
1278         dma_contiguous_remap();
1279         devicemaps_init(mdesc);
1280         kmap_init();
1281         tcm_init();
1282
1283         top_pmd = pmd_off_k(0xffff0000);
1284
1285         /* allocate the zero page. */
1286         zero_page = early_alloc(PAGE_SIZE);
1287
1288         bootmem_init();
1289
1290         empty_zero_page = virt_to_page(zero_page);
1291         __flush_dcache_page(NULL, empty_zero_page);
1292 }