2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/fixmap.h>
26 #include <asm/sections.h>
27 #include <asm/setup.h>
28 #include <asm/smp_plat.h>
30 #include <asm/highmem.h>
31 #include <asm/system_info.h>
32 #include <asm/traps.h>
33 #include <asm/procinfo.h>
34 #include <asm/memory.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/pci.h>
39 #include <asm/fixmap.h>
45 * empty_zero_page is a special page that is used for
46 * zero-initialized data and COW.
48 struct page *empty_zero_page;
49 EXPORT_SYMBOL(empty_zero_page);
52 * The pmd table for the upper-most set of pages.
56 #define CPOLICY_UNCACHED 0
57 #define CPOLICY_BUFFERED 1
58 #define CPOLICY_WRITETHROUGH 2
59 #define CPOLICY_WRITEBACK 3
60 #define CPOLICY_WRITEALLOC 4
62 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
63 static unsigned int ecc_mask __initdata = 0;
65 pgprot_t pgprot_kernel;
66 pgprot_t pgprot_hyp_device;
68 pgprot_t pgprot_s2_device;
70 EXPORT_SYMBOL(pgprot_user);
71 EXPORT_SYMBOL(pgprot_kernel);
74 const char policy[16];
81 #ifdef CONFIG_ARM_LPAE
82 #define s2_policy(policy) policy
84 #define s2_policy(policy) 0
87 static struct cachepolicy cache_policies[] __initdata = {
91 .pmd = PMD_SECT_UNCACHED,
92 .pte = L_PTE_MT_UNCACHED,
93 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
97 .pmd = PMD_SECT_BUFFERED,
98 .pte = L_PTE_MT_BUFFERABLE,
99 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
101 .policy = "writethrough",
104 .pte = L_PTE_MT_WRITETHROUGH,
105 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
107 .policy = "writeback",
110 .pte = L_PTE_MT_WRITEBACK,
111 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
113 .policy = "writealloc",
115 .pmd = PMD_SECT_WBWA,
116 .pte = L_PTE_MT_WRITEALLOC,
117 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
121 #ifdef CONFIG_CPU_CP15
122 static unsigned long initial_pmd_value __initdata = 0;
125 * Initialise the cache_policy variable with the initial state specified
126 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
127 * the C code sets the page tables up with the same policy as the head
128 * assembly code, which avoids an illegal state where the TLBs can get
129 * confused. See comments in early_cachepolicy() for more information.
131 void __init init_default_cache_policy(unsigned long pmd)
135 initial_pmd_value = pmd;
137 pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE;
139 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
140 if (cache_policies[i].pmd == pmd) {
145 if (i == ARRAY_SIZE(cache_policies))
146 pr_err("ERROR: could not find cache policy\n");
150 * These are useful for identifying cache coherency problems by allowing
151 * the cache or the cache and writebuffer to be turned off. (Note: the
152 * write buffer should not be on and the cache off).
154 static int __init early_cachepolicy(char *p)
156 int i, selected = -1;
158 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
159 int len = strlen(cache_policies[i].policy);
161 if (memcmp(p, cache_policies[i].policy, len) == 0) {
168 pr_err("ERROR: unknown or unsupported cache policy\n");
171 * This restriction is partly to do with the way we boot; it is
172 * unpredictable to have memory mapped using two different sets of
173 * memory attributes (shared, type, and cache attribs). We can not
174 * change these attributes once the initial assembly has setup the
177 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
178 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
179 cache_policies[cachepolicy].policy);
183 if (selected != cachepolicy) {
184 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
185 cachepolicy = selected;
191 early_param("cachepolicy", early_cachepolicy);
193 static int __init early_nocache(char *__unused)
195 char *p = "buffered";
196 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
197 early_cachepolicy(p);
200 early_param("nocache", early_nocache);
202 static int __init early_nowrite(char *__unused)
204 char *p = "uncached";
205 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
206 early_cachepolicy(p);
209 early_param("nowb", early_nowrite);
211 #ifndef CONFIG_ARM_LPAE
212 static int __init early_ecc(char *p)
214 if (memcmp(p, "on", 2) == 0)
215 ecc_mask = PMD_PROTECTION;
216 else if (memcmp(p, "off", 3) == 0)
220 early_param("ecc", early_ecc);
223 #else /* ifdef CONFIG_CPU_CP15 */
225 static int __init early_cachepolicy(char *p)
227 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
229 early_param("cachepolicy", early_cachepolicy);
231 static int __init noalign_setup(char *__unused)
233 pr_warning("noalign kernel parameter not supported without cp15\n");
235 __setup("noalign", noalign_setup);
237 #endif /* ifdef CONFIG_CPU_CP15 / else */
239 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
240 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
241 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
243 static struct mem_type mem_types[] = {
244 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
245 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
247 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
248 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
250 .prot_l1 = PMD_TYPE_TABLE,
251 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
254 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
255 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
256 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PROT_SECT_DEVICE,
260 [MT_DEVICE_CACHED] = { /* ioremap_cached */
261 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
262 .prot_l1 = PMD_TYPE_TABLE,
263 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
266 [MT_DEVICE_WC] = { /* ioremap_wc */
267 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
268 .prot_l1 = PMD_TYPE_TABLE,
269 .prot_sect = PROT_SECT_DEVICE,
273 .prot_pte = PROT_PTE_DEVICE,
274 .prot_l1 = PMD_TYPE_TABLE,
275 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
279 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
280 .domain = DOMAIN_KERNEL,
282 #ifndef CONFIG_ARM_LPAE
284 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
285 .domain = DOMAIN_KERNEL,
289 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
291 .prot_l1 = PMD_TYPE_TABLE,
292 .domain = DOMAIN_USER,
294 [MT_HIGH_VECTORS] = {
295 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
296 L_PTE_USER | L_PTE_RDONLY,
297 .prot_l1 = PMD_TYPE_TABLE,
298 .domain = DOMAIN_USER,
301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
302 .prot_l1 = PMD_TYPE_TABLE,
303 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
304 .domain = DOMAIN_KERNEL,
307 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
309 .prot_l1 = PMD_TYPE_TABLE,
310 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
311 .domain = DOMAIN_KERNEL,
314 .prot_sect = PMD_TYPE_SECT,
315 .domain = DOMAIN_KERNEL,
317 [MT_MEMORY_RWX_NONCACHED] = {
318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
320 .prot_l1 = PMD_TYPE_TABLE,
321 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
322 .domain = DOMAIN_KERNEL,
324 [MT_MEMORY_RW_DTCM] = {
325 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
327 .prot_l1 = PMD_TYPE_TABLE,
328 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
329 .domain = DOMAIN_KERNEL,
331 [MT_MEMORY_RWX_ITCM] = {
332 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
333 .prot_l1 = PMD_TYPE_TABLE,
334 .domain = DOMAIN_KERNEL,
336 [MT_MEMORY_RW_SO] = {
337 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
338 L_PTE_MT_UNCACHED | L_PTE_XN,
339 .prot_l1 = PMD_TYPE_TABLE,
340 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
341 PMD_SECT_UNCACHED | PMD_SECT_XN,
342 .domain = DOMAIN_KERNEL,
344 [MT_MEMORY_DMA_READY] = {
345 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
347 .prot_l1 = PMD_TYPE_TABLE,
348 .domain = DOMAIN_KERNEL,
352 const struct mem_type *get_mem_type(unsigned int type)
354 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
356 EXPORT_SYMBOL(get_mem_type);
358 #define PTE_SET_FN(_name, pteop) \
359 static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \
362 pte_t pte = pteop(*ptep); \
364 set_pte_ext(ptep, pte, 0); \
368 #define SET_MEMORY_FN(_name, callback) \
369 int set_memory_##_name(unsigned long addr, int numpages) \
371 unsigned long start = addr; \
372 unsigned long size = PAGE_SIZE*numpages; \
373 unsigned end = start + size; \
375 if (start < MODULES_VADDR || start >= MODULES_END) \
378 if (end < MODULES_VADDR || end >= MODULES_END) \
381 apply_to_page_range(&init_mm, start, size, callback, NULL); \
382 flush_tlb_kernel_range(start, end); \
386 PTE_SET_FN(ro, pte_wrprotect)
387 PTE_SET_FN(rw, pte_mkwrite)
388 PTE_SET_FN(x, pte_mkexec)
389 PTE_SET_FN(nx, pte_mknexec)
391 SET_MEMORY_FN(ro, pte_set_ro)
392 SET_MEMORY_FN(rw, pte_set_rw)
393 SET_MEMORY_FN(x, pte_set_x)
394 SET_MEMORY_FN(nx, pte_set_nx)
397 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
398 * As a result, this can only be called with preemption disabled, as under
401 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
403 unsigned long vaddr = __fix_to_virt(idx);
404 pte_t *pte = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
406 /* Make sure fixmap region does not exceed available allocation. */
407 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
409 BUG_ON(idx >= __end_of_fixed_addresses);
411 if (pgprot_val(prot))
412 set_pte_at(NULL, vaddr, pte,
413 pfn_pte(phys >> PAGE_SHIFT, prot));
415 pte_clear(NULL, vaddr, pte);
416 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
420 * Adjust the PMD section entries according to the CPU in use.
422 static void __init build_mem_type_table(void)
424 struct cachepolicy *cp;
425 unsigned int cr = get_cr();
426 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
427 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
428 int cpu_arch = cpu_architecture();
431 if (cpu_arch < CPU_ARCH_ARMv6) {
432 #if defined(CONFIG_CPU_DCACHE_DISABLE)
433 if (cachepolicy > CPOLICY_BUFFERED)
434 cachepolicy = CPOLICY_BUFFERED;
435 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
436 if (cachepolicy > CPOLICY_WRITETHROUGH)
437 cachepolicy = CPOLICY_WRITETHROUGH;
440 if (cpu_arch < CPU_ARCH_ARMv5) {
441 if (cachepolicy >= CPOLICY_WRITEALLOC)
442 cachepolicy = CPOLICY_WRITEBACK;
447 if (cachepolicy != CPOLICY_WRITEALLOC) {
448 pr_warn("Forcing write-allocate cache policy for SMP\n");
449 cachepolicy = CPOLICY_WRITEALLOC;
451 if (!(initial_pmd_value & PMD_SECT_S)) {
452 pr_warn("Forcing shared mappings for SMP\n");
453 initial_pmd_value |= PMD_SECT_S;
458 * Strip out features not present on earlier architectures.
459 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
460 * without extended page tables don't have the 'Shared' bit.
462 if (cpu_arch < CPU_ARCH_ARMv5)
463 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
464 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
465 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
466 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
467 mem_types[i].prot_sect &= ~PMD_SECT_S;
470 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
471 * "update-able on write" bit on ARM610). However, Xscale and
472 * Xscale3 require this bit to be cleared.
474 if (cpu_is_xscale() || cpu_is_xsc3()) {
475 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
476 mem_types[i].prot_sect &= ~PMD_BIT4;
477 mem_types[i].prot_l1 &= ~PMD_BIT4;
479 } else if (cpu_arch < CPU_ARCH_ARMv6) {
480 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
481 if (mem_types[i].prot_l1)
482 mem_types[i].prot_l1 |= PMD_BIT4;
483 if (mem_types[i].prot_sect)
484 mem_types[i].prot_sect |= PMD_BIT4;
489 * Mark the device areas according to the CPU/architecture.
491 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
492 if (!cpu_is_xsc3()) {
494 * Mark device regions on ARMv6+ as execute-never
495 * to prevent speculative instruction fetches.
497 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
498 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
499 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
500 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
502 /* Also setup NX memory mapping */
503 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
505 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
507 * For ARMv7 with TEX remapping,
508 * - shared device is SXCB=1100
509 * - nonshared device is SXCB=0100
510 * - write combine device mem is SXCB=0001
511 * (Uncached Normal memory)
513 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
514 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
515 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
516 } else if (cpu_is_xsc3()) {
519 * - shared device is TEXCB=00101
520 * - nonshared device is TEXCB=01000
521 * - write combine device mem is TEXCB=00100
522 * (Inner/Outer Uncacheable in xsc3 parlance)
524 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
525 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
526 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
529 * For ARMv6 and ARMv7 without TEX remapping,
530 * - shared device is TEXCB=00001
531 * - nonshared device is TEXCB=01000
532 * - write combine device mem is TEXCB=00100
533 * (Uncached Normal in ARMv6 parlance).
535 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
536 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
537 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
541 * On others, write combining is "Uncached/Buffered"
543 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
547 * Now deal with the memory-type mappings
549 cp = &cache_policies[cachepolicy];
550 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
551 s2_pgprot = cp->pte_s2;
552 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
553 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
556 * We don't use domains on ARMv6 (since this causes problems with
557 * v6/v7 kernels), so we must use a separate memory type for user
558 * r/o, kernel r/w to map the vectors page.
560 #ifndef CONFIG_ARM_LPAE
561 if (cpu_arch == CPU_ARCH_ARMv6)
562 vecs_pgprot |= L_PTE_MT_VECTORS;
566 * ARMv6 and above have extended page tables.
568 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
569 #ifndef CONFIG_ARM_LPAE
571 * Mark cache clean areas and XIP ROM read only
572 * from SVC mode and no access from userspace.
574 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
575 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
576 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
580 * If the initial page tables were created with the S bit
581 * set, then we need to do the same here for the same
582 * reasons given in early_cachepolicy().
584 if (initial_pmd_value & PMD_SECT_S) {
585 user_pgprot |= L_PTE_SHARED;
586 kern_pgprot |= L_PTE_SHARED;
587 vecs_pgprot |= L_PTE_SHARED;
588 s2_pgprot |= L_PTE_SHARED;
589 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
590 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
591 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
592 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
593 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
594 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
595 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
596 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
597 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
598 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
599 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
604 * Non-cacheable Normal - intended for memory areas that must
605 * not cause dirty cache line writebacks when used
607 if (cpu_arch >= CPU_ARCH_ARMv6) {
608 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
609 /* Non-cacheable Normal is XCB = 001 */
610 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
613 /* For both ARMv6 and non-TEX-remapping ARMv7 */
614 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
618 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
621 #ifdef CONFIG_ARM_LPAE
623 * Do not generate access flag faults for the kernel mappings.
625 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
626 mem_types[i].prot_pte |= PTE_EXT_AF;
627 if (mem_types[i].prot_sect)
628 mem_types[i].prot_sect |= PMD_SECT_AF;
630 kern_pgprot |= PTE_EXT_AF;
631 vecs_pgprot |= PTE_EXT_AF;
634 for (i = 0; i < 16; i++) {
635 pteval_t v = pgprot_val(protection_map[i]);
636 protection_map[i] = __pgprot(v | user_pgprot);
639 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
640 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
642 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
643 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
644 L_PTE_DIRTY | kern_pgprot);
645 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
646 pgprot_s2_device = __pgprot(s2_device_pgprot);
647 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
649 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
650 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
651 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
652 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
653 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
654 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
655 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
656 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
657 mem_types[MT_ROM].prot_sect |= cp->pmd;
661 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
665 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
668 pr_info("Memory policy: %sData cache %s\n",
669 ecc_mask ? "ECC enabled, " : "", cp->policy);
671 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
672 struct mem_type *t = &mem_types[i];
674 t->prot_l1 |= PMD_DOMAIN(t->domain);
676 t->prot_sect |= PMD_DOMAIN(t->domain);
680 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
681 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
682 unsigned long size, pgprot_t vma_prot)
685 return pgprot_noncached(vma_prot);
686 else if (file->f_flags & O_SYNC)
687 return pgprot_writecombine(vma_prot);
690 EXPORT_SYMBOL(phys_mem_access_prot);
693 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
695 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
697 void *ptr = __va(memblock_alloc(sz, align));
702 static void __init *early_alloc(unsigned long sz)
704 return early_alloc_aligned(sz, sz);
707 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
709 if (pmd_none(*pmd)) {
710 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
711 __pmd_populate(pmd, __pa(pte), prot);
713 BUG_ON(pmd_bad(*pmd));
714 return pte_offset_kernel(pmd, addr);
717 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
718 unsigned long end, unsigned long pfn,
719 const struct mem_type *type)
721 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
723 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
725 } while (pte++, addr += PAGE_SIZE, addr != end);
728 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
729 unsigned long end, phys_addr_t phys,
730 const struct mem_type *type)
734 #ifndef CONFIG_ARM_LPAE
736 * In classic MMU format, puds and pmds are folded in to
737 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
738 * group of L1 entries making up one logical pointer to
739 * an L2 table (2MB), where as PMDs refer to the individual
740 * L1 entries (1MB). Hence increment to get the correct
741 * offset for odd 1MB sections.
742 * (See arch/arm/include/asm/pgtable-2level.h)
744 if (addr & SECTION_SIZE)
748 *pmd = __pmd(phys | type->prot_sect);
749 phys += SECTION_SIZE;
750 } while (pmd++, addr += SECTION_SIZE, addr != end);
755 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
756 unsigned long end, phys_addr_t phys,
757 const struct mem_type *type)
759 pmd_t *pmd = pmd_offset(pud, addr);
764 * With LPAE, we must loop over to map
765 * all the pmds for the given range.
767 next = pmd_addr_end(addr, end);
770 * Try a section mapping - addr, next and phys must all be
771 * aligned to a section boundary.
773 if (type->prot_sect &&
774 ((addr | next | phys) & ~SECTION_MASK) == 0) {
775 __map_init_section(pmd, addr, next, phys, type);
777 alloc_init_pte(pmd, addr, next,
778 __phys_to_pfn(phys), type);
783 } while (pmd++, addr = next, addr != end);
786 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
787 unsigned long end, phys_addr_t phys,
788 const struct mem_type *type)
790 pud_t *pud = pud_offset(pgd, addr);
794 next = pud_addr_end(addr, end);
795 alloc_init_pmd(pud, addr, next, phys, type);
797 } while (pud++, addr = next, addr != end);
800 #ifndef CONFIG_ARM_LPAE
801 static void __init create_36bit_mapping(struct map_desc *md,
802 const struct mem_type *type)
804 unsigned long addr, length, end;
809 phys = __pfn_to_phys(md->pfn);
810 length = PAGE_ALIGN(md->length);
812 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
813 printk(KERN_ERR "MM: CPU does not support supersection "
814 "mapping for 0x%08llx at 0x%08lx\n",
815 (long long)__pfn_to_phys((u64)md->pfn), addr);
819 /* N.B. ARMv6 supersections are only defined to work with domain 0.
820 * Since domain assignments can in fact be arbitrary, the
821 * 'domain == 0' check below is required to insure that ARMv6
822 * supersections are only allocated for domain 0 regardless
823 * of the actual domain assignments in use.
826 printk(KERN_ERR "MM: invalid domain in supersection "
827 "mapping for 0x%08llx at 0x%08lx\n",
828 (long long)__pfn_to_phys((u64)md->pfn), addr);
832 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
833 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
834 " at 0x%08lx invalid alignment\n",
835 (long long)__pfn_to_phys((u64)md->pfn), addr);
840 * Shift bits [35:32] of address into bits [23:20] of PMD
843 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
845 pgd = pgd_offset_k(addr);
848 pud_t *pud = pud_offset(pgd, addr);
849 pmd_t *pmd = pmd_offset(pud, addr);
852 for (i = 0; i < 16; i++)
853 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
855 addr += SUPERSECTION_SIZE;
856 phys += SUPERSECTION_SIZE;
857 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
858 } while (addr != end);
860 #endif /* !CONFIG_ARM_LPAE */
863 * Create the page directory entries and any necessary
864 * page tables for the mapping specified by `md'. We
865 * are able to cope here with varying sizes and address
866 * offsets, and we take full advantage of sections and
869 static void __init create_mapping(struct map_desc *md)
871 unsigned long addr, length, end;
873 const struct mem_type *type;
876 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
877 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
878 " at 0x%08lx in user region\n",
879 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
883 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
884 md->virtual >= PAGE_OFFSET &&
885 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
886 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
887 " at 0x%08lx out of vmalloc space\n",
888 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
891 type = &mem_types[md->type];
893 #ifndef CONFIG_ARM_LPAE
895 * Catch 36-bit addresses
897 if (md->pfn >= 0x100000) {
898 create_36bit_mapping(md, type);
903 addr = md->virtual & PAGE_MASK;
904 phys = __pfn_to_phys(md->pfn);
905 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
907 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
908 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
909 "be mapped using pages, ignoring.\n",
910 (long long)__pfn_to_phys(md->pfn), addr);
914 pgd = pgd_offset_k(addr);
917 unsigned long next = pgd_addr_end(addr, end);
919 alloc_init_pud(pgd, addr, next, phys, type);
923 } while (pgd++, addr != end);
927 * Create the architecture specific mappings
929 void __init iotable_init(struct map_desc *io_desc, int nr)
932 struct vm_struct *vm;
933 struct static_vm *svm;
938 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
940 for (md = io_desc; nr; md++, nr--) {
944 vm->addr = (void *)(md->virtual & PAGE_MASK);
945 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
946 vm->phys_addr = __pfn_to_phys(md->pfn);
947 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
948 vm->flags |= VM_ARM_MTYPE(md->type);
949 vm->caller = iotable_init;
950 add_static_vm_early(svm++);
954 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
957 struct vm_struct *vm;
958 struct static_vm *svm;
960 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
963 vm->addr = (void *)addr;
965 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
967 add_static_vm_early(svm);
970 #ifndef CONFIG_ARM_LPAE
973 * The Linux PMD is made of two consecutive section entries covering 2MB
974 * (see definition in include/asm/pgtable-2level.h). However a call to
975 * create_mapping() may optimize static mappings by using individual
976 * 1MB section mappings. This leaves the actual PMD potentially half
977 * initialized if the top or bottom section entry isn't used, leaving it
978 * open to problems if a subsequent ioremap() or vmalloc() tries to use
979 * the virtual space left free by that unused section entry.
981 * Let's avoid the issue by inserting dummy vm entries covering the unused
982 * PMD halves once the static mappings are in place.
985 static void __init pmd_empty_section_gap(unsigned long addr)
987 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
990 static void __init fill_pmd_gaps(void)
992 struct static_vm *svm;
993 struct vm_struct *vm;
994 unsigned long addr, next = 0;
997 list_for_each_entry(svm, &static_vmlist, list) {
999 addr = (unsigned long)vm->addr;
1004 * Check if this vm starts on an odd section boundary.
1005 * If so and the first section entry for this PMD is free
1006 * then we block the corresponding virtual address.
1008 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1009 pmd = pmd_off_k(addr);
1011 pmd_empty_section_gap(addr & PMD_MASK);
1015 * Then check if this vm ends on an odd section boundary.
1016 * If so and the second section entry for this PMD is empty
1017 * then we block the corresponding virtual address.
1020 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1021 pmd = pmd_off_k(addr) + 1;
1023 pmd_empty_section_gap(addr);
1026 /* no need to look at any vm entry until we hit the next PMD */
1027 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1032 #define fill_pmd_gaps() do { } while (0)
1035 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1036 static void __init pci_reserve_io(void)
1038 struct static_vm *svm;
1040 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1044 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1047 #define pci_reserve_io() do { } while (0)
1050 #ifdef CONFIG_DEBUG_LL
1051 void __init debug_ll_io_init(void)
1053 struct map_desc map;
1055 debug_ll_addr(&map.pfn, &map.virtual);
1056 if (!map.pfn || !map.virtual)
1058 map.pfn = __phys_to_pfn(map.pfn);
1059 map.virtual &= PAGE_MASK;
1060 map.length = PAGE_SIZE;
1061 map.type = MT_DEVICE;
1062 iotable_init(&map, 1);
1066 static void * __initdata vmalloc_min =
1067 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1070 * vmalloc=size forces the vmalloc area to be exactly 'size'
1071 * bytes. This can be used to increase (or decrease) the vmalloc
1072 * area - the default is 240m.
1074 static int __init early_vmalloc(char *arg)
1076 unsigned long vmalloc_reserve = memparse(arg, NULL);
1078 if (vmalloc_reserve < SZ_16M) {
1079 vmalloc_reserve = SZ_16M;
1081 "vmalloc area too small, limiting to %luMB\n",
1082 vmalloc_reserve >> 20);
1085 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1086 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1088 "vmalloc area is too big, limiting to %luMB\n",
1089 vmalloc_reserve >> 20);
1092 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1095 early_param("vmalloc", early_vmalloc);
1097 phys_addr_t arm_lowmem_limit __initdata = 0;
1099 void __init sanity_check_meminfo(void)
1101 phys_addr_t memblock_limit = 0;
1103 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1104 struct memblock_region *reg;
1106 for_each_memblock(memory, reg) {
1107 phys_addr_t block_start = reg->base;
1108 phys_addr_t block_end = reg->base + reg->size;
1109 phys_addr_t size_limit = reg->size;
1111 if (reg->base >= vmalloc_limit)
1114 size_limit = vmalloc_limit - reg->base;
1117 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1120 pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
1121 &block_start, &block_end);
1122 memblock_remove(reg->base, reg->size);
1126 if (reg->size > size_limit) {
1127 phys_addr_t overlap_size = reg->size - size_limit;
1129 pr_notice("Truncating RAM at %pa-%pa to -%pa",
1130 &block_start, &block_end, &vmalloc_limit);
1131 memblock_remove(vmalloc_limit, overlap_size);
1132 block_end = vmalloc_limit;
1137 if (block_end > arm_lowmem_limit) {
1138 if (reg->size > size_limit)
1139 arm_lowmem_limit = vmalloc_limit;
1141 arm_lowmem_limit = block_end;
1145 * Find the first non-section-aligned page, and point
1146 * memblock_limit at it. This relies on rounding the
1147 * limit down to be section-aligned, which happens at
1148 * the end of this function.
1150 * With this algorithm, the start or end of almost any
1151 * bank can be non-section-aligned. The only exception
1152 * is that the start of the bank 0 must be section-
1153 * aligned, since otherwise memory would need to be
1154 * allocated when mapping the start of bank 0, which
1155 * occurs before any free memory is mapped.
1157 if (!memblock_limit) {
1158 if (!IS_ALIGNED(block_start, SECTION_SIZE))
1159 memblock_limit = block_start;
1160 else if (!IS_ALIGNED(block_end, SECTION_SIZE))
1161 memblock_limit = arm_lowmem_limit;
1167 high_memory = __va(arm_lowmem_limit - 1) + 1;
1170 * Round the memblock limit down to a section size. This
1171 * helps to ensure that we will allocate memory from the
1172 * last full section, which should be mapped.
1175 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1176 if (!memblock_limit)
1177 memblock_limit = arm_lowmem_limit;
1179 memblock_set_current_limit(memblock_limit);
1182 static inline void prepare_page_table(void)
1188 * Clear out all the mappings below the kernel image.
1190 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1191 pmd_clear(pmd_off_k(addr));
1193 #ifdef CONFIG_XIP_KERNEL
1194 /* The XIP kernel is mapped in the module area -- skip over it */
1195 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1197 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1198 pmd_clear(pmd_off_k(addr));
1201 * Find the end of the first block of lowmem.
1203 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1204 if (end >= arm_lowmem_limit)
1205 end = arm_lowmem_limit;
1208 * Clear out all the kernel space mappings, except for the first
1209 * memory bank, up to the vmalloc region.
1211 for (addr = __phys_to_virt(end);
1212 addr < VMALLOC_START; addr += PMD_SIZE)
1213 pmd_clear(pmd_off_k(addr));
1216 #ifdef CONFIG_ARM_LPAE
1217 /* the first page is reserved for pgd */
1218 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1219 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1221 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1225 * Reserve the special regions of memory
1227 void __init arm_mm_memblock_reserve(void)
1230 * Reserve the page tables. These are already in use,
1231 * and can only be in node 0.
1233 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1235 #ifdef CONFIG_SA1111
1237 * Because of the SA1111 DMA bug, we want to preserve our
1238 * precious DMA-able memory...
1240 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1245 * Set up the device mappings. Since we clear out the page tables for all
1246 * mappings above VMALLOC_START, we will remove any debug device mappings.
1247 * This means you have to be careful how you debug this function, or any
1248 * called function. This means you can't use any function or debugging
1249 * method which may touch any device, otherwise the kernel _will_ crash.
1251 static void __init devicemaps_init(const struct machine_desc *mdesc)
1253 struct map_desc map;
1258 * Allocate the vector page early.
1260 vectors = early_alloc(PAGE_SIZE * 2);
1262 early_trap_init(vectors);
1264 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1265 pmd_clear(pmd_off_k(addr));
1268 * Map the kernel if it is XIP.
1269 * It is always first in the modulearea.
1271 #ifdef CONFIG_XIP_KERNEL
1272 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1273 map.virtual = MODULES_VADDR;
1274 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1276 create_mapping(&map);
1280 * Map the cache flushing regions.
1283 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1284 map.virtual = FLUSH_BASE;
1286 map.type = MT_CACHECLEAN;
1287 create_mapping(&map);
1289 #ifdef FLUSH_BASE_MINICACHE
1290 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1291 map.virtual = FLUSH_BASE_MINICACHE;
1293 map.type = MT_MINICLEAN;
1294 create_mapping(&map);
1298 * Create a mapping for the machine vectors at the high-vectors
1299 * location (0xffff0000). If we aren't using high-vectors, also
1300 * create a mapping at the low-vectors virtual address.
1302 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1303 map.virtual = 0xffff0000;
1304 map.length = PAGE_SIZE;
1305 #ifdef CONFIG_KUSER_HELPERS
1306 map.type = MT_HIGH_VECTORS;
1308 map.type = MT_LOW_VECTORS;
1310 create_mapping(&map);
1312 if (!vectors_high()) {
1314 map.length = PAGE_SIZE * 2;
1315 map.type = MT_LOW_VECTORS;
1316 create_mapping(&map);
1319 /* Now create a kernel read-only mapping */
1321 map.virtual = 0xffff0000 + PAGE_SIZE;
1322 map.length = PAGE_SIZE;
1323 map.type = MT_LOW_VECTORS;
1324 create_mapping(&map);
1327 * Ask the machine support to map in the statically mapped devices.
1335 /* Reserve fixed i/o space in VMALLOC region */
1339 * Finally flush the caches and tlb to ensure that we're in a
1340 * consistent state wrt the writebuffer. This also ensures that
1341 * any write-allocated cache lines in the vector page are written
1342 * back. After this point, we can start to touch devices again.
1344 local_flush_tlb_all();
1348 static void __init kmap_init(void)
1350 #ifdef CONFIG_HIGHMEM
1351 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1352 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1355 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1356 _PAGE_KERNEL_TABLE);
1359 static void __init map_lowmem(void)
1361 struct memblock_region *reg;
1362 unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1363 unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1365 /* Map all the lowmem memory banks. */
1366 for_each_memblock(memory, reg) {
1367 phys_addr_t start = reg->base;
1368 phys_addr_t end = start + reg->size;
1369 struct map_desc map;
1371 if (end > arm_lowmem_limit)
1372 end = arm_lowmem_limit;
1376 if (end < kernel_x_start || start >= kernel_x_end) {
1377 map.pfn = __phys_to_pfn(start);
1378 map.virtual = __phys_to_virt(start);
1379 map.length = end - start;
1380 map.type = MT_MEMORY_RWX;
1382 create_mapping(&map);
1384 /* This better cover the entire kernel */
1385 if (start < kernel_x_start) {
1386 map.pfn = __phys_to_pfn(start);
1387 map.virtual = __phys_to_virt(start);
1388 map.length = kernel_x_start - start;
1389 map.type = MT_MEMORY_RW;
1391 create_mapping(&map);
1394 map.pfn = __phys_to_pfn(kernel_x_start);
1395 map.virtual = __phys_to_virt(kernel_x_start);
1396 map.length = kernel_x_end - kernel_x_start;
1397 map.type = MT_MEMORY_RWX;
1399 create_mapping(&map);
1401 if (kernel_x_end < end) {
1402 map.pfn = __phys_to_pfn(kernel_x_end);
1403 map.virtual = __phys_to_virt(kernel_x_end);
1404 map.length = end - kernel_x_end;
1405 map.type = MT_MEMORY_RW;
1407 create_mapping(&map);
1413 #ifdef CONFIG_ARM_LPAE
1415 * early_paging_init() recreates boot time page table setup, allowing machines
1416 * to switch over to a high (>4G) address space on LPAE systems
1418 void __init early_paging_init(const struct machine_desc *mdesc,
1419 struct proc_info_list *procinfo)
1421 pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
1422 unsigned long map_start, map_end;
1424 pud_t *pud0, *pudk, *pud_start;
1429 if (!(mdesc->init_meminfo))
1432 /* remap kernel code and data */
1433 map_start = init_mm.start_code & PMD_MASK;
1434 map_end = ALIGN(init_mm.brk, PMD_SIZE);
1436 /* get a handle on things... */
1437 pgd0 = pgd_offset_k(0);
1438 pud_start = pud0 = pud_offset(pgd0, 0);
1439 pmd0 = pmd_offset(pud0, 0);
1441 pgdk = pgd_offset_k(map_start);
1442 pudk = pud_offset(pgdk, map_start);
1443 pmdk = pmd_offset(pudk, map_start);
1445 mdesc->init_meminfo();
1447 /* Run the patch stub to update the constants */
1448 fixup_pv_table(&__pv_table_begin,
1449 (&__pv_table_end - &__pv_table_begin) << 2);
1452 * Cache cleaning operations for self-modifying code
1453 * We should clean the entries by MVA but running a
1454 * for loop over every pv_table entry pointer would
1455 * just complicate the code.
1457 flush_cache_louis();
1462 * FIXME: This code is not architecturally compliant: we modify
1463 * the mappings in-place, indeed while they are in use by this
1464 * very same code. This may lead to unpredictable behaviour of
1467 * Even modifying the mappings in a separate page table does
1470 * The architecture strongly recommends that when a mapping is
1471 * changed, that it is changed by first going via an invalid
1472 * mapping and back to the new mapping. This is to ensure that
1473 * no TLB conflicts (caused by the TLB having more than one TLB
1474 * entry match a translation) can occur. However, doing that
1475 * here will result in unmapping the code we are running.
1477 pr_warn("WARNING: unsafe modification of in-place page tables - tainting kernel\n");
1478 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1481 * Remap level 1 table. This changes the physical addresses
1482 * used to refer to the level 2 page tables to the high
1483 * physical address alias, leaving everything else the same.
1485 for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
1487 __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
1488 pmd0 += PTRS_PER_PMD;
1492 * Remap the level 2 table, pointing the mappings at the high
1493 * physical address alias of these pages.
1495 phys = __pa(map_start);
1497 *pmdk++ = __pmd(phys | pmdprot);
1499 } while (phys < map_end);
1502 * Ensure that the above updates are flushed out of the cache.
1503 * This is not strictly correct; on a system where the caches
1504 * are coherent with each other, but the MMU page table walks
1505 * may not be coherent, flush_cache_all() may be a no-op, and
1511 * Re-write the TTBR values to point them at the high physical
1512 * alias of the page tables. We expect __va() will work on
1513 * cpu_get_pgd(), which returns the value of TTBR0.
1515 cpu_switch_mm(pgd0, &init_mm);
1516 cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
1518 /* Finally flush any stale TLB values. */
1519 local_flush_bp_all();
1520 local_flush_tlb_all();
1525 void __init early_paging_init(const struct machine_desc *mdesc,
1526 struct proc_info_list *procinfo)
1528 if (mdesc->init_meminfo)
1529 mdesc->init_meminfo();
1535 * paging_init() sets up the page tables, initialises the zone memory
1536 * maps, and sets up the zero page, bad page and bad page tables.
1538 void __init paging_init(const struct machine_desc *mdesc)
1542 build_mem_type_table();
1543 prepare_page_table();
1545 dma_contiguous_remap();
1546 devicemaps_init(mdesc);
1550 top_pmd = pmd_off_k(0xffff0000);
1552 /* allocate the zero page. */
1553 zero_page = early_alloc(PAGE_SIZE);
1557 empty_zero_page = virt_to_page(zero_page);
1558 __flush_dcache_page(NULL, empty_zero_page);