arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18
  19 #include <asm/cputype.h>
  20 #include <asm/sections.h>
  21 #include <asm/cachetype.h>
  22 #include <asm/setup.h>
  23 #include <asm/sizes.h>
  24 #include <asm/smp_plat.h>
  25 #include <asm/tlb.h>
  26 #include <asm/highmem.h>
  27 #include <asm/traps.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31
  32 #include "mm.h"
  33
  34 /*
  35  * empty_zero_page is a special page that is used for
  36  * zero-initialized data and COW.
  37  */
  38 struct page *empty_zero_page;
  39 EXPORT_SYMBOL(empty_zero_page);
  40
  41 /*
  42  * The pmd table for the upper-most set of pages.
  43  */
  44 pmd_t *top_pmd;
  45
  46 #define CPOLICY_UNCACHED        0
  47 #define CPOLICY_BUFFERED        1
  48 #define CPOLICY_WRITETHROUGH    2
  49 #define CPOLICY_WRITEBACK       3
  50 #define CPOLICY_WRITEALLOC      4
  51
  52 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  53 static unsigned int ecc_mask __initdata = 0;
  54 pgprot_t pgprot_user;
  55 pgprot_t pgprot_kernel;
  56
  57 EXPORT_SYMBOL(pgprot_user);
  58 EXPORT_SYMBOL(pgprot_kernel);
  59
  60 struct cachepolicy {
  61         const char      policy[16];
  62         unsigned int    cr_mask;
  63         unsigned int    pmd;
  64         pteval_t        pte;
  65 };
  66
  67 static struct cachepolicy cache_policies[] __initdata = {
  68         {
  69                 .policy         = "uncached",
  70                 .cr_mask        = CR_W|CR_C,
  71                 .pmd            = PMD_SECT_UNCACHED,
  72                 .pte            = L_PTE_MT_UNCACHED,
  73         }, {
  74                 .policy         = "buffered",
  75                 .cr_mask        = CR_C,
  76                 .pmd            = PMD_SECT_BUFFERED,
  77                 .pte            = L_PTE_MT_BUFFERABLE,
  78         }, {
  79                 .policy         = "writethrough",
  80                 .cr_mask        = 0,
  81                 .pmd            = PMD_SECT_WT,
  82                 .pte            = L_PTE_MT_WRITETHROUGH,
  83         }, {
  84                 .policy         = "writeback",
  85                 .cr_mask        = 0,
  86                 .pmd            = PMD_SECT_WB,
  87                 .pte            = L_PTE_MT_WRITEBACK,
  88         }, {
  89                 .policy         = "writealloc",
  90                 .cr_mask        = 0,
  91                 .pmd            = PMD_SECT_WBWA,
  92                 .pte            = L_PTE_MT_WRITEALLOC,
  93         }
  94 };
  95
  96 /*
  97  * These are useful for identifying cache coherency
  98  * problems by allowing the cache or the cache and
  99  * writebuffer to be turned off.  (Note: the write
 100  * buffer should not be on and the cache off).
 101  */
 102 static int __init early_cachepolicy(char *p)
 103 {
 104         int i;
 105
 106         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 107                 int len = strlen(cache_policies[i].policy);
 108
 109                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 110                         cachepolicy = i;
 111                         cr_alignment &= ~cache_policies[i].cr_mask;
 112                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 113                         break;
 114                 }
 115         }
 116         if (i == ARRAY_SIZE(cache_policies))
 117                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 118         /*
 119          * This restriction is partly to do with the way we boot; it is
 120          * unpredictable to have memory mapped using two different sets of
 121          * memory attributes (shared, type, and cache attribs).  We can not
 122          * change these attributes once the initial assembly has setup the
 123          * page tables.
 124          */
 125         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 126                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 127                 cachepolicy = CPOLICY_WRITEBACK;
 128         }
 129         flush_cache_all();
 130         set_cr(cr_alignment);
 131         return 0;
 132 }
 133 early_param("cachepolicy", early_cachepolicy);
 134
 135 static int __init early_nocache(char *__unused)
 136 {
 137         char *p = "buffered";
 138         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 139         early_cachepolicy(p);
 140         return 0;
 141 }
 142 early_param("nocache", early_nocache);
 143
 144 static int __init early_nowrite(char *__unused)
 145 {
 146         char *p = "uncached";
 147         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 148         early_cachepolicy(p);
 149         return 0;
 150 }
 151 early_param("nowb", early_nowrite);
 152
 153 static int __init early_ecc(char *p)
 154 {
 155         if (memcmp(p, "on", 2) == 0)
 156                 ecc_mask = PMD_PROTECTION;
 157         else if (memcmp(p, "off", 3) == 0)
 158                 ecc_mask = 0;
 159         return 0;
 160 }
 161 early_param("ecc", early_ecc);
 162
 163 static int __init noalign_setup(char *__unused)
 164 {
 165         cr_alignment &= ~CR_A;
 166         cr_no_alignment &= ~CR_A;
 167         set_cr(cr_alignment);
 168         return 1;
 169 }
 170 __setup("noalign", noalign_setup);
 171
 172 #ifndef CONFIG_SMP
 173 void adjust_cr(unsigned long mask, unsigned long set)
 174 {
 175         unsigned long flags;
 176
 177         mask &= ~CR_A;
 178
 179         set &= mask;
 180
 181         local_irq_save(flags);
 182
 183         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 184         cr_alignment = (cr_alignment & ~mask) | set;
 185
 186         set_cr((get_cr() & ~mask) | set);
 187
 188         local_irq_restore(flags);
 189 }
 190 #endif
 191
 192 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 193 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 194
 195 static struct mem_type mem_types[] = {
 196         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 197                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 198                                   L_PTE_SHARED,
 199                 .prot_l1        = PMD_TYPE_TABLE,
 200                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 201                 .domain         = DOMAIN_IO,
 202         },
 203         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 204                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 205                 .prot_l1        = PMD_TYPE_TABLE,
 206                 .prot_sect      = PROT_SECT_DEVICE,
 207                 .domain         = DOMAIN_IO,
 208         },
 209         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 210                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 211                 .prot_l1        = PMD_TYPE_TABLE,
 212                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 213                 .domain         = DOMAIN_IO,
 214         },
 215         [MT_DEVICE_STRONGLY_ORDERED] = {  /* Guaranteed strongly ordered */
 216                 .prot_pte       = PROT_PTE_DEVICE,
 217                 .prot_l1        = PMD_TYPE_TABLE,
 218                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
 219                 .domain         = DOMAIN_IO,
 220         },
 221         [MT_DEVICE_WC] = {      /* ioremap_wc */
 222                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 223                 .prot_l1        = PMD_TYPE_TABLE,
 224                 .prot_sect      = PROT_SECT_DEVICE,
 225                 .domain         = DOMAIN_IO,
 226         },
 227         [MT_UNCACHED] = {
 228                 .prot_pte       = PROT_PTE_DEVICE,
 229                 .prot_l1        = PMD_TYPE_TABLE,
 230                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 231                 .domain         = DOMAIN_IO,
 232         },
 233         [MT_CACHECLEAN] = {
 234                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 235                 .domain    = DOMAIN_KERNEL,
 236         },
 237         [MT_MINICLEAN] = {
 238                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 239                 .domain    = DOMAIN_KERNEL,
 240         },
 241         [MT_LOW_VECTORS] = {
 242                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 243                                 L_PTE_RDONLY,
 244                 .prot_l1   = PMD_TYPE_TABLE,
 245                 .domain    = DOMAIN_USER,
 246         },
 247         [MT_HIGH_VECTORS] = {
 248                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 249                                 L_PTE_USER | L_PTE_RDONLY,
 250                 .prot_l1   = PMD_TYPE_TABLE,
 251                 .domain    = DOMAIN_USER,
 252         },
 253         [MT_MEMORY] = {
 254                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 255                 .prot_l1   = PMD_TYPE_TABLE,
 256                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 257                 .domain    = DOMAIN_KERNEL,
 258         },
 259         [MT_ROM] = {
 260                 .prot_sect = PMD_TYPE_SECT,
 261                 .domain    = DOMAIN_KERNEL,
 262         },
 263         [MT_MEMORY_NONCACHED] = {
 264                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 265                                 L_PTE_MT_BUFFERABLE,
 266                 .prot_l1   = PMD_TYPE_TABLE,
 267                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 268                 .domain    = DOMAIN_KERNEL,
 269         },
 270         [MT_MEMORY_DTCM] = {
 271                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 272                                 L_PTE_XN,
 273                 .prot_l1   = PMD_TYPE_TABLE,
 274                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 275                 .domain    = DOMAIN_KERNEL,
 276         },
 277         [MT_MEMORY_ITCM] = {
 278                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 279                 .prot_l1   = PMD_TYPE_TABLE,
 280                 .domain    = DOMAIN_KERNEL,
 281         },
 282 };
 283
 284 const struct mem_type *get_mem_type(unsigned int type)
 285 {
 286         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 287 }
 288 EXPORT_SYMBOL(get_mem_type);
 289
 290 /*
 291  * Adjust the PMD section entries according to the CPU in use.
 292  */
 293 static void __init build_mem_type_table(void)
 294 {
 295         struct cachepolicy *cp;
 296         unsigned int cr = get_cr();
 297         unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
 298         int cpu_arch = cpu_architecture();
 299         int i;
 300
 301         if (cpu_arch < CPU_ARCH_ARMv6) {
 302 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 303                 if (cachepolicy > CPOLICY_BUFFERED)
 304                         cachepolicy = CPOLICY_BUFFERED;
 305 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 306                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 307                         cachepolicy = CPOLICY_WRITETHROUGH;
 308 #endif
 309         }
 310         if (cpu_arch < CPU_ARCH_ARMv5) {
 311                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 312                         cachepolicy = CPOLICY_WRITEBACK;
 313                 ecc_mask = 0;
 314         }
 315 #ifndef CONFIG_PLAT_RK
 316         if (is_smp())
 317                 cachepolicy = CPOLICY_WRITEALLOC;
 318 #endif
 319
 320         /*
 321          * Strip out features not present on earlier architectures.
 322          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 323          * without extended page tables don't have the 'Shared' bit.
 324          */
 325         if (cpu_arch < CPU_ARCH_ARMv5)
 326                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 327                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 328         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 329                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 330                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 331
 332         /*
 333          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 334          * "update-able on write" bit on ARM610).  However, Xscale and
 335          * Xscale3 require this bit to be cleared.
 336          */
 337         if (cpu_is_xscale() || cpu_is_xsc3()) {
 338                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 339                         mem_types[i].prot_sect &= ~PMD_BIT4;
 340                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 341                 }
 342         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 343                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 344                         if (mem_types[i].prot_l1)
 345                                 mem_types[i].prot_l1 |= PMD_BIT4;
 346                         if (mem_types[i].prot_sect)
 347                                 mem_types[i].prot_sect |= PMD_BIT4;
 348                 }
 349         }
 350
 351         /*
 352          * Mark the device areas according to the CPU/architecture.
 353          */
 354         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 355                 if (!cpu_is_xsc3()) {
 356                         /*
 357                          * Mark device regions on ARMv6+ as execute-never
 358                          * to prevent speculative instruction fetches.
 359                          */
 360                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 361                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 362                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 363                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 364                         mem_types[MT_DEVICE_STRONGLY_ORDERED].prot_sect |= PMD_SECT_XN;
 365                 }
 366                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 367                         /*
 368                          * For ARMv7 with TEX remapping,
 369                          * - shared device is SXCB=1100
 370                          * - nonshared device is SXCB=0100
 371                          * - write combine device mem is SXCB=0001
 372                          * (Uncached Normal memory)
 373                          */
 374                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 375                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 376                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 377                 } else if (cpu_is_xsc3()) {
 378                         /*
 379                          * For Xscale3,
 380                          * - shared device is TEXCB=00101
 381                          * - nonshared device is TEXCB=01000
 382                          * - write combine device mem is TEXCB=00100
 383                          * (Inner/Outer Uncacheable in xsc3 parlance)
 384                          */
 385                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 386                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 387                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 388                 } else {
 389                         /*
 390                          * For ARMv6 and ARMv7 without TEX remapping,
 391                          * - shared device is TEXCB=00001
 392                          * - nonshared device is TEXCB=01000
 393                          * - write combine device mem is TEXCB=00100
 394                          * (Uncached Normal in ARMv6 parlance).
 395                          */
 396                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 397                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 398                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 399                 }
 400         } else {
 401                 /*
 402                  * On others, write combining is "Uncached/Buffered"
 403                  */
 404                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 405         }
 406
 407         /*
 408          * Now deal with the memory-type mappings
 409          */
 410         cp = &cache_policies[cachepolicy];
 411         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 412
 413         /*
 414          * Only use write-through for non-SMP systems
 415          */
 416         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 417                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 418
 419         /*
 420          * Enable CPU-specific coherency if supported.
 421          * (Only available on XSC3 at the moment.)
 422          */
 423         if (arch_is_coherent() && cpu_is_xsc3()) {
 424                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 425                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 426                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 427                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 428         }
 429         /*
 430          * ARMv6 and above have extended page tables.
 431          */
 432         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 433                 /*
 434                  * Mark cache clean areas and XIP ROM read only
 435                  * from SVC mode and no access from userspace.
 436                  */
 437                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 438                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 439                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 440
 441                 if (is_smp()) {
 442                         /*
 443                          * Mark memory with the "shared" attribute
 444                          * for SMP systems
 445                          */
 446                         user_pgprot |= L_PTE_SHARED;
 447                         kern_pgprot |= L_PTE_SHARED;
 448                         vecs_pgprot |= L_PTE_SHARED;
 449                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 450                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 451                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 452                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 453                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 454                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 455                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 456                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 457                 }
 458         }
 459
 460         /*
 461          * Non-cacheable Normal - intended for memory areas that must
 462          * not cause dirty cache line writebacks when used
 463          */
 464         if (cpu_arch >= CPU_ARCH_ARMv6) {
 465                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 466                         /* Non-cacheable Normal is XCB = 001 */
 467                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 468                                 PMD_SECT_BUFFERED;
 469                 } else {
 470                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 471                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 472                                 PMD_SECT_TEX(1);
 473                 }
 474         } else {
 475                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 476         }
 477
 478         for (i = 0; i < 16; i++) {
 479                 pteval_t v = pgprot_val(protection_map[i]);
 480                 protection_map[i] = __pgprot(v | user_pgprot);
 481         }
 482
 483         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 484         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 485
 486         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 487         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 488                                  L_PTE_DIRTY | kern_pgprot);
 489
 490         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 491         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 492         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 493         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 494         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 495         mem_types[MT_ROM].prot_sect |= cp->pmd;
 496
 497         switch (cp->pmd) {
 498         case PMD_SECT_WT:
 499                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 500                 break;
 501         case PMD_SECT_WB:
 502         case PMD_SECT_WBWA:
 503                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 504                 break;
 505         }
 506         printk("Memory policy: ECC %sabled, Data cache %s\n",
 507                 ecc_mask ? "en" : "dis", cp->policy);
 508
 509         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 510                 struct mem_type *t = &mem_types[i];
 511                 if (t->prot_l1)
 512                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 513                 if (t->prot_sect)
 514                         t->prot_sect |= PMD_DOMAIN(t->domain);
 515         }
 516 }
 517
 518 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 519 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 520                               unsigned long size, pgprot_t vma_prot)
 521 {
 522         if (!pfn_valid(pfn))
 523                 return pgprot_noncached(vma_prot);
 524         else if (file->f_flags & O_SYNC)
 525                 return pgprot_writecombine(vma_prot);
 526         return vma_prot;
 527 }
 528 EXPORT_SYMBOL(phys_mem_access_prot);
 529 #endif
 530
 531 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 532
 533 static void __init *early_alloc(unsigned long sz)
 534 {
 535         void *ptr = __va(memblock_alloc(sz, sz));
 536         memset(ptr, 0, sz);
 537         return ptr;
 538 }
 539
 540 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 541 {
 542         if (pmd_none(*pmd)) {
 543                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 544                 __pmd_populate(pmd, __pa(pte), prot);
 545         }
 546         BUG_ON(pmd_bad(*pmd));
 547         return pte_offset_kernel(pmd, addr);
 548 }
 549
 550 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 551                                   unsigned long end, unsigned long pfn,
 552                                   const struct mem_type *type)
 553 {
 554         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 555         do {
 556                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 557                 pfn++;
 558         } while (pte++, addr += PAGE_SIZE, addr != end);
 559 }
 560
 561 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 562                                       unsigned long end, phys_addr_t phys,
 563                                       const struct mem_type *type)
 564 {
 565         pmd_t *pmd = pmd_offset(pud, addr);
 566
 567         /*
 568          * Try a section mapping - end, addr and phys must all be aligned
 569          * to a section boundary.  Note that PMDs refer to the individual
 570          * L1 entries, whereas PGDs refer to a group of L1 entries making
 571          * up one logical pointer to an L2 table.
 572          */
 573         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
 574                 pmd_t *p = pmd;
 575
 576                 if (addr & SECTION_SIZE)
 577                         pmd++;
 578
 579                 do {
 580                         *pmd = __pmd(phys | type->prot_sect);
 581                         phys += SECTION_SIZE;
 582                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 583
 584                 flush_pmd_entry(p);
 585         } else {
 586                 /*
 587                  * No need to loop; pte's aren't interested in the
 588                  * individual L1 entries.
 589                  */
 590                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 591         }
 592 }
 593
 594 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
 595         unsigned long phys, const struct mem_type *type)
 596 {
 597         pud_t *pud = pud_offset(pgd, addr);
 598         unsigned long next;
 599
 600         do {
 601                 next = pud_addr_end(addr, end);
 602                 alloc_init_section(pud, addr, next, phys, type);
 603                 phys += next - addr;
 604         } while (pud++, addr = next, addr != end);
 605 }
 606
 607 static void __init create_36bit_mapping(struct map_desc *md,
 608                                         const struct mem_type *type)
 609 {
 610         unsigned long addr, length, end;
 611         phys_addr_t phys;
 612         pgd_t *pgd;
 613
 614         addr = md->virtual;
 615         phys = __pfn_to_phys(md->pfn);
 616         length = PAGE_ALIGN(md->length);
 617
 618         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 619                 printk(KERN_ERR "MM: CPU does not support supersection "
 620                        "mapping for 0x%08llx at 0x%08lx\n",
 621                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 622                 return;
 623         }
 624
 625         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 626          *      Since domain assignments can in fact be arbitrary, the
 627          *      'domain == 0' check below is required to insure that ARMv6
 628          *      supersections are only allocated for domain 0 regardless
 629          *      of the actual domain assignments in use.
 630          */
 631         if (type->domain) {
 632                 printk(KERN_ERR "MM: invalid domain in supersection "
 633                        "mapping for 0x%08llx at 0x%08lx\n",
 634                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 635                 return;
 636         }
 637
 638         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 639                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 640                        " at 0x%08lx invalid alignment\n",
 641                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 642                 return;
 643         }
 644
 645         /*
 646          * Shift bits [35:32] of address into bits [23:20] of PMD
 647          * (See ARMv6 spec).
 648          */
 649         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 650
 651         pgd = pgd_offset_k(addr);
 652         end = addr + length;
 653         do {
 654                 pud_t *pud = pud_offset(pgd, addr);
 655                 pmd_t *pmd = pmd_offset(pud, addr);
 656                 int i;
 657
 658                 for (i = 0; i < 16; i++)
 659                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 660
 661                 addr += SUPERSECTION_SIZE;
 662                 phys += SUPERSECTION_SIZE;
 663                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 664         } while (addr != end);
 665 }
 666
 667 /*
 668  * Create the page directory entries and any necessary
 669  * page tables for the mapping specified by `md'.  We
 670  * are able to cope here with varying sizes and address
 671  * offsets, and we take full advantage of sections and
 672  * supersections.
 673  */
 674 static void __init create_mapping(struct map_desc *md)
 675 {
 676         unsigned long addr, length, end;
 677         phys_addr_t phys;
 678         const struct mem_type *type;
 679         pgd_t *pgd;
 680
 681         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 682                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 683                        " at 0x%08lx in user region\n",
 684                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 685                 return;
 686         }
 687
 688         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 689             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 690                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 691                        " at 0x%08lx overlaps vmalloc space\n",
 692                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 693         }
 694
 695         type = &mem_types[md->type];
 696
 697         /*
 698          * Catch 36-bit addresses
 699          */
 700         if (md->pfn >= 0x100000) {
 701                 create_36bit_mapping(md, type);
 702                 return;
 703         }
 704
 705         addr = md->virtual & PAGE_MASK;
 706         phys = __pfn_to_phys(md->pfn);
 707         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 708
 709         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 710                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 711                        "be mapped using pages, ignoring.\n",
 712                        (long long)__pfn_to_phys(md->pfn), addr);
 713                 return;
 714         }
 715
 716         pgd = pgd_offset_k(addr);
 717         end = addr + length;
 718         do {
 719                 unsigned long next = pgd_addr_end(addr, end);
 720
 721                 alloc_init_pud(pgd, addr, next, phys, type);
 722
 723                 phys += next - addr;
 724                 addr = next;
 725         } while (pgd++, addr != end);
 726 }
 727
 728 /*
 729  * Create the architecture specific mappings
 730  */
 731 void __init iotable_init(struct map_desc *io_desc, int nr)
 732 {
 733         int i;
 734
 735         for (i = 0; i < nr; i++)
 736                 create_mapping(io_desc + i);
 737 }
 738
 739 #if defined(CONFIG_PLAT_RK)
 740 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_512M);
 741 #else
 742 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
 743 #endif
 744
 745 /*
 746  * vmalloc=size forces the vmalloc area to be exactly 'size'
 747  * bytes. This can be used to increase (or decrease) the vmalloc
 748  * area - the default is 128m.
 749  */
 750 static int __init early_vmalloc(char *arg)
 751 {
 752         unsigned long vmalloc_reserve = memparse(arg, NULL);
 753
 754         if (vmalloc_reserve < SZ_16M) {
 755                 vmalloc_reserve = SZ_16M;
 756                 printk(KERN_WARNING
 757                         "vmalloc area too small, limiting to %luMB\n",
 758                         vmalloc_reserve >> 20);
 759         }
 760
 761         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 762                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 763                 printk(KERN_WARNING
 764                         "vmalloc area is too big, limiting to %luMB\n",
 765                         vmalloc_reserve >> 20);
 766         }
 767
 768         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 769         return 0;
 770 }
 771 early_param("vmalloc", early_vmalloc);
 772
 773 static phys_addr_t lowmem_limit __initdata = 0;
 774
 775 void __init sanity_check_meminfo(void)
 776 {
 777         int i, j, highmem = 0;
 778
 779         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 780                 struct membank *bank = &meminfo.bank[j];
 781                 *bank = meminfo.bank[i];
 782
 783 #ifdef CONFIG_HIGHMEM
 784                 if (__va(bank->start) >= vmalloc_min ||
 785                     __va(bank->start) < (void *)PAGE_OFFSET)
 786                         highmem = 1;
 787
 788                 bank->highmem = highmem;
 789
 790                 /*
 791                  * Split those memory banks which are partially overlapping
 792                  * the vmalloc area greatly simplifying things later.
 793                  */
 794                 if (__va(bank->start) < vmalloc_min &&
 795                     bank->size > vmalloc_min - __va(bank->start)) {
 796                         if (meminfo.nr_banks >= NR_BANKS) {
 797                                 printk(KERN_CRIT "NR_BANKS too low, "
 798                                                  "ignoring high memory\n");
 799                         } else {
 800                                 memmove(bank + 1, bank,
 801                                         (meminfo.nr_banks - i) * sizeof(*bank));
 802                                 meminfo.nr_banks++;
 803                                 i++;
 804                                 bank[1].size -= vmalloc_min - __va(bank->start);
 805                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 806                                 bank[1].highmem = highmem = 1;
 807                                 j++;
 808                         }
 809                         bank->size = vmalloc_min - __va(bank->start);
 810                 }
 811 #else
 812                 bank->highmem = highmem;
 813
 814                 /*
 815                  * Check whether this memory bank would entirely overlap
 816                  * the vmalloc area.
 817                  */
 818                 if (__va(bank->start) >= vmalloc_min ||
 819                     __va(bank->start) < (void *)PAGE_OFFSET) {
 820                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 821                                "(vmalloc region overlap).\n",
 822                                (unsigned long long)bank->start,
 823                                (unsigned long long)bank->start + bank->size - 1);
 824                         continue;
 825                 }
 826
 827                 /*
 828                  * Check whether this memory bank would partially overlap
 829                  * the vmalloc area.
 830                  */
 831                 if (__va(bank->start + bank->size) > vmalloc_min ||
 832                     __va(bank->start + bank->size) < __va(bank->start)) {
 833                         unsigned long newsize = vmalloc_min - __va(bank->start);
 834                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 835                                "to -%.8llx (vmalloc region overlap).\n",
 836                                (unsigned long long)bank->start,
 837                                (unsigned long long)bank->start + bank->size - 1,
 838                                (unsigned long long)bank->start + newsize - 1);
 839                         bank->size = newsize;
 840                 }
 841 #endif
 842                 if (!bank->highmem && bank->start + bank->size > lowmem_limit)
 843                         lowmem_limit = bank->start + bank->size;
 844
 845                 j++;
 846         }
 847 #ifdef CONFIG_HIGHMEM
 848         if (highmem) {
 849                 const char *reason = NULL;
 850
 851                 if (cache_is_vipt_aliasing()) {
 852                         /*
 853                          * Interactions between kmap and other mappings
 854                          * make highmem support with aliasing VIPT caches
 855                          * rather difficult.
 856                          */
 857                         reason = "with VIPT aliasing cache";
 858                 }
 859                 if (reason) {
 860                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 861                                 reason);
 862                         while (j > 0 && meminfo.bank[j - 1].highmem)
 863                                 j--;
 864                 }
 865         }
 866 #endif
 867         meminfo.nr_banks = j;
 868         memblock_set_current_limit(lowmem_limit);
 869 }
 870
 871 static inline void prepare_page_table(void)
 872 {
 873         unsigned long addr;
 874         phys_addr_t end;
 875
 876         /*
 877          * Clear out all the mappings below the kernel image.
 878          */
 879         for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
 880                 pmd_clear(pmd_off_k(addr));
 881
 882 #ifdef CONFIG_XIP_KERNEL
 883         /* The XIP kernel is mapped in the module area -- skip over it */
 884         addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
 885 #endif
 886         for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
 887                 pmd_clear(pmd_off_k(addr));
 888
 889         /*
 890          * Find the end of the first block of lowmem.
 891          */
 892         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
 893         if (end >= lowmem_limit)
 894                 end = lowmem_limit;
 895
 896         /*
 897          * Clear out all the kernel space mappings, except for the first
 898          * memory bank, up to the end of the vmalloc region.
 899          */
 900         for (addr = __phys_to_virt(end);
 901              addr < VMALLOC_END; addr += PGDIR_SIZE)
 902                 pmd_clear(pmd_off_k(addr));
 903 }
 904
 905 /*
 906  * Reserve the special regions of memory
 907  */
 908 void __init arm_mm_memblock_reserve(void)
 909 {
 910         /*
 911          * Reserve the page tables.  These are already in use,
 912          * and can only be in node 0.
 913          */
 914         memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
 915
 916 #ifdef CONFIG_SA1111
 917         /*
 918          * Because of the SA1111 DMA bug, we want to preserve our
 919          * precious DMA-able memory...
 920          */
 921         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 922 #endif
 923 }
 924
 925 /*
 926  * Set up device the mappings.  Since we clear out the page tables for all
 927  * mappings above VMALLOC_END, we will remove any debug device mappings.
 928  * This means you have to be careful how you debug this function, or any
 929  * called function.  This means you can't use any function or debugging
 930  * method which may touch any device, otherwise the kernel _will_ crash.
 931  */
 932 static void __init devicemaps_init(struct machine_desc *mdesc)
 933 {
 934         struct map_desc map;
 935         unsigned long addr;
 936
 937         /*
 938          * Allocate the vector page early.
 939          */
 940         vectors_page = early_alloc(PAGE_SIZE);
 941
 942         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 943                 pmd_clear(pmd_off_k(addr));
 944
 945         /*
 946          * Map the kernel if it is XIP.
 947          * It is always first in the modulearea.
 948          */
 949 #ifdef CONFIG_XIP_KERNEL
 950         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
 951         map.virtual = MODULES_VADDR;
 952         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
 953         map.type = MT_ROM;
 954         create_mapping(&map);
 955 #endif
 956
 957         /*
 958          * Map the cache flushing regions.
 959          */
 960 #ifdef FLUSH_BASE
 961         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
 962         map.virtual = FLUSH_BASE;
 963         map.length = SZ_1M;
 964         map.type = MT_CACHECLEAN;
 965         create_mapping(&map);
 966 #endif
 967 #ifdef FLUSH_BASE_MINICACHE
 968         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
 969         map.virtual = FLUSH_BASE_MINICACHE;
 970         map.length = SZ_1M;
 971         map.type = MT_MINICLEAN;
 972         create_mapping(&map);
 973 #endif
 974
 975         /*
 976          * Create a mapping for the machine vectors at the high-vectors
 977          * location (0xffff0000).  If we aren't using high-vectors, also
 978          * create a mapping at the low-vectors virtual address.
 979          */
 980         map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
 981         map.virtual = 0xffff0000;
 982         map.length = PAGE_SIZE;
 983         map.type = MT_HIGH_VECTORS;
 984         create_mapping(&map);
 985
 986         if (!vectors_high()) {
 987                 map.virtual = 0;
 988                 map.type = MT_LOW_VECTORS;
 989                 create_mapping(&map);
 990         }
 991
 992         /*
 993          * Ask the machine support to map in the statically mapped devices.
 994          */
 995         if (mdesc->map_io)
 996                 mdesc->map_io();
 997
 998         /*
 999          * Finally flush the caches and tlb to ensure that we're in a
1000          * consistent state wrt the writebuffer.  This also ensures that
1001          * any write-allocated cache lines in the vector page are written
1002          * back.  After this point, we can start to touch devices again.
1003          */
1004         local_flush_tlb_all();
1005         flush_cache_all();
1006 }
1007
1008 static void __init kmap_init(void)
1009 {
1010 #ifdef CONFIG_HIGHMEM
1011         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1012                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1013 #endif
1014 }
1015
1016 static void __init map_lowmem(void)
1017 {
1018         struct memblock_region *reg;
1019
1020         /* Map all the lowmem memory banks. */
1021         for_each_memblock(memory, reg) {
1022                 phys_addr_t start = reg->base;
1023                 phys_addr_t end = start + reg->size;
1024                 struct map_desc map;
1025
1026                 if (end > lowmem_limit)
1027                         end = lowmem_limit;
1028                 if (start >= end)
1029                         break;
1030
1031                 map.pfn = __phys_to_pfn(start);
1032                 map.virtual = __phys_to_virt(start);
1033                 map.length = end - start;
1034                 map.type = MT_MEMORY;
1035
1036                 create_mapping(&map);
1037         }
1038 }
1039
1040 /*
1041  * paging_init() sets up the page tables, initialises the zone memory
1042  * maps, and sets up the zero page, bad page and bad page tables.
1043  */
1044 void __init paging_init(struct machine_desc *mdesc)
1045 {
1046         void *zero_page;
1047
1048         memblock_set_current_limit(lowmem_limit);
1049
1050         build_mem_type_table();
1051         prepare_page_table();
1052         map_lowmem();
1053         devicemaps_init(mdesc);
1054         kmap_init();
1055
1056         top_pmd = pmd_off_k(0xffff0000);
1057
1058         /* allocate the zero page. */
1059         zero_page = early_alloc(PAGE_SIZE);
1060
1061         bootmem_init();
1062
1063         empty_zero_page = virt_to_page(zero_page);
1064         __flush_dcache_page(NULL, empty_zero_page);
1065 }