2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/setup.h>
26 #include <asm/smp_plat.h>
28 #include <asm/highmem.h>
29 #include <asm/system_info.h>
30 #include <asm/traps.h>
31 #include <asm/procinfo.h>
32 #include <asm/memory.h>
34 #include <asm/mach/arch.h>
35 #include <asm/mach/map.h>
36 #include <asm/mach/pci.h>
42 * empty_zero_page is a special page that is used for
43 * zero-initialized data and COW.
45 struct page *empty_zero_page;
46 EXPORT_SYMBOL(empty_zero_page);
49 * The pmd table for the upper-most set of pages.
53 #define CPOLICY_UNCACHED 0
54 #define CPOLICY_BUFFERED 1
55 #define CPOLICY_WRITETHROUGH 2
56 #define CPOLICY_WRITEBACK 3
57 #define CPOLICY_WRITEALLOC 4
59 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
60 static unsigned int ecc_mask __initdata = 0;
62 pgprot_t pgprot_kernel;
63 pgprot_t pgprot_hyp_device;
65 pgprot_t pgprot_s2_device;
67 EXPORT_SYMBOL(pgprot_user);
68 EXPORT_SYMBOL(pgprot_kernel);
71 const char policy[16];
78 #ifdef CONFIG_ARM_LPAE
79 #define s2_policy(policy) policy
81 #define s2_policy(policy) 0
84 static struct cachepolicy cache_policies[] __initdata = {
88 .pmd = PMD_SECT_UNCACHED,
89 .pte = L_PTE_MT_UNCACHED,
90 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
94 .pmd = PMD_SECT_BUFFERED,
95 .pte = L_PTE_MT_BUFFERABLE,
96 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
98 .policy = "writethrough",
101 .pte = L_PTE_MT_WRITETHROUGH,
102 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
104 .policy = "writeback",
107 .pte = L_PTE_MT_WRITEBACK,
108 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
110 .policy = "writealloc",
112 .pmd = PMD_SECT_WBWA,
113 .pte = L_PTE_MT_WRITEALLOC,
114 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
118 #ifdef CONFIG_CPU_CP15
120 * These are useful for identifying cache coherency
121 * problems by allowing the cache or the cache and
122 * writebuffer to be turned off. (Note: the write
123 * buffer should not be on and the cache off).
125 static int __init early_cachepolicy(char *p)
129 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
130 int len = strlen(cache_policies[i].policy);
132 if (memcmp(p, cache_policies[i].policy, len) == 0) {
134 cr_alignment &= ~cache_policies[i].cr_mask;
135 cr_no_alignment &= ~cache_policies[i].cr_mask;
139 if (i == ARRAY_SIZE(cache_policies))
140 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
142 * This restriction is partly to do with the way we boot; it is
143 * unpredictable to have memory mapped using two different sets of
144 * memory attributes (shared, type, and cache attribs). We can not
145 * change these attributes once the initial assembly has setup the
148 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
149 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
150 cachepolicy = CPOLICY_WRITEBACK;
153 set_cr(cr_alignment);
156 early_param("cachepolicy", early_cachepolicy);
158 static int __init early_nocache(char *__unused)
160 char *p = "buffered";
161 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
162 early_cachepolicy(p);
165 early_param("nocache", early_nocache);
167 static int __init early_nowrite(char *__unused)
169 char *p = "uncached";
170 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
171 early_cachepolicy(p);
174 early_param("nowb", early_nowrite);
176 #ifndef CONFIG_ARM_LPAE
177 static int __init early_ecc(char *p)
179 if (memcmp(p, "on", 2) == 0)
180 ecc_mask = PMD_PROTECTION;
181 else if (memcmp(p, "off", 3) == 0)
185 early_param("ecc", early_ecc);
188 static int __init noalign_setup(char *__unused)
190 cr_alignment &= ~CR_A;
191 cr_no_alignment &= ~CR_A;
192 set_cr(cr_alignment);
195 __setup("noalign", noalign_setup);
198 void adjust_cr(unsigned long mask, unsigned long set)
206 local_irq_save(flags);
208 cr_no_alignment = (cr_no_alignment & ~mask) | set;
209 cr_alignment = (cr_alignment & ~mask) | set;
211 set_cr((get_cr() & ~mask) | set);
213 local_irq_restore(flags);
217 #else /* ifdef CONFIG_CPU_CP15 */
219 static int __init early_cachepolicy(char *p)
221 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
223 early_param("cachepolicy", early_cachepolicy);
225 static int __init noalign_setup(char *__unused)
227 pr_warning("noalign kernel parameter not supported without cp15\n");
229 __setup("noalign", noalign_setup);
231 #endif /* ifdef CONFIG_CPU_CP15 / else */
233 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
234 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
236 static struct mem_type mem_types[] = {
237 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
238 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
240 .prot_l1 = PMD_TYPE_TABLE,
241 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
244 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
245 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
246 .prot_l1 = PMD_TYPE_TABLE,
247 .prot_sect = PROT_SECT_DEVICE,
250 [MT_DEVICE_CACHED] = { /* ioremap_cached */
251 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
252 .prot_l1 = PMD_TYPE_TABLE,
253 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
256 [MT_DEVICE_WC] = { /* ioremap_wc */
257 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
258 .prot_l1 = PMD_TYPE_TABLE,
259 .prot_sect = PROT_SECT_DEVICE,
263 .prot_pte = PROT_PTE_DEVICE,
264 .prot_l1 = PMD_TYPE_TABLE,
265 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
269 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
270 .domain = DOMAIN_KERNEL,
272 #ifndef CONFIG_ARM_LPAE
274 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
275 .domain = DOMAIN_KERNEL,
279 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
281 .prot_l1 = PMD_TYPE_TABLE,
282 .domain = DOMAIN_USER,
284 [MT_HIGH_VECTORS] = {
285 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
286 L_PTE_USER | L_PTE_RDONLY,
287 .prot_l1 = PMD_TYPE_TABLE,
288 .domain = DOMAIN_USER,
291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
292 .prot_l1 = PMD_TYPE_TABLE,
293 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
294 .domain = DOMAIN_KERNEL,
297 .prot_sect = PMD_TYPE_SECT,
298 .domain = DOMAIN_KERNEL,
300 [MT_MEMORY_RWX_NONCACHED] = {
301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
303 .prot_l1 = PMD_TYPE_TABLE,
304 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
305 .domain = DOMAIN_KERNEL,
307 [MT_MEMORY_RW_DTCM] = {
308 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
310 .prot_l1 = PMD_TYPE_TABLE,
311 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
312 .domain = DOMAIN_KERNEL,
314 [MT_MEMORY_RWX_ITCM] = {
315 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
316 .prot_l1 = PMD_TYPE_TABLE,
317 .domain = DOMAIN_KERNEL,
319 [MT_MEMORY_RW_SO] = {
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_MT_UNCACHED | L_PTE_XN,
322 .prot_l1 = PMD_TYPE_TABLE,
323 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
324 PMD_SECT_UNCACHED | PMD_SECT_XN,
325 .domain = DOMAIN_KERNEL,
327 [MT_MEMORY_DMA_READY] = {
328 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
329 .prot_l1 = PMD_TYPE_TABLE,
330 .domain = DOMAIN_KERNEL,
334 const struct mem_type *get_mem_type(unsigned int type)
336 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
338 EXPORT_SYMBOL(get_mem_type);
341 * Adjust the PMD section entries according to the CPU in use.
343 static void __init build_mem_type_table(void)
345 struct cachepolicy *cp;
346 unsigned int cr = get_cr();
347 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
348 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
349 int cpu_arch = cpu_architecture();
352 if (cpu_arch < CPU_ARCH_ARMv6) {
353 #if defined(CONFIG_CPU_DCACHE_DISABLE)
354 if (cachepolicy > CPOLICY_BUFFERED)
355 cachepolicy = CPOLICY_BUFFERED;
356 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
357 if (cachepolicy > CPOLICY_WRITETHROUGH)
358 cachepolicy = CPOLICY_WRITETHROUGH;
361 if (cpu_arch < CPU_ARCH_ARMv5) {
362 if (cachepolicy >= CPOLICY_WRITEALLOC)
363 cachepolicy = CPOLICY_WRITEBACK;
367 cachepolicy = CPOLICY_WRITEALLOC;
370 * Strip out features not present on earlier architectures.
371 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
372 * without extended page tables don't have the 'Shared' bit.
374 if (cpu_arch < CPU_ARCH_ARMv5)
375 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
376 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
377 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
378 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
379 mem_types[i].prot_sect &= ~PMD_SECT_S;
382 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
383 * "update-able on write" bit on ARM610). However, Xscale and
384 * Xscale3 require this bit to be cleared.
386 if (cpu_is_xscale() || cpu_is_xsc3()) {
387 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
388 mem_types[i].prot_sect &= ~PMD_BIT4;
389 mem_types[i].prot_l1 &= ~PMD_BIT4;
391 } else if (cpu_arch < CPU_ARCH_ARMv6) {
392 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
393 if (mem_types[i].prot_l1)
394 mem_types[i].prot_l1 |= PMD_BIT4;
395 if (mem_types[i].prot_sect)
396 mem_types[i].prot_sect |= PMD_BIT4;
401 * Mark the device areas according to the CPU/architecture.
403 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
404 if (!cpu_is_xsc3()) {
406 * Mark device regions on ARMv6+ as execute-never
407 * to prevent speculative instruction fetches.
409 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
410 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
411 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
412 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
414 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
416 * For ARMv7 with TEX remapping,
417 * - shared device is SXCB=1100
418 * - nonshared device is SXCB=0100
419 * - write combine device mem is SXCB=0001
420 * (Uncached Normal memory)
422 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
423 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
424 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
425 } else if (cpu_is_xsc3()) {
428 * - shared device is TEXCB=00101
429 * - nonshared device is TEXCB=01000
430 * - write combine device mem is TEXCB=00100
431 * (Inner/Outer Uncacheable in xsc3 parlance)
433 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
434 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
435 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
438 * For ARMv6 and ARMv7 without TEX remapping,
439 * - shared device is TEXCB=00001
440 * - nonshared device is TEXCB=01000
441 * - write combine device mem is TEXCB=00100
442 * (Uncached Normal in ARMv6 parlance).
444 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
445 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
446 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
450 * On others, write combining is "Uncached/Buffered"
452 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
456 * Now deal with the memory-type mappings
458 cp = &cache_policies[cachepolicy];
459 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
460 s2_pgprot = cp->pte_s2;
461 hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
464 * ARMv6 and above have extended page tables.
466 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
467 #ifndef CONFIG_ARM_LPAE
469 * Mark cache clean areas and XIP ROM read only
470 * from SVC mode and no access from userspace.
472 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
473 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
474 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
479 * Mark memory with the "shared" attribute
482 user_pgprot |= L_PTE_SHARED;
483 kern_pgprot |= L_PTE_SHARED;
484 vecs_pgprot |= L_PTE_SHARED;
485 s2_pgprot |= L_PTE_SHARED;
486 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
487 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
488 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
489 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
490 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
491 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
492 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
493 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
494 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
499 * Non-cacheable Normal - intended for memory areas that must
500 * not cause dirty cache line writebacks when used
502 if (cpu_arch >= CPU_ARCH_ARMv6) {
503 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
504 /* Non-cacheable Normal is XCB = 001 */
505 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
508 /* For both ARMv6 and non-TEX-remapping ARMv7 */
509 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
513 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
516 #ifdef CONFIG_ARM_LPAE
518 * Do not generate access flag faults for the kernel mappings.
520 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
521 mem_types[i].prot_pte |= PTE_EXT_AF;
522 if (mem_types[i].prot_sect)
523 mem_types[i].prot_sect |= PMD_SECT_AF;
525 kern_pgprot |= PTE_EXT_AF;
526 vecs_pgprot |= PTE_EXT_AF;
529 for (i = 0; i < 16; i++) {
530 pteval_t v = pgprot_val(protection_map[i]);
531 protection_map[i] = __pgprot(v | user_pgprot);
534 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
535 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
537 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
538 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
539 L_PTE_DIRTY | kern_pgprot);
540 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
541 pgprot_s2_device = __pgprot(s2_device_pgprot);
542 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
544 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
545 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
546 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
547 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
548 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
549 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
550 mem_types[MT_ROM].prot_sect |= cp->pmd;
554 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
558 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
561 pr_info("Memory policy: %sData cache %s\n",
562 ecc_mask ? "ECC enabled, " : "", cp->policy);
564 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
565 struct mem_type *t = &mem_types[i];
567 t->prot_l1 |= PMD_DOMAIN(t->domain);
569 t->prot_sect |= PMD_DOMAIN(t->domain);
573 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
574 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
575 unsigned long size, pgprot_t vma_prot)
578 return pgprot_noncached(vma_prot);
579 else if (file->f_flags & O_SYNC)
580 return pgprot_writecombine(vma_prot);
583 EXPORT_SYMBOL(phys_mem_access_prot);
586 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
588 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
590 void *ptr = __va(memblock_alloc(sz, align));
595 static void __init *early_alloc(unsigned long sz)
597 return early_alloc_aligned(sz, sz);
600 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
602 if (pmd_none(*pmd)) {
603 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
604 __pmd_populate(pmd, __pa(pte), prot);
606 BUG_ON(pmd_bad(*pmd));
607 return pte_offset_kernel(pmd, addr);
610 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
611 unsigned long end, unsigned long pfn,
612 const struct mem_type *type)
614 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
616 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
618 } while (pte++, addr += PAGE_SIZE, addr != end);
621 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
622 unsigned long end, phys_addr_t phys,
623 const struct mem_type *type)
627 #ifndef CONFIG_ARM_LPAE
629 * In classic MMU format, puds and pmds are folded in to
630 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
631 * group of L1 entries making up one logical pointer to
632 * an L2 table (2MB), where as PMDs refer to the individual
633 * L1 entries (1MB). Hence increment to get the correct
634 * offset for odd 1MB sections.
635 * (See arch/arm/include/asm/pgtable-2level.h)
637 if (addr & SECTION_SIZE)
641 *pmd = __pmd(phys | type->prot_sect);
642 phys += SECTION_SIZE;
643 } while (pmd++, addr += SECTION_SIZE, addr != end);
648 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
649 unsigned long end, phys_addr_t phys,
650 const struct mem_type *type)
652 pmd_t *pmd = pmd_offset(pud, addr);
657 * With LPAE, we must loop over to map
658 * all the pmds for the given range.
660 next = pmd_addr_end(addr, end);
663 * Try a section mapping - addr, next and phys must all be
664 * aligned to a section boundary.
666 if (type->prot_sect &&
667 ((addr | next | phys) & ~SECTION_MASK) == 0) {
668 __map_init_section(pmd, addr, next, phys, type);
670 alloc_init_pte(pmd, addr, next,
671 __phys_to_pfn(phys), type);
676 } while (pmd++, addr = next, addr != end);
679 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
680 unsigned long end, phys_addr_t phys,
681 const struct mem_type *type)
683 pud_t *pud = pud_offset(pgd, addr);
687 next = pud_addr_end(addr, end);
688 alloc_init_pmd(pud, addr, next, phys, type);
690 } while (pud++, addr = next, addr != end);
693 #ifndef CONFIG_ARM_LPAE
694 static void __init create_36bit_mapping(struct map_desc *md,
695 const struct mem_type *type)
697 unsigned long addr, length, end;
702 phys = __pfn_to_phys(md->pfn);
703 length = PAGE_ALIGN(md->length);
705 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
706 printk(KERN_ERR "MM: CPU does not support supersection "
707 "mapping for 0x%08llx at 0x%08lx\n",
708 (long long)__pfn_to_phys((u64)md->pfn), addr);
712 /* N.B. ARMv6 supersections are only defined to work with domain 0.
713 * Since domain assignments can in fact be arbitrary, the
714 * 'domain == 0' check below is required to insure that ARMv6
715 * supersections are only allocated for domain 0 regardless
716 * of the actual domain assignments in use.
719 printk(KERN_ERR "MM: invalid domain in supersection "
720 "mapping for 0x%08llx at 0x%08lx\n",
721 (long long)__pfn_to_phys((u64)md->pfn), addr);
725 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
726 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
727 " at 0x%08lx invalid alignment\n",
728 (long long)__pfn_to_phys((u64)md->pfn), addr);
733 * Shift bits [35:32] of address into bits [23:20] of PMD
736 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
738 pgd = pgd_offset_k(addr);
741 pud_t *pud = pud_offset(pgd, addr);
742 pmd_t *pmd = pmd_offset(pud, addr);
745 for (i = 0; i < 16; i++)
746 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
748 addr += SUPERSECTION_SIZE;
749 phys += SUPERSECTION_SIZE;
750 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
751 } while (addr != end);
753 #endif /* !CONFIG_ARM_LPAE */
756 * Create the page directory entries and any necessary
757 * page tables for the mapping specified by `md'. We
758 * are able to cope here with varying sizes and address
759 * offsets, and we take full advantage of sections and
762 static void __init create_mapping(struct map_desc *md)
764 unsigned long addr, length, end;
766 const struct mem_type *type;
769 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
770 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
771 " at 0x%08lx in user region\n",
772 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
776 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
777 md->virtual >= PAGE_OFFSET &&
778 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
779 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
780 " at 0x%08lx out of vmalloc space\n",
781 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
784 type = &mem_types[md->type];
786 #ifndef CONFIG_ARM_LPAE
788 * Catch 36-bit addresses
790 if (md->pfn >= 0x100000) {
791 create_36bit_mapping(md, type);
796 addr = md->virtual & PAGE_MASK;
797 phys = __pfn_to_phys(md->pfn);
798 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
800 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
801 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
802 "be mapped using pages, ignoring.\n",
803 (long long)__pfn_to_phys(md->pfn), addr);
807 pgd = pgd_offset_k(addr);
810 unsigned long next = pgd_addr_end(addr, end);
812 alloc_init_pud(pgd, addr, next, phys, type);
816 } while (pgd++, addr != end);
820 * Create the architecture specific mappings
822 void __init iotable_init(struct map_desc *io_desc, int nr)
825 struct vm_struct *vm;
826 struct static_vm *svm;
831 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
833 for (md = io_desc; nr; md++, nr--) {
837 vm->addr = (void *)(md->virtual & PAGE_MASK);
838 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
839 vm->phys_addr = __pfn_to_phys(md->pfn);
840 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
841 vm->flags |= VM_ARM_MTYPE(md->type);
842 vm->caller = iotable_init;
843 add_static_vm_early(svm++);
847 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
850 struct vm_struct *vm;
851 struct static_vm *svm;
853 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
856 vm->addr = (void *)addr;
858 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
860 add_static_vm_early(svm);
863 #ifndef CONFIG_ARM_LPAE
866 * The Linux PMD is made of two consecutive section entries covering 2MB
867 * (see definition in include/asm/pgtable-2level.h). However a call to
868 * create_mapping() may optimize static mappings by using individual
869 * 1MB section mappings. This leaves the actual PMD potentially half
870 * initialized if the top or bottom section entry isn't used, leaving it
871 * open to problems if a subsequent ioremap() or vmalloc() tries to use
872 * the virtual space left free by that unused section entry.
874 * Let's avoid the issue by inserting dummy vm entries covering the unused
875 * PMD halves once the static mappings are in place.
878 static void __init pmd_empty_section_gap(unsigned long addr)
880 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
883 static void __init fill_pmd_gaps(void)
885 struct static_vm *svm;
886 struct vm_struct *vm;
887 unsigned long addr, next = 0;
890 list_for_each_entry(svm, &static_vmlist, list) {
892 addr = (unsigned long)vm->addr;
897 * Check if this vm starts on an odd section boundary.
898 * If so and the first section entry for this PMD is free
899 * then we block the corresponding virtual address.
901 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
902 pmd = pmd_off_k(addr);
904 pmd_empty_section_gap(addr & PMD_MASK);
908 * Then check if this vm ends on an odd section boundary.
909 * If so and the second section entry for this PMD is empty
910 * then we block the corresponding virtual address.
913 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
914 pmd = pmd_off_k(addr) + 1;
916 pmd_empty_section_gap(addr);
919 /* no need to look at any vm entry until we hit the next PMD */
920 next = (addr + PMD_SIZE - 1) & PMD_MASK;
925 #define fill_pmd_gaps() do { } while (0)
928 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
929 static void __init pci_reserve_io(void)
931 struct static_vm *svm;
933 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
937 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
940 #define pci_reserve_io() do { } while (0)
943 #ifdef CONFIG_DEBUG_LL
944 void __init debug_ll_io_init(void)
948 debug_ll_addr(&map.pfn, &map.virtual);
949 if (!map.pfn || !map.virtual)
951 map.pfn = __phys_to_pfn(map.pfn);
952 map.virtual &= PAGE_MASK;
953 map.length = PAGE_SIZE;
954 map.type = MT_DEVICE;
955 iotable_init(&map, 1);
959 static void * __initdata vmalloc_min =
960 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
963 * vmalloc=size forces the vmalloc area to be exactly 'size'
964 * bytes. This can be used to increase (or decrease) the vmalloc
965 * area - the default is 240m.
967 static int __init early_vmalloc(char *arg)
969 unsigned long vmalloc_reserve = memparse(arg, NULL);
971 if (vmalloc_reserve < SZ_16M) {
972 vmalloc_reserve = SZ_16M;
974 "vmalloc area too small, limiting to %luMB\n",
975 vmalloc_reserve >> 20);
978 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
979 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
981 "vmalloc area is too big, limiting to %luMB\n",
982 vmalloc_reserve >> 20);
985 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
988 early_param("vmalloc", early_vmalloc);
990 phys_addr_t arm_lowmem_limit __initdata = 0;
992 void __init sanity_check_meminfo(void)
994 phys_addr_t memblock_limit = 0;
995 int i, j, highmem = 0;
996 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
998 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
999 struct membank *bank = &meminfo.bank[j];
1000 phys_addr_t size_limit;
1002 *bank = meminfo.bank[i];
1003 size_limit = bank->size;
1005 if (bank->start >= vmalloc_limit)
1008 size_limit = vmalloc_limit - bank->start;
1010 bank->highmem = highmem;
1012 #ifdef CONFIG_HIGHMEM
1014 * Split those memory banks which are partially overlapping
1015 * the vmalloc area greatly simplifying things later.
1017 if (!highmem && bank->size > size_limit) {
1018 if (meminfo.nr_banks >= NR_BANKS) {
1019 printk(KERN_CRIT "NR_BANKS too low, "
1020 "ignoring high memory\n");
1022 memmove(bank + 1, bank,
1023 (meminfo.nr_banks - i) * sizeof(*bank));
1026 bank[1].size -= size_limit;
1027 bank[1].start = vmalloc_limit;
1028 bank[1].highmem = highmem = 1;
1031 bank->size = size_limit;
1035 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1038 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1039 "(!CONFIG_HIGHMEM).\n",
1040 (unsigned long long)bank->start,
1041 (unsigned long long)bank->start + bank->size - 1);
1046 * Check whether this memory bank would partially overlap
1049 if (bank->size > size_limit) {
1050 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1051 "to -%.8llx (vmalloc region overlap).\n",
1052 (unsigned long long)bank->start,
1053 (unsigned long long)bank->start + bank->size - 1,
1054 (unsigned long long)bank->start + size_limit - 1);
1055 bank->size = size_limit;
1058 if (!bank->highmem) {
1059 phys_addr_t bank_end = bank->start + bank->size;
1061 if (bank_end > arm_lowmem_limit)
1062 arm_lowmem_limit = bank_end;
1065 * Find the first non-section-aligned page, and point
1066 * memblock_limit at it. This relies on rounding the
1067 * limit down to be section-aligned, which happens at
1068 * the end of this function.
1070 * With this algorithm, the start or end of almost any
1071 * bank can be non-section-aligned. The only exception
1072 * is that the start of the bank 0 must be section-
1073 * aligned, since otherwise memory would need to be
1074 * allocated when mapping the start of bank 0, which
1075 * occurs before any free memory is mapped.
1077 if (!memblock_limit) {
1078 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1079 memblock_limit = bank->start;
1080 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1081 memblock_limit = bank_end;
1086 #ifdef CONFIG_HIGHMEM
1088 const char *reason = NULL;
1090 if (cache_is_vipt_aliasing()) {
1092 * Interactions between kmap and other mappings
1093 * make highmem support with aliasing VIPT caches
1096 reason = "with VIPT aliasing cache";
1099 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1101 while (j > 0 && meminfo.bank[j - 1].highmem)
1106 meminfo.nr_banks = j;
1107 high_memory = __va(arm_lowmem_limit - 1) + 1;
1110 * Round the memblock limit down to a section size. This
1111 * helps to ensure that we will allocate memory from the
1112 * last full section, which should be mapped.
1115 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1116 if (!memblock_limit)
1117 memblock_limit = arm_lowmem_limit;
1119 memblock_set_current_limit(memblock_limit);
1122 static inline void prepare_page_table(void)
1128 * Clear out all the mappings below the kernel image.
1130 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1131 pmd_clear(pmd_off_k(addr));
1133 #ifdef CONFIG_XIP_KERNEL
1134 /* The XIP kernel is mapped in the module area -- skip over it */
1135 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1137 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1138 pmd_clear(pmd_off_k(addr));
1141 * Find the end of the first block of lowmem.
1143 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1144 if (end >= arm_lowmem_limit)
1145 end = arm_lowmem_limit;
1148 * Clear out all the kernel space mappings, except for the first
1149 * memory bank, up to the vmalloc region.
1151 for (addr = __phys_to_virt(end);
1152 addr < VMALLOC_START; addr += PMD_SIZE)
1153 pmd_clear(pmd_off_k(addr));
1156 #ifdef CONFIG_ARM_LPAE
1157 /* the first page is reserved for pgd */
1158 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1159 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1161 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1165 * Reserve the special regions of memory
1167 void __init arm_mm_memblock_reserve(void)
1170 * Reserve the page tables. These are already in use,
1171 * and can only be in node 0.
1173 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1175 #ifdef CONFIG_SA1111
1177 * Because of the SA1111 DMA bug, we want to preserve our
1178 * precious DMA-able memory...
1180 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1185 * Set up the device mappings. Since we clear out the page tables for all
1186 * mappings above VMALLOC_START, we will remove any debug device mappings.
1187 * This means you have to be careful how you debug this function, or any
1188 * called function. This means you can't use any function or debugging
1189 * method which may touch any device, otherwise the kernel _will_ crash.
1191 static void __init devicemaps_init(const struct machine_desc *mdesc)
1193 struct map_desc map;
1198 * Allocate the vector page early.
1200 vectors = early_alloc(PAGE_SIZE * 2);
1202 early_trap_init(vectors);
1204 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1205 pmd_clear(pmd_off_k(addr));
1208 * Map the kernel if it is XIP.
1209 * It is always first in the modulearea.
1211 #ifdef CONFIG_XIP_KERNEL
1212 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1213 map.virtual = MODULES_VADDR;
1214 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1216 create_mapping(&map);
1220 * Map the cache flushing regions.
1223 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1224 map.virtual = FLUSH_BASE;
1226 map.type = MT_CACHECLEAN;
1227 create_mapping(&map);
1229 #ifdef FLUSH_BASE_MINICACHE
1230 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1231 map.virtual = FLUSH_BASE_MINICACHE;
1233 map.type = MT_MINICLEAN;
1234 create_mapping(&map);
1238 * Create a mapping for the machine vectors at the high-vectors
1239 * location (0xffff0000). If we aren't using high-vectors, also
1240 * create a mapping at the low-vectors virtual address.
1242 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1243 map.virtual = 0xffff0000;
1244 map.length = PAGE_SIZE;
1245 #ifdef CONFIG_KUSER_HELPERS
1246 map.type = MT_HIGH_VECTORS;
1248 map.type = MT_LOW_VECTORS;
1250 create_mapping(&map);
1252 if (!vectors_high()) {
1254 map.length = PAGE_SIZE * 2;
1255 map.type = MT_LOW_VECTORS;
1256 create_mapping(&map);
1259 /* Now create a kernel read-only mapping */
1261 map.virtual = 0xffff0000 + PAGE_SIZE;
1262 map.length = PAGE_SIZE;
1263 map.type = MT_LOW_VECTORS;
1264 create_mapping(&map);
1267 * Ask the machine support to map in the statically mapped devices.
1275 /* Reserve fixed i/o space in VMALLOC region */
1279 * Finally flush the caches and tlb to ensure that we're in a
1280 * consistent state wrt the writebuffer. This also ensures that
1281 * any write-allocated cache lines in the vector page are written
1282 * back. After this point, we can start to touch devices again.
1284 local_flush_tlb_all();
1288 static void __init kmap_init(void)
1290 #ifdef CONFIG_HIGHMEM
1291 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1292 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1296 static void __init map_lowmem(void)
1298 struct memblock_region *reg;
1300 /* Map all the lowmem memory banks. */
1301 for_each_memblock(memory, reg) {
1302 phys_addr_t start = reg->base;
1303 phys_addr_t end = start + reg->size;
1304 struct map_desc map;
1306 if (end > arm_lowmem_limit)
1307 end = arm_lowmem_limit;
1311 map.pfn = __phys_to_pfn(start);
1312 map.virtual = __phys_to_virt(start);
1313 map.length = end - start;
1314 map.type = MT_MEMORY;
1316 create_mapping(&map);
1320 #ifdef CONFIG_ARM_LPAE
1322 * early_paging_init() recreates boot time page table setup, allowing machines
1323 * to switch over to a high (>4G) address space on LPAE systems
1325 void __init early_paging_init(const struct machine_desc *mdesc,
1326 struct proc_info_list *procinfo)
1328 pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
1329 unsigned long map_start, map_end;
1331 pud_t *pud0, *pudk, *pud_start;
1336 if (!(mdesc->init_meminfo))
1339 /* remap kernel code and data */
1340 map_start = init_mm.start_code;
1341 map_end = init_mm.brk;
1343 /* get a handle on things... */
1344 pgd0 = pgd_offset_k(0);
1345 pud_start = pud0 = pud_offset(pgd0, 0);
1346 pmd0 = pmd_offset(pud0, 0);
1348 pgdk = pgd_offset_k(map_start);
1349 pudk = pud_offset(pgdk, map_start);
1350 pmdk = pmd_offset(pudk, map_start);
1352 mdesc->init_meminfo();
1354 /* Run the patch stub to update the constants */
1355 fixup_pv_table(&__pv_table_begin,
1356 (&__pv_table_end - &__pv_table_begin) << 2);
1359 * Cache cleaning operations for self-modifying code
1360 * We should clean the entries by MVA but running a
1361 * for loop over every pv_table entry pointer would
1362 * just complicate the code.
1364 flush_cache_louis();
1368 /* remap level 1 table */
1369 for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
1371 __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
1372 pmd0 += PTRS_PER_PMD;
1375 /* remap pmds for kernel mapping */
1376 phys = __pa(map_start) & PMD_MASK;
1378 *pmdk++ = __pmd(phys | pmdprot);
1380 } while (phys < map_end);
1383 cpu_switch_mm(pgd0, &init_mm);
1384 cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
1385 local_flush_bp_all();
1386 local_flush_tlb_all();
1391 void __init early_paging_init(const struct machine_desc *mdesc,
1392 struct proc_info_list *procinfo)
1394 if (mdesc->init_meminfo)
1395 mdesc->init_meminfo();
1401 * paging_init() sets up the page tables, initialises the zone memory
1402 * maps, and sets up the zero page, bad page and bad page tables.
1404 void __init paging_init(const struct machine_desc *mdesc)
1408 build_mem_type_table();
1409 prepare_page_table();
1411 dma_contiguous_remap();
1412 devicemaps_init(mdesc);
1416 top_pmd = pmd_off_k(0xffff0000);
1418 /* allocate the zero page. */
1419 zero_page = early_alloc(PAGE_SIZE);
1423 empty_zero_page = virt_to_page(zero_page);
1424 __flush_dcache_page(NULL, empty_zero_page);