2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 ENTRY(cpu_v7_proc_init)
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ENDPROC(cpu_v7_proc_fin)
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
47 * - loc - location to jump to for soft reset
49 * This code must be executed using a flat identity mapping with
53 .pushsection .idmap.text, "ax"
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
67 * Idle the processor (eg, wait for interrupt).
69 * IRQs are already disabled.
72 dsb @ WFI may enter a low-power mode
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(mov pc, lr) @ MP extensions imply L1 PTW
80 dcache_line_size r2, r3
81 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 ENDPROC(cpu_v7_dcache_clean_area)
89 string cpu_v7_name, "ARMv7 Processor"
92 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
93 .globl cpu_v7_suspend_size
94 .equ cpu_v7_suspend_size, 4 * 8
95 #ifdef CONFIG_ARM_CPU_SUSPEND
96 ENTRY(cpu_v7_do_suspend)
97 stmfd sp!, {r4 - r10, lr}
98 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
99 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
102 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
103 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
104 mrc p15, 0, r8, c1, c0, 0 @ Control register
105 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
106 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
108 ldmfd sp!, {r4 - r10, pc}
109 ENDPROC(cpu_v7_do_suspend)
111 ENTRY(cpu_v7_do_resume)
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
114 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
117 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
118 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
120 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
121 #ifndef CONFIG_ARM_LPAE
122 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
123 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
125 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
126 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
127 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
128 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
129 teq r4, r9 @ Is it already set?
130 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
131 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
134 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
135 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
138 mov r0, r8 @ control register
140 ENDPROC(cpu_v7_do_resume)
143 #ifdef CONFIG_CPU_PJ4B
144 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
145 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
146 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
147 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
148 globl_equ cpu_pj4b_reset, cpu_v7_reset
149 #ifdef CONFIG_PJ4B_ERRATA_4742
150 ENTRY(cpu_pj4b_do_idle)
151 dsb @ WFI may enter a low-power mode
155 ENDPROC(cpu_pj4b_do_idle)
157 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
159 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
160 globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
161 globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
162 globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
171 * Initialise TLB, Caches, and MMU state ready to switch the MMU
172 * on. Return in r0 the new CP15 C1 control register setting.
174 * This should be able to cover all ARMv7 cores.
176 * It is assumed that:
177 * - cache type register is implemented
181 mov r10, #(1 << 0) @ TLB ops broadcasting
188 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
189 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
190 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
191 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
192 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
193 mcreq p15, 0, r0, c1, c0, 1
198 #ifdef CONFIG_CPU_PJ4B
200 /* Auxiliary Debug Modes Control 1 Register */
201 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
202 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
203 #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
204 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
206 /* Auxiliary Debug Modes Control 2 Register */
207 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
208 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
209 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
210 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
211 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
212 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
213 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
215 /* Auxiliary Functional Modes Control Register 0 */
216 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
217 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
218 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
220 /* Auxiliary Debug Modes Control 0 Register */
221 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
223 /* Auxiliary Debug Modes Control 1 Register */
224 mrc p15, 1, r0, c15, c1, 1
225 orr r0, r0, #PJ4B_CLEAN_LINE
226 orr r0, r0, #PJ4B_BCK_OFF_STREX
227 orr r0, r0, #PJ4B_INTER_PARITY
228 bic r0, r0, #PJ4B_STATIC_BP
229 mcr p15, 1, r0, c15, c1, 1
231 /* Auxiliary Debug Modes Control 2 Register */
232 mrc p15, 1, r0, c15, c1, 2
233 bic r0, r0, #PJ4B_FAST_LDR
234 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
235 mcr p15, 1, r0, c15, c1, 2
237 /* Auxiliary Functional Modes Control Register 0 */
238 mrc p15, 1, r0, c15, c2, 0
240 orr r0, r0, #PJ4B_SMP_CFB
242 orr r0, r0, #PJ4B_L1_PAR_CHK
243 orr r0, r0, #PJ4B_BROADCAST_CACHE
244 mcr p15, 1, r0, c15, c2, 0
246 /* Auxiliary Debug Modes Control 0 Register */
247 mrc p15, 1, r0, c15, c1, 0
248 orr r0, r0, #PJ4B_WFI_WFE
249 mcr p15, 1, r0, c15, c1, 0
251 #endif /* CONFIG_CPU_PJ4B */
254 adr r12, __v7_setup_stack @ the local stack
255 stmia r12, {r0-r5, r7, r9, r11, lr}
256 bl v7_flush_dcache_louis
257 ldmia r12, {r0-r5, r7, r9, r11, lr}
259 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
260 and r10, r0, #0xff000000 @ ARM?
263 and r5, r0, #0x00f00000 @ variant
264 and r6, r0, #0x0000000f @ revision
265 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
266 ubfx r0, r0, #4, #12 @ primary part number
268 /* Cortex-A8 Errata */
269 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
272 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
274 teq r5, #0x00100000 @ only present in r1p*
275 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
276 orreq r10, r10, #(1 << 6) @ set IBE to 1
277 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
279 #ifdef CONFIG_ARM_ERRATA_458693
280 teq r6, #0x20 @ only present in r2p0
281 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
282 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
283 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
284 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
286 #ifdef CONFIG_ARM_ERRATA_460075
287 teq r6, #0x20 @ only present in r2p0
288 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
290 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
291 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
295 /* Cortex-A9 Errata */
296 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
299 #ifdef CONFIG_ARM_ERRATA_742230
300 cmp r6, #0x22 @ only present up to r2p2
301 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
302 orrle r10, r10, #1 << 4 @ set bit #4
303 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
305 #ifdef CONFIG_ARM_ERRATA_742231
306 teq r6, #0x20 @ present in r2p0
307 teqne r6, #0x21 @ present in r2p1
308 teqne r6, #0x22 @ present in r2p2
309 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
310 orreq r10, r10, #1 << 12 @ set bit #12
311 orreq r10, r10, #1 << 22 @ set bit #22
312 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
314 #ifdef CONFIG_ARM_ERRATA_743622
315 teq r5, #0x00200000 @ only present in r2p*
316 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
317 orreq r10, r10, #1 << 6 @ set bit #6
318 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
320 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
321 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
323 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
324 orrlt r10, r10, #1 << 11 @ set bit #11
325 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
330 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
333 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
334 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
337 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
338 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
340 #ifndef CONFIG_ARM_THUMBEE
341 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
342 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
343 teq r0, #(1 << 12) @ check if ThumbEE is present
346 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
347 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
348 orr r0, r0, #1 @ set the 1st bit in order to
349 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
354 #ifdef CONFIG_CPU_ENDIAN_BE8
355 orr r6, r6, #1 << 25 @ big-endian page tables
357 #ifdef CONFIG_SWP_EMULATE
358 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
359 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
361 mrc p15, 0, r0, c1, c0, 0 @ read control register
362 bic r0, r0, r5 @ clear bits them
363 orr r0, r0, r6 @ set them
364 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
365 mov pc, lr @ return to head.S:__ret
370 .space 4 * 11 @ 11 registers
374 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
375 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
376 #ifdef CONFIG_CPU_PJ4B
377 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
382 string cpu_arch_name, "armv7"
383 string cpu_elf_name, "v7"
386 .section ".proc.info.init", #alloc, #execinstr
389 * Standard v7 proc info content
391 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
392 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
393 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
394 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
395 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
396 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
397 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
401 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
402 HWCAP_EDSP | HWCAP_TLS | \hwcaps
410 #ifndef CONFIG_ARM_LPAE
412 * ARM Ltd. Cortex A5 processor.
414 .type __v7_ca5mp_proc_info, #object
415 __v7_ca5mp_proc_info:
418 __v7_proc __v7_ca5mp_setup
419 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
422 * ARM Ltd. Cortex A9 processor.
424 .type __v7_ca9mp_proc_info, #object
425 __v7_ca9mp_proc_info:
428 __v7_proc __v7_ca9mp_setup
429 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
431 #endif /* CONFIG_ARM_LPAE */
434 * Marvell PJ4B processor.
436 #ifdef CONFIG_CPU_PJ4B
437 .type __v7_pj4b_proc_info, #object
441 __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
442 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
446 * ARM Ltd. Cortex A7 processor.
448 .type __v7_ca7mp_proc_info, #object
449 __v7_ca7mp_proc_info:
452 __v7_proc __v7_ca7mp_setup
453 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
456 * ARM Ltd. Cortex A15 processor.
458 .type __v7_ca15mp_proc_info, #object
459 __v7_ca15mp_proc_info:
462 __v7_proc __v7_ca15mp_setup
463 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
466 * Qualcomm Inc. Krait processors.
468 .type __krait_proc_info, #object
470 .long 0x510f0400 @ Required ID value
471 .long 0xff0ffc00 @ Mask for ID
473 * Some Krait processors don't indicate support for SDIV and UDIV
474 * instructions in the ARM instruction set, even though they actually
477 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
478 .size __krait_proc_info, . - __krait_proc_info
481 * Match any ARMv7 processor core.
483 .type __v7_proc_info, #object
485 .long 0x000f0000 @ Required ID value
486 .long 0x000f0000 @ Mask for ID
488 .size __v7_proc_info, . - __v7_proc_info