2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 ENTRY(cpu_v7_proc_init)
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ENDPROC(cpu_v7_proc_fin)
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
47 * - loc - location to jump to for soft reset
49 * This code must be executed using a flat identity mapping with
53 .pushsection .idmap.text, "ax"
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
67 * Idle the processor (eg, wait for interrupt).
69 * IRQs are already disabled.
72 dsb @ WFI may enter a low-power mode
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
81 1: dcache_line_size r2, r3
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
88 ENDPROC(cpu_v7_dcache_clean_area)
90 string cpu_v7_name, "ARMv7 Processor"
93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94 .globl cpu_v7_suspend_size
95 .equ cpu_v7_suspend_size, 4 * 8
96 #ifdef CONFIG_ARM_CPU_SUSPEND
97 ENTRY(cpu_v7_do_suspend)
98 stmfd sp!, {r4 - r10, lr}
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
102 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
103 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
104 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
105 mrc p15, 0, r8, c1, c0, 0 @ Control register
106 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
107 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
109 ldmfd sp!, {r4 - r10, pc}
110 ENDPROC(cpu_v7_do_suspend)
112 ENTRY(cpu_v7_do_resume)
114 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
115 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
116 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
118 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
119 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
121 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
122 #ifndef CONFIG_ARM_LPAE
123 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
124 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
126 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
127 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
128 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
129 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
130 teq r4, r9 @ Is it already set?
131 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
132 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
135 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
136 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
139 mov r0, r8 @ control register
141 ENDPROC(cpu_v7_do_resume)
144 #ifdef CONFIG_CPU_PJ4B
145 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
146 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
147 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
148 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
149 globl_equ cpu_pj4b_reset, cpu_v7_reset
150 #ifdef CONFIG_PJ4B_ERRATA_4742
151 ENTRY(cpu_pj4b_do_idle)
152 dsb @ WFI may enter a low-power mode
156 ENDPROC(cpu_pj4b_do_idle)
158 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
160 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
161 globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
162 globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
163 globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
172 * Initialise TLB, Caches, and MMU state ready to switch the MMU
173 * on. Return in r0 the new CP15 C1 control register setting.
175 * This should be able to cover all ARMv7 cores.
177 * It is assumed that:
178 * - cache type register is implemented
182 mov r10, #(1 << 0) @ TLB ops broadcasting
189 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
190 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
191 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
192 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
193 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
194 mcreq p15, 0, r0, c1, c0, 1
199 #ifdef CONFIG_CPU_PJ4B
201 /* Auxiliary Debug Modes Control 1 Register */
202 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
203 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
204 #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
205 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
207 /* Auxiliary Debug Modes Control 2 Register */
208 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
209 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
210 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
211 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
212 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
213 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
214 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
216 /* Auxiliary Functional Modes Control Register 0 */
217 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
218 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
219 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
221 /* Auxiliary Debug Modes Control 0 Register */
222 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
224 /* Auxiliary Debug Modes Control 1 Register */
225 mrc p15, 1, r0, c15, c1, 1
226 orr r0, r0, #PJ4B_CLEAN_LINE
227 orr r0, r0, #PJ4B_BCK_OFF_STREX
228 orr r0, r0, #PJ4B_INTER_PARITY
229 bic r0, r0, #PJ4B_STATIC_BP
230 mcr p15, 1, r0, c15, c1, 1
232 /* Auxiliary Debug Modes Control 2 Register */
233 mrc p15, 1, r0, c15, c1, 2
234 bic r0, r0, #PJ4B_FAST_LDR
235 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
236 mcr p15, 1, r0, c15, c1, 2
238 /* Auxiliary Functional Modes Control Register 0 */
239 mrc p15, 1, r0, c15, c2, 0
241 orr r0, r0, #PJ4B_SMP_CFB
243 orr r0, r0, #PJ4B_L1_PAR_CHK
244 orr r0, r0, #PJ4B_BROADCAST_CACHE
245 mcr p15, 1, r0, c15, c2, 0
247 /* Auxiliary Debug Modes Control 0 Register */
248 mrc p15, 1, r0, c15, c1, 0
249 orr r0, r0, #PJ4B_WFI_WFE
250 mcr p15, 1, r0, c15, c1, 0
252 #endif /* CONFIG_CPU_PJ4B */
255 adr r12, __v7_setup_stack @ the local stack
256 stmia r12, {r0-r5, r7, r9, r11, lr}
257 bl v7_flush_dcache_louis
258 ldmia r12, {r0-r5, r7, r9, r11, lr}
260 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
261 and r10, r0, #0xff000000 @ ARM?
264 and r5, r0, #0x00f00000 @ variant
265 and r6, r0, #0x0000000f @ revision
266 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
267 ubfx r0, r0, #4, #12 @ primary part number
269 /* Cortex-A8 Errata */
270 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
273 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
275 teq r5, #0x00100000 @ only present in r1p*
276 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
277 orreq r10, r10, #(1 << 6) @ set IBE to 1
278 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
280 #ifdef CONFIG_ARM_ERRATA_458693
281 teq r6, #0x20 @ only present in r2p0
282 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
283 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
284 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
285 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
287 #ifdef CONFIG_ARM_ERRATA_460075
288 teq r6, #0x20 @ only present in r2p0
289 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
291 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
292 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
296 /* Cortex-A9 Errata */
297 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
300 #ifdef CONFIG_ARM_ERRATA_742230
301 cmp r6, #0x22 @ only present up to r2p2
302 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
303 orrle r10, r10, #1 << 4 @ set bit #4
304 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
306 #ifdef CONFIG_ARM_ERRATA_742231
307 teq r6, #0x20 @ present in r2p0
308 teqne r6, #0x21 @ present in r2p1
309 teqne r6, #0x22 @ present in r2p2
310 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
311 orreq r10, r10, #1 << 12 @ set bit #12
312 orreq r10, r10, #1 << 22 @ set bit #22
313 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
315 #ifdef CONFIG_ARM_ERRATA_743622
316 teq r5, #0x00200000 @ only present in r2p*
317 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
318 orreq r10, r10, #1 << 6 @ set bit #6
319 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
321 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
322 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
324 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
325 orrlt r10, r10, #1 << 11 @ set bit #11
326 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
331 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
333 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
334 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
337 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
338 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
340 dsb @ Complete invalidations
341 #ifndef CONFIG_ARM_THUMBEE
342 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
343 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
344 teq r0, #(1 << 12) @ check if ThumbEE is present
347 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
348 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
349 orr r0, r0, #1 @ set the 1st bit in order to
350 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
355 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
356 #ifdef CONFIG_SWP_EMULATE
357 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
358 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
360 mrc p15, 0, r0, c1, c0, 0 @ read control register
361 bic r0, r0, r5 @ clear bits them
362 orr r0, r0, r6 @ set them
363 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
364 mov pc, lr @ return to head.S:__ret
369 .space 4 * 11 @ 11 registers
373 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
374 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
375 #ifdef CONFIG_CPU_PJ4B
376 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
381 string cpu_arch_name, "armv7"
382 string cpu_elf_name, "v7"
385 .section ".proc.info.init", #alloc, #execinstr
388 * Standard v7 proc info content
390 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
391 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
392 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
393 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
394 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
395 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
396 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
400 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
401 HWCAP_EDSP | HWCAP_TLS | \hwcaps
409 #ifndef CONFIG_ARM_LPAE
411 * ARM Ltd. Cortex A5 processor.
413 .type __v7_ca5mp_proc_info, #object
414 __v7_ca5mp_proc_info:
417 __v7_proc __v7_ca5mp_setup
418 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
421 * ARM Ltd. Cortex A9 processor.
423 .type __v7_ca9mp_proc_info, #object
424 __v7_ca9mp_proc_info:
427 __v7_proc __v7_ca9mp_setup
428 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
430 #endif /* CONFIG_ARM_LPAE */
433 * Marvell PJ4B processor.
435 #ifdef CONFIG_CPU_PJ4B
436 .type __v7_pj4b_proc_info, #object
440 __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
441 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
445 * ARM Ltd. Cortex A7 processor.
447 .type __v7_ca7mp_proc_info, #object
448 __v7_ca7mp_proc_info:
451 __v7_proc __v7_ca7mp_setup
452 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
455 * ARM Ltd. Cortex A15 processor.
457 .type __v7_ca15mp_proc_info, #object
458 __v7_ca15mp_proc_info:
461 __v7_proc __v7_ca15mp_setup
462 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
465 * Qualcomm Inc. Krait processors.
467 .type __krait_proc_info, #object
469 .long 0x510f0400 @ Required ID value
470 .long 0xff0ffc00 @ Mask for ID
472 * Some Krait processors don't indicate support for SDIV and UDIV
473 * instructions in the ARM instruction set, even though they actually
476 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
477 .size __krait_proc_info, . - __krait_proc_info
480 * Match any ARMv7 processor core.
482 .type __v7_proc_info, #object
484 .long 0x000f0000 @ Required ID value
485 .long 0x000f0000 @ Mask for ID
487 .size __v7_proc_info, . - __v7_proc_info