2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
29 #include <asm/system.h>
30 #include <asm/hardware.h>
34 #include <asm/arch/tc.h>
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
52 static int enable_1510_mode = 0;
60 void (* callback)(int lch, u16 ch_status, void *data);
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
75 struct dma_link_info {
77 int no_of_lchs_linked;
88 static struct dma_link_info *dma_linked_lch;
90 #ifndef CONFIG_ARCH_OMAP1
92 /* Chain handling macros */
93 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
99 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109 #define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
124 static int dma_lch_count;
125 static int dma_chan_count;
127 static spinlock_t dma_chan_lock;
128 static struct omap_dma_lch *dma_chan;
130 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
131 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
132 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
133 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
134 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
135 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
138 static inline void disable_lnk(int lch);
139 static void omap_disable_channel_irq(int lch);
140 static inline void omap_enable_channel_irq(int lch);
142 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
145 #ifdef CONFIG_ARCH_OMAP15XX
146 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
147 int omap_dma_in_1510_mode(void)
149 return enable_1510_mode;
152 #define omap_dma_in_1510_mode() 0
155 #ifdef CONFIG_ARCH_OMAP1
156 static inline int get_gdma_dev(int req)
158 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
159 int shift = ((req - 1) % 5) * 6;
161 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
164 static inline void set_gdma_dev(int req, int dev)
166 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
167 int shift = ((req - 1) % 5) * 6;
171 l &= ~(0x3f << shift);
172 l |= (dev - 1) << shift;
176 #define set_gdma_dev(req, dev) do {} while (0)
179 static void clear_lch_regs(int lch)
182 u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
184 for (i = 0; i < 0x2c; i += 2)
185 omap_writew(0, lch_base + i);
188 void omap_set_dma_priority(int lch, int dst_port, int priority)
193 if (cpu_class_is_omap1()) {
195 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
196 reg = OMAP_TC_OCPT1_PRIOR;
198 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
199 reg = OMAP_TC_OCPT2_PRIOR;
201 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
202 reg = OMAP_TC_EMIFF_PRIOR;
204 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
205 reg = OMAP_TC_EMIFS_PRIOR;
213 l |= (priority & 0xf) << 8;
217 if (cpu_class_is_omap2()) {
219 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
221 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
225 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
226 int frame_count, int sync_mode,
227 int dma_trigger, int src_or_dst_synch)
229 OMAP_DMA_CSDP_REG(lch) &= ~0x03;
230 OMAP_DMA_CSDP_REG(lch) |= data_type;
232 if (cpu_class_is_omap1()) {
233 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
234 if (sync_mode == OMAP_DMA_SYNC_FRAME)
235 OMAP_DMA_CCR_REG(lch) |= 1 << 5;
237 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
238 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
239 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
242 if (cpu_class_is_omap2() && dma_trigger) {
243 u32 val = OMAP_DMA_CCR_REG(lch);
246 if (dma_trigger > 63)
248 if (dma_trigger > 31)
252 val |= (dma_trigger & 0x1f);
254 if (sync_mode & OMAP_DMA_SYNC_FRAME)
259 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
264 if (src_or_dst_synch)
265 val |= 1 << 24; /* source synch */
267 val &= ~(1 << 24); /* dest synch */
269 OMAP_DMA_CCR_REG(lch) = val;
272 OMAP_DMA_CEN_REG(lch) = elem_count;
273 OMAP_DMA_CFN_REG(lch) = frame_count;
276 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
280 BUG_ON(omap_dma_in_1510_mode());
282 if (cpu_class_is_omap2()) {
287 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
289 case OMAP_DMA_CONSTANT_FILL:
292 case OMAP_DMA_TRANSPARENT_COPY:
295 case OMAP_DMA_COLOR_DIS:
300 OMAP1_DMA_CCR2_REG(lch) = w;
302 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
303 /* Default is channel type 2D */
305 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
306 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
307 w |= 1; /* Channel type G */
309 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
312 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
314 if (cpu_class_is_omap2()) {
315 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
316 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
320 /* Note that src_port is only for omap1 */
321 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
322 unsigned long src_start,
323 int src_ei, int src_fi)
325 if (cpu_class_is_omap1()) {
326 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
327 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
330 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
331 OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
333 if (cpu_class_is_omap1()) {
334 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
335 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
338 if (cpu_class_is_omap2())
339 OMAP2_DMA_CSSA_REG(lch) = src_start;
341 OMAP_DMA_CSEI_REG(lch) = src_ei;
342 OMAP_DMA_CSFI_REG(lch) = src_fi;
345 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
347 omap_set_dma_transfer_params(lch, params->data_type,
348 params->elem_count, params->frame_count,
349 params->sync_mode, params->trigger,
350 params->src_or_dst_synch);
351 omap_set_dma_src_params(lch, params->src_port,
352 params->src_amode, params->src_start,
353 params->src_ei, params->src_fi);
355 omap_set_dma_dest_params(lch, params->dst_port,
356 params->dst_amode, params->dst_start,
357 params->dst_ei, params->dst_fi);
358 if (params->read_prio || params->write_prio)
359 omap_dma_set_prio_lch(lch, params->read_prio,
363 void omap_set_dma_src_index(int lch, int eidx, int fidx)
365 if (cpu_class_is_omap2()) {
369 OMAP_DMA_CSEI_REG(lch) = eidx;
370 OMAP_DMA_CSFI_REG(lch) = fidx;
373 void omap_set_dma_src_data_pack(int lch, int enable)
375 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
377 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
380 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
382 unsigned int burst = 0;
383 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
385 switch (burst_mode) {
386 case OMAP_DMA_DATA_BURST_DIS:
388 case OMAP_DMA_DATA_BURST_4:
389 if (cpu_class_is_omap2())
394 case OMAP_DMA_DATA_BURST_8:
395 if (cpu_class_is_omap2()) {
399 /* not supported by current hardware on OMAP1
403 case OMAP_DMA_DATA_BURST_16:
404 if (cpu_class_is_omap2()) {
408 /* OMAP1 don't support burst 16
414 OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
417 /* Note that dest_port is only for OMAP1 */
418 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
419 unsigned long dest_start,
420 int dst_ei, int dst_fi)
422 if (cpu_class_is_omap1()) {
423 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
424 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
427 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
428 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
430 if (cpu_class_is_omap1()) {
431 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
432 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
435 if (cpu_class_is_omap2())
436 OMAP2_DMA_CDSA_REG(lch) = dest_start;
438 OMAP_DMA_CDEI_REG(lch) = dst_ei;
439 OMAP_DMA_CDFI_REG(lch) = dst_fi;
442 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
444 if (cpu_class_is_omap2()) {
448 OMAP_DMA_CDEI_REG(lch) = eidx;
449 OMAP_DMA_CDFI_REG(lch) = fidx;
452 void omap_set_dma_dest_data_pack(int lch, int enable)
454 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
456 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
459 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
461 unsigned int burst = 0;
462 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
464 switch (burst_mode) {
465 case OMAP_DMA_DATA_BURST_DIS:
467 case OMAP_DMA_DATA_BURST_4:
468 if (cpu_class_is_omap2())
473 case OMAP_DMA_DATA_BURST_8:
474 if (cpu_class_is_omap2())
479 case OMAP_DMA_DATA_BURST_16:
480 if (cpu_class_is_omap2()) {
484 /* OMAP1 don't support burst 16
488 printk(KERN_ERR "Invalid DMA burst mode\n");
492 OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
495 static inline void omap_enable_channel_irq(int lch)
500 if (cpu_class_is_omap1())
501 status = OMAP_DMA_CSR_REG(lch);
502 else if (cpu_class_is_omap2())
503 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
505 /* Enable some nice interrupts. */
506 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
509 static void omap_disable_channel_irq(int lch)
511 if (cpu_class_is_omap2())
512 OMAP_DMA_CICR_REG(lch) = 0;
515 void omap_enable_dma_irq(int lch, u16 bits)
517 dma_chan[lch].enabled_irqs |= bits;
520 void omap_disable_dma_irq(int lch, u16 bits)
522 dma_chan[lch].enabled_irqs &= ~bits;
525 static inline void enable_lnk(int lch)
527 if (cpu_class_is_omap1())
528 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
530 /* Set the ENABLE_LNK bits */
531 if (dma_chan[lch].next_lch != -1)
532 OMAP_DMA_CLNK_CTRL_REG(lch) =
533 dma_chan[lch].next_lch | (1 << 15);
535 #ifndef CONFIG_ARCH_OMAP1
536 if (dma_chan[lch].next_linked_ch != -1)
537 OMAP_DMA_CLNK_CTRL_REG(lch) =
538 dma_chan[lch].next_linked_ch | (1 << 15);
542 static inline void disable_lnk(int lch)
544 /* Disable interrupts */
545 if (cpu_class_is_omap1()) {
546 OMAP_DMA_CICR_REG(lch) = 0;
547 /* Set the STOP_LNK bit */
548 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
551 if (cpu_class_is_omap2()) {
552 omap_disable_channel_irq(lch);
553 /* Clear the ENABLE_LNK bit */
554 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
557 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
560 static inline void omap2_enable_irq_lch(int lch)
564 if (!cpu_class_is_omap2())
567 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
569 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
572 int omap_request_dma(int dev_id, const char *dev_name,
573 void (* callback)(int lch, u16 ch_status, void *data),
574 void *data, int *dma_ch_out)
576 int ch, free_ch = -1;
578 struct omap_dma_lch *chan;
580 spin_lock_irqsave(&dma_chan_lock, flags);
581 for (ch = 0; ch < dma_chan_count; ch++) {
582 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
589 spin_unlock_irqrestore(&dma_chan_lock, flags);
592 chan = dma_chan + free_ch;
593 chan->dev_id = dev_id;
595 if (cpu_class_is_omap1())
596 clear_lch_regs(free_ch);
598 if (cpu_class_is_omap2())
599 omap_clear_dma(free_ch);
601 spin_unlock_irqrestore(&dma_chan_lock, flags);
603 chan->dev_name = dev_name;
604 chan->callback = callback;
606 #ifndef CONFIG_ARCH_OMAP1
608 chan->next_linked_ch = -1;
610 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
612 if (cpu_class_is_omap1())
613 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
614 else if (cpu_class_is_omap2())
615 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
616 OMAP2_DMA_TRANS_ERR_IRQ;
618 if (cpu_is_omap16xx()) {
619 /* If the sync device is set, configure it dynamically. */
621 set_gdma_dev(free_ch + 1, dev_id);
622 dev_id = free_ch + 1;
624 /* Disable the 1510 compatibility mode and set the sync device
626 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
627 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
628 OMAP_DMA_CCR_REG(free_ch) = dev_id;
631 if (cpu_class_is_omap2()) {
632 omap2_enable_irq_lch(free_ch);
634 omap_enable_channel_irq(free_ch);
635 /* Clear the CSR register and IRQ status register */
636 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
637 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
640 *dma_ch_out = free_ch;
645 void omap_free_dma(int lch)
649 spin_lock_irqsave(&dma_chan_lock, flags);
650 if (dma_chan[lch].dev_id == -1) {
651 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
653 spin_unlock_irqrestore(&dma_chan_lock, flags);
656 dma_chan[lch].dev_id = -1;
657 dma_chan[lch].next_lch = -1;
658 dma_chan[lch].callback = NULL;
659 spin_unlock_irqrestore(&dma_chan_lock, flags);
661 if (cpu_class_is_omap1()) {
662 /* Disable all DMA interrupts for the channel. */
663 OMAP_DMA_CICR_REG(lch) = 0;
664 /* Make sure the DMA transfer is stopped. */
665 OMAP_DMA_CCR_REG(lch) = 0;
668 if (cpu_class_is_omap2()) {
670 /* Disable interrupts */
671 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
673 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
675 /* Clear the CSR register and IRQ status register */
676 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
677 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
679 /* Disable all DMA interrupts for the channel. */
680 OMAP_DMA_CICR_REG(lch) = 0;
682 /* Make sure the DMA transfer is stopped. */
683 OMAP_DMA_CCR_REG(lch) = 0;
689 * @brief omap_dma_set_global_params : Set global priority settings for dma
692 * @param max_fifo_depth
693 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
694 * DMA_THREAD_RESERVE_ONET
695 * DMA_THREAD_RESERVE_TWOT
696 * DMA_THREAD_RESERVE_THREET
699 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
703 if (!cpu_class_is_omap2()) {
704 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
711 reg = (arb_rate & 0xff) << 16;
712 reg |= (0xff & max_fifo_depth);
714 omap_writel(reg, OMAP_DMA4_GCR_REG);
716 EXPORT_SYMBOL(omap_dma_set_global_params);
719 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
722 * @param read_prio - Read priority
723 * @param write_prio - Write priority
724 * Both of the above can be set with one of the following values :
725 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
728 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
729 unsigned char write_prio)
733 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
734 printk(KERN_ERR "Invalid channel id\n");
737 w = OMAP_DMA_CCR_REG(lch);
738 w &= ~((1 << 6) | (1 << 26));
739 if (cpu_is_omap2430() || cpu_is_omap34xx())
740 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
742 w |= ((read_prio & 0x1) << 6);
744 OMAP_DMA_CCR_REG(lch) = w;
747 EXPORT_SYMBOL(omap_dma_set_prio_lch);
750 * Clears any DMA state so the DMA engine is ready to restart with new buffers
751 * through omap_start_dma(). Any buffers in flight are discarded.
753 void omap_clear_dma(int lch)
757 local_irq_save(flags);
759 if (cpu_class_is_omap1()) {
761 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
763 /* Clear pending interrupts */
764 status = OMAP_DMA_CSR_REG(lch);
767 if (cpu_class_is_omap2()) {
769 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
770 for (i = 0; i < 0x44; i += 4)
771 omap_writel(0, lch_base + i);
774 local_irq_restore(flags);
777 void omap_start_dma(int lch)
779 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
780 int next_lch, cur_lch;
781 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
783 dma_chan_link_map[lch] = 1;
784 /* Set the link register of the first channel */
787 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
788 cur_lch = dma_chan[lch].next_lch;
790 next_lch = dma_chan[cur_lch].next_lch;
792 /* The loop case: we've been here already */
793 if (dma_chan_link_map[cur_lch])
795 /* Mark the current channel */
796 dma_chan_link_map[cur_lch] = 1;
799 omap_enable_channel_irq(cur_lch);
802 } while (next_lch != -1);
803 } else if (cpu_class_is_omap2()) {
804 /* Errata: Need to write lch even if not using chaining */
805 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
808 omap_enable_channel_irq(lch);
810 /* Errata: On ES2.0 BUFFERING disable must be set.
811 * This will always fail on ES1.0 */
812 if (cpu_is_omap24xx()) {
813 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
816 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
818 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
821 void omap_stop_dma(int lch)
823 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
824 int next_lch, cur_lch = lch;
825 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
827 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
829 /* The loop case: we've been here already */
830 if (dma_chan_link_map[cur_lch])
832 /* Mark the current channel */
833 dma_chan_link_map[cur_lch] = 1;
835 disable_lnk(cur_lch);
837 next_lch = dma_chan[cur_lch].next_lch;
839 } while (next_lch != -1);
844 /* Disable all interrupts on the channel */
845 if (cpu_class_is_omap1())
846 OMAP_DMA_CICR_REG(lch) = 0;
848 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
849 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
853 * Allows changing the DMA callback function or data. This may be needed if
854 * the driver shares a single DMA channel for multiple dma triggers.
856 int omap_set_dma_callback(int lch,
857 void (* callback)(int lch, u16 ch_status, void *data),
865 spin_lock_irqsave(&dma_chan_lock, flags);
866 if (dma_chan[lch].dev_id == -1) {
867 printk(KERN_ERR "DMA callback for not set for free channel\n");
868 spin_unlock_irqrestore(&dma_chan_lock, flags);
871 dma_chan[lch].callback = callback;
872 dma_chan[lch].data = data;
873 spin_unlock_irqrestore(&dma_chan_lock, flags);
879 * Returns current physical source address for the given DMA channel.
880 * If the channel is running the caller must disable interrupts prior calling
881 * this function and process the returned value before re-enabling interrupt to
882 * prevent races with the interrupt handler. Note that in continuous mode there
883 * is a chance for CSSA_L register overflow inbetween the two reads resulting
884 * in incorrect return value.
886 dma_addr_t omap_get_dma_src_pos(int lch)
888 dma_addr_t offset = 0;
890 if (cpu_class_is_omap1())
891 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
892 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
894 if (cpu_class_is_omap2())
895 offset = OMAP_DMA_CSAC_REG(lch);
901 * Returns current physical destination address for the given DMA channel.
902 * If the channel is running the caller must disable interrupts prior calling
903 * this function and process the returned value before re-enabling interrupt to
904 * prevent races with the interrupt handler. Note that in continuous mode there
905 * is a chance for CDSA_L register overflow inbetween the two reads resulting
906 * in incorrect return value.
908 dma_addr_t omap_get_dma_dst_pos(int lch)
910 dma_addr_t offset = 0;
912 if (cpu_class_is_omap1())
913 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
914 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
916 if (cpu_class_is_omap2())
917 offset = OMAP_DMA_CDAC_REG(lch);
923 * Returns current source transfer counting for the given DMA channel.
924 * Can be used to monitor the progress of a transfer inside a block.
925 * It must be called with disabled interrupts.
927 int omap_get_dma_src_addr_counter(int lch)
929 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
932 int omap_dma_running(void)
936 /* Check if LCD DMA is running */
937 if (cpu_is_omap16xx())
938 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
941 for (lch = 0; lch < dma_chan_count; lch++)
942 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
949 * lch_queue DMA will start right after lch_head one is finished.
950 * For this DMA link to start, you still need to start (see omap_start_dma)
951 * the first one. That will fire up the entire queue.
953 void omap_dma_link_lch (int lch_head, int lch_queue)
955 if (omap_dma_in_1510_mode()) {
956 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
961 if ((dma_chan[lch_head].dev_id == -1) ||
962 (dma_chan[lch_queue].dev_id == -1)) {
963 printk(KERN_ERR "omap_dma: trying to link "
964 "non requested channels\n");
968 dma_chan[lch_head].next_lch = lch_queue;
972 * Once the DMA queue is stopped, we can destroy it.
974 void omap_dma_unlink_lch (int lch_head, int lch_queue)
976 if (omap_dma_in_1510_mode()) {
977 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
982 if (dma_chan[lch_head].next_lch != lch_queue ||
983 dma_chan[lch_head].next_lch == -1) {
984 printk(KERN_ERR "omap_dma: trying to unlink "
985 "non linked channels\n");
990 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
991 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
992 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
993 "before unlinking\n");
997 dma_chan[lch_head].next_lch = -1;
1000 #ifndef CONFIG_ARCH_OMAP1
1001 /* Create chain of DMA channesls */
1002 static void create_dma_lch_chain(int lch_head, int lch_queue)
1006 /* Check if this is the first link in chain */
1007 if (dma_chan[lch_head].next_linked_ch == -1) {
1008 dma_chan[lch_head].next_linked_ch = lch_queue;
1009 dma_chan[lch_head].prev_linked_ch = lch_queue;
1010 dma_chan[lch_queue].next_linked_ch = lch_head;
1011 dma_chan[lch_queue].prev_linked_ch = lch_head;
1014 /* a link exists, link the new channel in circular chain */
1016 dma_chan[lch_queue].next_linked_ch =
1017 dma_chan[lch_head].next_linked_ch;
1018 dma_chan[lch_queue].prev_linked_ch = lch_head;
1019 dma_chan[lch_head].next_linked_ch = lch_queue;
1020 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1024 w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
1027 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
1029 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
1031 w |= (dma_chan[lch_queue].next_linked_ch);
1032 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
1036 * @brief omap_request_dma_chain : Request a chain of DMA channels
1038 * @param dev_id - Device id using the dma channel
1039 * @param dev_name - Device name
1040 * @param callback - Call back function
1042 * @no_of_chans - Number of channels requested
1043 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1044 * OMAP_DMA_DYNAMIC_CHAIN
1045 * @params - Channel parameters
1047 * @return - Succes : 0
1048 * Failure: -EINVAL/-ENOMEM
1050 int omap_request_dma_chain(int dev_id, const char *dev_name,
1051 void (*callback) (int chain_id, u16 ch_status,
1053 int *chain_id, int no_of_chans, int chain_mode,
1054 struct omap_dma_channel_params params)
1059 /* Is the chain mode valid ? */
1060 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1061 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1062 printk(KERN_ERR "Invalid chain mode requested\n");
1066 if (unlikely((no_of_chans < 1
1067 || no_of_chans > dma_lch_count))) {
1068 printk(KERN_ERR "Invalid Number of channels requested\n");
1072 /* Allocate a queue to maintain the status of the channels
1074 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1075 if (channels == NULL) {
1076 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1080 /* request and reserve DMA channels for the chain */
1081 for (i = 0; i < no_of_chans; i++) {
1082 err = omap_request_dma(dev_id, dev_name,
1083 callback, 0, &channels[i]);
1086 for (j = 0; j < i; j++)
1087 omap_free_dma(channels[j]);
1089 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1092 dma_chan[channels[i]].prev_linked_ch = -1;
1093 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1096 * Allowing client drivers to set common parameters now,
1097 * so that later only relevant (src_start, dest_start
1098 * and element count) can be set
1100 omap_set_dma_params(channels[i], ¶ms);
1103 *chain_id = channels[0];
1104 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1105 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1106 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1107 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1109 for (i = 0; i < no_of_chans; i++)
1110 dma_chan[channels[i]].chain_id = *chain_id;
1112 /* Reset the Queue pointers */
1113 OMAP_DMA_CHAIN_QINIT(*chain_id);
1115 /* Set up the chain */
1116 if (no_of_chans == 1)
1117 create_dma_lch_chain(channels[0], channels[0]);
1119 for (i = 0; i < (no_of_chans - 1); i++)
1120 create_dma_lch_chain(channels[i], channels[i + 1]);
1124 EXPORT_SYMBOL(omap_request_dma_chain);
1127 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1128 * params after setting it. Dont do this while dma is running!!
1130 * @param chain_id - Chained logical channel id.
1133 * @return - Success : 0
1136 int omap_modify_dma_chain_params(int chain_id,
1137 struct omap_dma_channel_params params)
1142 /* Check for input params */
1143 if (unlikely((chain_id < 0
1144 || chain_id >= dma_lch_count))) {
1145 printk(KERN_ERR "Invalid chain id\n");
1149 /* Check if the chain exists */
1150 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1151 printk(KERN_ERR "Chain doesn't exists\n");
1154 channels = dma_linked_lch[chain_id].linked_dmach_q;
1156 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1158 * Allowing client drivers to set common parameters now,
1159 * so that later only relevant (src_start, dest_start
1160 * and element count) can be set
1162 omap_set_dma_params(channels[i], ¶ms);
1166 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1169 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1173 * @return - Success : 0
1176 int omap_free_dma_chain(int chain_id)
1181 /* Check for input params */
1182 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1183 printk(KERN_ERR "Invalid chain id\n");
1187 /* Check if the chain exists */
1188 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1189 printk(KERN_ERR "Chain doesn't exists\n");
1193 channels = dma_linked_lch[chain_id].linked_dmach_q;
1194 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1195 dma_chan[channels[i]].next_linked_ch = -1;
1196 dma_chan[channels[i]].prev_linked_ch = -1;
1197 dma_chan[channels[i]].chain_id = -1;
1198 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1199 omap_free_dma(channels[i]);
1204 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1205 dma_linked_lch[chain_id].chain_mode = -1;
1206 dma_linked_lch[chain_id].chain_state = -1;
1209 EXPORT_SYMBOL(omap_free_dma_chain);
1212 * @brief omap_dma_chain_status - Check if the chain is in
1213 * active / inactive state.
1216 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1219 int omap_dma_chain_status(int chain_id)
1221 /* Check for input params */
1222 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1223 printk(KERN_ERR "Invalid chain id\n");
1227 /* Check if the chain exists */
1228 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1229 printk(KERN_ERR "Chain doesn't exists\n");
1232 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1233 dma_linked_lch[chain_id].q_count);
1235 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1236 return OMAP_DMA_CHAIN_INACTIVE;
1237 return OMAP_DMA_CHAIN_ACTIVE;
1239 EXPORT_SYMBOL(omap_dma_chain_status);
1242 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1243 * set the params and start the transfer.
1246 * @param src_start - buffer start address
1247 * @param dest_start - Dest address
1249 * @param frame_count
1250 * @param callbk_data - channel callback parameter data.
1252 * @return - Success : 0
1253 * Failure: -EINVAL/-EBUSY
1255 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1256 int elem_count, int frame_count, void *callbk_data)
1262 /* if buffer size is less than 1 then there is
1263 * no use of starting the chain */
1264 if (elem_count < 1) {
1265 printk(KERN_ERR "Invalid buffer size\n");
1269 /* Check for input params */
1270 if (unlikely((chain_id < 0
1271 || chain_id >= dma_lch_count))) {
1272 printk(KERN_ERR "Invalid chain id\n");
1276 /* Check if the chain exists */
1277 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1278 printk(KERN_ERR "Chain doesn't exist\n");
1282 /* Check if all the channels in chain are in use */
1283 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1286 /* Frame count may be negative in case of indexed transfers */
1287 channels = dma_linked_lch[chain_id].linked_dmach_q;
1289 /* Get a free channel */
1290 lch = channels[dma_linked_lch[chain_id].q_tail];
1292 /* Store the callback data */
1293 dma_chan[lch].data = callbk_data;
1295 /* Increment the q_tail */
1296 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1298 /* Set the params to the free channel */
1300 OMAP2_DMA_CSSA_REG(lch) = src_start;
1301 if (dest_start != 0)
1302 OMAP2_DMA_CDSA_REG(lch) = dest_start;
1304 /* Write the buffer size */
1305 OMAP_DMA_CEN_REG(lch) = elem_count;
1306 OMAP_DMA_CFN_REG(lch) = frame_count;
1308 /* If the chain is dynamically linked,
1309 * then we may have to start the chain if its not active */
1310 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1312 /* In Dynamic chain, if the chain is not started,
1313 * queue the channel */
1314 if (dma_linked_lch[chain_id].chain_state ==
1315 DMA_CHAIN_NOTSTARTED) {
1316 /* Enable the link in previous channel */
1317 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1319 enable_lnk(dma_chan[lch].prev_linked_ch);
1320 dma_chan[lch].state = DMA_CH_QUEUED;
1323 /* Chain is already started, make sure its active,
1324 * if not then start the chain */
1328 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1330 enable_lnk(dma_chan[lch].prev_linked_ch);
1331 dma_chan[lch].state = DMA_CH_QUEUED;
1333 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
1334 (dma_chan[lch].prev_linked_ch)))) {
1335 disable_lnk(dma_chan[lch].
1337 pr_debug("\n prev ch is stopped\n");
1342 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1344 enable_lnk(dma_chan[lch].prev_linked_ch);
1345 dma_chan[lch].state = DMA_CH_QUEUED;
1348 omap_enable_channel_irq(lch);
1350 w = OMAP_DMA_CCR_REG(lch);
1352 if ((0 == (w & (1 << 24))))
1356 if (start_dma == 1) {
1357 if (0 == (w & (1 << 7))) {
1359 dma_chan[lch].state = DMA_CH_STARTED;
1360 pr_debug("starting %d\n", lch);
1361 OMAP_DMA_CCR_REG(lch) = w;
1365 if (0 == (w & (1 << 7)))
1366 OMAP_DMA_CCR_REG(lch) = w;
1368 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1373 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1376 * @brief omap_start_dma_chain_transfers - Start the chain
1380 * @return - Success : 0
1381 * Failure : -EINVAL/-EBUSY
1383 int omap_start_dma_chain_transfers(int chain_id)
1388 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1389 printk(KERN_ERR "Invalid chain id\n");
1393 channels = dma_linked_lch[chain_id].linked_dmach_q;
1395 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1396 printk(KERN_ERR "Chain is already started\n");
1400 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1401 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1403 enable_lnk(channels[i]);
1404 omap_enable_channel_irq(channels[i]);
1407 omap_enable_channel_irq(channels[0]);
1410 w = OMAP_DMA_CCR_REG(channels[0]);
1412 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1413 dma_chan[channels[0]].state = DMA_CH_STARTED;
1415 if ((0 == (w & (1 << 24))))
1419 OMAP_DMA_CCR_REG(channels[0]) = w;
1421 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1424 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1427 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1431 * @return - Success : 0
1434 int omap_stop_dma_chain_transfers(int chain_id)
1440 /* Check for input params */
1441 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1442 printk(KERN_ERR "Invalid chain id\n");
1446 /* Check if the chain exists */
1447 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1448 printk(KERN_ERR "Chain doesn't exists\n");
1451 channels = dma_linked_lch[chain_id].linked_dmach_q;
1454 * Special programming model needed to disable DMA before end of block
1456 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
1458 /* Middle mode reg set no Standby */
1459 w &= ~((1 << 12)|(1 << 13));
1460 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
1462 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1464 /* Stop the Channel transmission */
1465 w = OMAP_DMA_CCR_REG(channels[i]);
1467 OMAP_DMA_CCR_REG(channels[i]) = w;
1469 /* Disable the link in all the channels */
1470 disable_lnk(channels[i]);
1471 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1474 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1476 /* Reset the Queue pointers */
1477 OMAP_DMA_CHAIN_QINIT(chain_id);
1479 /* Errata - put in the old value */
1480 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
1483 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1485 /* Get the index of the ongoing DMA in chain */
1487 * @brief omap_get_dma_chain_index - Get the element and frame index
1488 * of the ongoing DMA in chain
1491 * @param ei - Element index
1492 * @param fi - Frame index
1494 * @return - Success : 0
1497 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1502 /* Check for input params */
1503 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1504 printk(KERN_ERR "Invalid chain id\n");
1508 /* Check if the chain exists */
1509 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1510 printk(KERN_ERR "Chain doesn't exists\n");
1516 channels = dma_linked_lch[chain_id].linked_dmach_q;
1518 /* Get the current channel */
1519 lch = channels[dma_linked_lch[chain_id].q_head];
1521 *ei = OMAP2_DMA_CCEN_REG(lch);
1522 *fi = OMAP2_DMA_CCFN_REG(lch);
1526 EXPORT_SYMBOL(omap_get_dma_chain_index);
1529 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1530 * ongoing DMA in chain
1534 * @return - Success : Destination position
1537 int omap_get_dma_chain_dst_pos(int chain_id)
1542 /* Check for input params */
1543 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1544 printk(KERN_ERR "Invalid chain id\n");
1548 /* Check if the chain exists */
1549 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1550 printk(KERN_ERR "Chain doesn't exists\n");
1554 channels = dma_linked_lch[chain_id].linked_dmach_q;
1556 /* Get the current channel */
1557 lch = channels[dma_linked_lch[chain_id].q_head];
1559 return (OMAP_DMA_CDAC_REG(lch));
1561 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1564 * @brief omap_get_dma_chain_src_pos - Get the source position
1565 * of the ongoing DMA in chain
1568 * @return - Success : Destination position
1571 int omap_get_dma_chain_src_pos(int chain_id)
1576 /* Check for input params */
1577 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1578 printk(KERN_ERR "Invalid chain id\n");
1582 /* Check if the chain exists */
1583 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1584 printk(KERN_ERR "Chain doesn't exists\n");
1588 channels = dma_linked_lch[chain_id].linked_dmach_q;
1590 /* Get the current channel */
1591 lch = channels[dma_linked_lch[chain_id].q_head];
1593 return (OMAP_DMA_CSAC_REG(lch));
1595 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1598 /*----------------------------------------------------------------------------*/
1600 #ifdef CONFIG_ARCH_OMAP1
1602 static int omap1_dma_handle_ch(int ch)
1606 if (enable_1510_mode && ch >= 6) {
1607 csr = dma_chan[ch].saved_csr;
1608 dma_chan[ch].saved_csr = 0;
1610 csr = OMAP_DMA_CSR_REG(ch);
1611 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1612 dma_chan[ch + 6].saved_csr = csr >> 7;
1615 if ((csr & 0x3f) == 0)
1617 if (unlikely(dma_chan[ch].dev_id == -1)) {
1618 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1619 "%d (CSR %04x)\n", ch, csr);
1622 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1623 printk(KERN_WARNING "DMA timeout with device %d\n",
1624 dma_chan[ch].dev_id);
1625 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1626 printk(KERN_WARNING "DMA synchronization event drop occurred "
1627 "with device %d\n", dma_chan[ch].dev_id);
1628 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1629 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1630 if (likely(dma_chan[ch].callback != NULL))
1631 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1635 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1637 int ch = ((int) dev_id) - 1;
1641 int handled_now = 0;
1643 handled_now += omap1_dma_handle_ch(ch);
1644 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1645 handled_now += omap1_dma_handle_ch(ch + 6);
1648 handled += handled_now;
1651 return handled ? IRQ_HANDLED : IRQ_NONE;
1655 #define omap1_dma_irq_handler NULL
1658 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1660 static int omap2_dma_handle_ch(int ch)
1662 u32 status = OMAP_DMA_CSR_REG(ch);
1665 if (printk_ratelimit())
1666 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
1667 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
1670 if (unlikely(dma_chan[ch].dev_id == -1)) {
1671 if (printk_ratelimit())
1672 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1673 "channel %d\n", status, ch);
1676 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1678 "DMA synchronization event drop occurred with device "
1679 "%d\n", dma_chan[ch].dev_id);
1680 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1681 printk(KERN_INFO "DMA transaction error with device %d\n",
1682 dma_chan[ch].dev_id);
1683 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1684 printk(KERN_INFO "DMA secure error with device %d\n",
1685 dma_chan[ch].dev_id);
1686 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1687 printk(KERN_INFO "DMA misaligned error with device %d\n",
1688 dma_chan[ch].dev_id);
1690 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
1691 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
1693 /* If the ch is not chained then chain_id will be -1 */
1694 if (dma_chan[ch].chain_id != -1) {
1695 int chain_id = dma_chan[ch].chain_id;
1696 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1697 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
1698 dma_chan[dma_chan[ch].next_linked_ch].state =
1700 if (dma_linked_lch[chain_id].chain_mode ==
1701 OMAP_DMA_DYNAMIC_CHAIN)
1704 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1705 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1707 status = OMAP_DMA_CSR_REG(ch);
1710 if (likely(dma_chan[ch].callback != NULL))
1711 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1713 OMAP_DMA_CSR_REG(ch) = status;
1718 /* STATUS register count is from 1-32 while our is 0-31 */
1719 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1724 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
1726 if (printk_ratelimit())
1727 printk(KERN_WARNING "Spurious DMA IRQ\n");
1730 for (i = 0; i < dma_lch_count && val != 0; i++) {
1732 omap2_dma_handle_ch(i);
1739 static struct irqaction omap24xx_dma_irq = {
1741 .handler = omap2_dma_irq_handler,
1742 .flags = IRQF_DISABLED
1746 static struct irqaction omap24xx_dma_irq;
1749 /*----------------------------------------------------------------------------*/
1751 static struct lcd_dma_info {
1754 void (* callback)(u16 status, void *data);
1758 unsigned long addr, size;
1759 int rotate, data_type, xres, yres;
1765 int single_transfer;
1768 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1771 lcd_dma.addr = addr;
1772 lcd_dma.data_type = data_type;
1773 lcd_dma.xres = fb_xres;
1774 lcd_dma.yres = fb_yres;
1777 void omap_set_lcd_dma_src_port(int port)
1779 lcd_dma.src_port = port;
1782 void omap_set_lcd_dma_ext_controller(int external)
1784 lcd_dma.ext_ctrl = external;
1787 void omap_set_lcd_dma_single_transfer(int single)
1789 lcd_dma.single_transfer = single;
1793 void omap_set_lcd_dma_b1_rotation(int rotate)
1795 if (omap_dma_in_1510_mode()) {
1796 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1800 lcd_dma.rotate = rotate;
1803 void omap_set_lcd_dma_b1_mirror(int mirror)
1805 if (omap_dma_in_1510_mode()) {
1806 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1809 lcd_dma.mirror = mirror;
1812 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1814 if (omap_dma_in_1510_mode()) {
1815 printk(KERN_ERR "DMA virtual resulotion is not supported "
1819 lcd_dma.vxres = vxres;
1822 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1824 if (omap_dma_in_1510_mode()) {
1825 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1828 lcd_dma.xscale = xscale;
1829 lcd_dma.yscale = yscale;
1832 static void set_b1_regs(void)
1834 unsigned long top, bottom;
1837 unsigned long en, fn;
1839 unsigned long vxres;
1840 unsigned int xscale, yscale;
1842 switch (lcd_dma.data_type) {
1843 case OMAP_DMA_DATA_TYPE_S8:
1846 case OMAP_DMA_DATA_TYPE_S16:
1849 case OMAP_DMA_DATA_TYPE_S32:
1857 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1858 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1859 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1860 BUG_ON(vxres < lcd_dma.xres);
1861 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1862 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1863 switch (lcd_dma.rotate) {
1865 if (!lcd_dma.mirror) {
1866 top = PIXADDR(0, 0);
1867 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1868 /* 1510 DMA requires the bottom address to be 2 more
1869 * than the actual last memory access location. */
1870 if (omap_dma_in_1510_mode() &&
1871 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1873 ei = PIXSTEP(0, 0, 1, 0);
1874 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1876 top = PIXADDR(lcd_dma.xres - 1, 0);
1877 bottom = PIXADDR(0, lcd_dma.yres - 1);
1878 ei = PIXSTEP(1, 0, 0, 0);
1879 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1885 if (!lcd_dma.mirror) {
1886 top = PIXADDR(0, lcd_dma.yres - 1);
1887 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1888 ei = PIXSTEP(0, 1, 0, 0);
1889 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1891 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1892 bottom = PIXADDR(0, 0);
1893 ei = PIXSTEP(0, 1, 0, 0);
1894 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1900 if (!lcd_dma.mirror) {
1901 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1902 bottom = PIXADDR(0, 0);
1903 ei = PIXSTEP(1, 0, 0, 0);
1904 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1906 top = PIXADDR(0, lcd_dma.yres - 1);
1907 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1908 ei = PIXSTEP(0, 0, 1, 0);
1909 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1915 if (!lcd_dma.mirror) {
1916 top = PIXADDR(lcd_dma.xres - 1, 0);
1917 bottom = PIXADDR(0, lcd_dma.yres - 1);
1918 ei = PIXSTEP(0, 0, 0, 1);
1919 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1921 top = PIXADDR(0, 0);
1922 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1923 ei = PIXSTEP(0, 0, 0, 1);
1924 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1931 return; /* Suppress warning about uninitialized vars */
1934 if (omap_dma_in_1510_mode()) {
1935 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1936 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1937 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1938 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1944 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1945 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1946 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1947 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1949 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1950 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1952 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1954 w |= lcd_dma.data_type;
1955 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1957 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1958 /* Always set the source port as SDRAM for now*/
1960 if (lcd_dma.callback != NULL)
1961 w |= 1 << 1; /* Block interrupt enable */
1964 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1966 if (!(lcd_dma.rotate || lcd_dma.mirror ||
1967 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1970 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1971 /* Set the double-indexed addressing mode */
1973 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1975 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1976 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1977 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1980 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1984 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1985 if (unlikely(!(w & (1 << 3)))) {
1986 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1991 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1993 if (lcd_dma.callback != NULL)
1994 lcd_dma.callback(w, lcd_dma.cb_data);
1999 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2002 spin_lock_irq(&lcd_dma.lock);
2003 if (lcd_dma.reserved) {
2004 spin_unlock_irq(&lcd_dma.lock);
2005 printk(KERN_ERR "LCD DMA channel already reserved\n");
2009 lcd_dma.reserved = 1;
2010 spin_unlock_irq(&lcd_dma.lock);
2011 lcd_dma.callback = callback;
2012 lcd_dma.cb_data = data;
2014 lcd_dma.single_transfer = 0;
2020 lcd_dma.ext_ctrl = 0;
2021 lcd_dma.src_port = 0;
2026 void omap_free_lcd_dma(void)
2028 spin_lock(&lcd_dma.lock);
2029 if (!lcd_dma.reserved) {
2030 spin_unlock(&lcd_dma.lock);
2031 printk(KERN_ERR "LCD DMA is not reserved\n");
2035 if (!enable_1510_mode)
2036 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2037 OMAP1610_DMA_LCD_CCR);
2038 lcd_dma.reserved = 0;
2039 spin_unlock(&lcd_dma.lock);
2042 void omap_enable_lcd_dma(void)
2046 /* Set the Enable bit only if an external controller is
2047 * connected. Otherwise the OMAP internal controller will
2048 * start the transfer when it gets enabled.
2050 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2053 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2055 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2059 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2061 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2064 void omap_setup_lcd_dma(void)
2066 BUG_ON(lcd_dma.active);
2067 if (!enable_1510_mode) {
2068 /* Set some reasonable defaults */
2069 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2070 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2071 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2074 if (!enable_1510_mode) {
2077 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2078 /* If DMA was already active set the end_prog bit to have
2079 * the programmed register set loaded into the active
2082 w |= 1 << 11; /* End_prog */
2083 if (!lcd_dma.single_transfer)
2084 w |= (3 << 8); /* Auto_init, repeat */
2085 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2089 void omap_stop_lcd_dma(void)
2094 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2097 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2099 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2101 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2103 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2106 /*----------------------------------------------------------------------------*/
2108 static int __init omap_init_dma(void)
2112 if (cpu_class_is_omap1())
2113 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2115 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2117 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2122 if (cpu_class_is_omap2()) {
2123 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2124 dma_lch_count, GFP_KERNEL);
2125 if (!dma_linked_lch) {
2131 if (cpu_is_omap15xx()) {
2132 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2134 enable_1510_mode = 1;
2135 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2136 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2137 omap_readw(OMAP_DMA_HW_ID));
2138 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2139 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
2140 omap_readw(OMAP_DMA_CAPS_0_L),
2141 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
2142 omap_readw(OMAP_DMA_CAPS_1_L),
2143 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
2144 omap_readw(OMAP_DMA_CAPS_4));
2145 if (!enable_1510_mode) {
2148 /* Disable OMAP 3.0/3.1 compatibility mode. */
2149 w = omap_readw(OMAP_DMA_GSCR);
2151 omap_writew(w, OMAP_DMA_GSCR);
2152 dma_chan_count = 16;
2155 if (cpu_is_omap16xx()) {
2158 /* this would prevent OMAP sleep */
2159 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2161 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2163 } else if (cpu_class_is_omap2()) {
2164 u8 revision = omap_readb(OMAP_DMA4_REVISION);
2165 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2166 revision >> 4, revision & 0xf);
2167 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2173 spin_lock_init(&lcd_dma.lock);
2174 spin_lock_init(&dma_chan_lock);
2176 for (ch = 0; ch < dma_chan_count; ch++) {
2178 dma_chan[ch].dev_id = -1;
2179 dma_chan[ch].next_lch = -1;
2181 if (ch >= 6 && enable_1510_mode)
2184 if (cpu_class_is_omap1()) {
2185 /* request_irq() doesn't like dev_id (ie. ch) being
2186 * zero, so we have to kludge around this. */
2187 r = request_irq(omap1_dma_irq[ch],
2188 omap1_dma_irq_handler, 0, "DMA",
2193 printk(KERN_ERR "unable to request IRQ %d "
2194 "for DMA (error %d)\n",
2195 omap1_dma_irq[ch], r);
2196 for (i = 0; i < ch; i++)
2197 free_irq(omap1_dma_irq[i],
2204 if (cpu_is_omap2430() || cpu_is_omap34xx())
2205 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2206 DMA_DEFAULT_FIFO_DEPTH, 0);
2208 if (cpu_class_is_omap2())
2209 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2211 /* FIXME: Update LCD DMA to work on 24xx */
2212 if (cpu_class_is_omap1()) {
2213 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2218 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2220 for (i = 0; i < dma_chan_count; i++)
2221 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2229 arch_initcall(omap_init_dma);
2231 EXPORT_SYMBOL(omap_get_dma_src_pos);
2232 EXPORT_SYMBOL(omap_get_dma_dst_pos);
2233 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2234 EXPORT_SYMBOL(omap_clear_dma);
2235 EXPORT_SYMBOL(omap_set_dma_priority);
2236 EXPORT_SYMBOL(omap_request_dma);
2237 EXPORT_SYMBOL(omap_free_dma);
2238 EXPORT_SYMBOL(omap_start_dma);
2239 EXPORT_SYMBOL(omap_stop_dma);
2240 EXPORT_SYMBOL(omap_set_dma_callback);
2241 EXPORT_SYMBOL(omap_enable_dma_irq);
2242 EXPORT_SYMBOL(omap_disable_dma_irq);
2244 EXPORT_SYMBOL(omap_set_dma_transfer_params);
2245 EXPORT_SYMBOL(omap_set_dma_color_mode);
2246 EXPORT_SYMBOL(omap_set_dma_write_mode);
2248 EXPORT_SYMBOL(omap_set_dma_src_params);
2249 EXPORT_SYMBOL(omap_set_dma_src_index);
2250 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2251 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2253 EXPORT_SYMBOL(omap_set_dma_dest_params);
2254 EXPORT_SYMBOL(omap_set_dma_dest_index);
2255 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2256 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2258 EXPORT_SYMBOL(omap_set_dma_params);
2260 EXPORT_SYMBOL(omap_dma_link_lch);
2261 EXPORT_SYMBOL(omap_dma_unlink_lch);
2263 EXPORT_SYMBOL(omap_request_lcd_dma);
2264 EXPORT_SYMBOL(omap_free_lcd_dma);
2265 EXPORT_SYMBOL(omap_enable_lcd_dma);
2266 EXPORT_SYMBOL(omap_setup_lcd_dma);
2267 EXPORT_SYMBOL(omap_stop_lcd_dma);
2268 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2269 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2270 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2271 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2272 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2273 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2274 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);