2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <mach/hardware.h>
45 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
46 * channels that an instance of the SDMA IP block can support. Used
47 * to size arrays. (The actual maximum on a particular SoC may be less
48 * than this -- for example, OMAP1 SDMA instances only support 17 logical
51 #define MAX_LOGICAL_DMA_CH_COUNT 32
55 #ifndef CONFIG_ARCH_OMAP1
56 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
57 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
60 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
63 #define OMAP_DMA_ACTIVE 0x01
64 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
66 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
68 static struct omap_system_dma_plat_info *p;
69 static struct omap_dma_dev_attr *d;
71 static int enable_1510_mode;
74 static struct omap_dma_global_context_registers {
76 u32 dma_ocp_sysconfig;
78 } omap_dma_global_context;
80 struct dma_link_info {
82 int no_of_lchs_linked;
93 static struct dma_link_info *dma_linked_lch;
95 #ifndef CONFIG_ARCH_OMAP1
97 /* Chain handling macros */
98 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
100 dma_linked_lch[chain_id].q_head = \
101 dma_linked_lch[chain_id].q_tail = \
102 dma_linked_lch[chain_id].q_count = 0; \
104 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
105 (dma_linked_lch[chain_id].no_of_lchs_linked == \
106 dma_linked_lch[chain_id].q_count)
107 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
109 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
110 dma_linked_lch[chain_id].q_count) \
112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
113 (0 == dma_linked_lch[chain_id].q_count)
114 #define __OMAP_DMA_CHAIN_INCQ(end) \
115 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
119 dma_linked_lch[chain_id].q_count--; \
122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
124 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
125 dma_linked_lch[chain_id].q_count++; \
129 static int dma_lch_count;
130 static int dma_chan_count;
131 static int omap_dma_reserve_channels;
133 static spinlock_t dma_chan_lock;
134 static struct omap_dma_lch *dma_chan;
136 static inline void disable_lnk(int lch);
137 static void omap_disable_channel_irq(int lch);
138 static inline void omap_enable_channel_irq(int lch);
140 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
143 #ifdef CONFIG_ARCH_OMAP15XX
144 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
145 static int omap_dma_in_1510_mode(void)
147 return enable_1510_mode;
150 #define omap_dma_in_1510_mode() 0
153 #ifdef CONFIG_ARCH_OMAP1
154 static inline int get_gdma_dev(int req)
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
159 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
162 static inline void set_gdma_dev(int req, int dev)
164 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
165 int shift = ((req - 1) % 5) * 6;
169 l &= ~(0x3f << shift);
170 l |= (dev - 1) << shift;
174 #define set_gdma_dev(req, dev) do {} while (0)
175 #define omap_readl(reg) 0
176 #define omap_writel(val, reg) do {} while (0)
179 void omap_set_dma_priority(int lch, int dst_port, int priority)
184 if (cpu_class_is_omap1()) {
186 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
187 reg = OMAP_TC_OCPT1_PRIOR;
189 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
190 reg = OMAP_TC_OCPT2_PRIOR;
192 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
193 reg = OMAP_TC_EMIFF_PRIOR;
195 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
196 reg = OMAP_TC_EMIFS_PRIOR;
204 l |= (priority & 0xf) << 8;
208 if (cpu_class_is_omap2()) {
211 ccr = p->dma_read(CCR, lch);
216 p->dma_write(ccr, CCR, lch);
219 EXPORT_SYMBOL(omap_set_dma_priority);
221 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
222 int frame_count, int sync_mode,
223 int dma_trigger, int src_or_dst_synch)
227 l = p->dma_read(CSDP, lch);
230 p->dma_write(l, CSDP, lch);
232 if (cpu_class_is_omap1()) {
235 ccr = p->dma_read(CCR, lch);
237 if (sync_mode == OMAP_DMA_SYNC_FRAME)
239 p->dma_write(ccr, CCR, lch);
241 ccr = p->dma_read(CCR2, lch);
243 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
245 p->dma_write(ccr, CCR2, lch);
248 if (cpu_class_is_omap2() && dma_trigger) {
251 val = p->dma_read(CCR, lch);
253 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
254 val &= ~((1 << 23) | (3 << 19) | 0x1f);
255 val |= (dma_trigger & ~0x1f) << 14;
256 val |= dma_trigger & 0x1f;
258 if (sync_mode & OMAP_DMA_SYNC_FRAME)
263 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
268 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
269 val &= ~(1 << 24); /* dest synch */
270 val |= (1 << 23); /* Prefetch */
271 } else if (src_or_dst_synch) {
272 val |= 1 << 24; /* source synch */
274 val &= ~(1 << 24); /* dest synch */
276 p->dma_write(val, CCR, lch);
279 p->dma_write(elem_count, CEN, lch);
280 p->dma_write(frame_count, CFN, lch);
282 EXPORT_SYMBOL(omap_set_dma_transfer_params);
284 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
286 BUG_ON(omap_dma_in_1510_mode());
288 if (cpu_class_is_omap1()) {
291 w = p->dma_read(CCR2, lch);
295 case OMAP_DMA_CONSTANT_FILL:
298 case OMAP_DMA_TRANSPARENT_COPY:
301 case OMAP_DMA_COLOR_DIS:
306 p->dma_write(w, CCR2, lch);
308 w = p->dma_read(LCH_CTRL, lch);
310 /* Default is channel type 2D */
312 p->dma_write(color, COLOR, lch);
313 w |= 1; /* Channel type G */
315 p->dma_write(w, LCH_CTRL, lch);
318 if (cpu_class_is_omap2()) {
321 val = p->dma_read(CCR, lch);
322 val &= ~((1 << 17) | (1 << 16));
325 case OMAP_DMA_CONSTANT_FILL:
328 case OMAP_DMA_TRANSPARENT_COPY:
331 case OMAP_DMA_COLOR_DIS:
336 p->dma_write(val, CCR, lch);
339 p->dma_write(color, COLOR, lch);
342 EXPORT_SYMBOL(omap_set_dma_color_mode);
344 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
346 if (cpu_class_is_omap2()) {
349 csdp = p->dma_read(CSDP, lch);
350 csdp &= ~(0x3 << 16);
351 csdp |= (mode << 16);
352 p->dma_write(csdp, CSDP, lch);
355 EXPORT_SYMBOL(omap_set_dma_write_mode);
357 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
359 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
362 l = p->dma_read(LCH_CTRL, lch);
365 p->dma_write(l, LCH_CTRL, lch);
368 EXPORT_SYMBOL(omap_set_dma_channel_mode);
370 /* Note that src_port is only for omap1 */
371 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
372 unsigned long src_start,
373 int src_ei, int src_fi)
377 if (cpu_class_is_omap1()) {
380 w = p->dma_read(CSDP, lch);
383 p->dma_write(w, CSDP, lch);
386 l = p->dma_read(CCR, lch);
388 l |= src_amode << 12;
389 p->dma_write(l, CCR, lch);
391 p->dma_write(src_start, CSSA, lch);
393 p->dma_write(src_ei, CSEI, lch);
394 p->dma_write(src_fi, CSFI, lch);
396 EXPORT_SYMBOL(omap_set_dma_src_params);
398 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
400 omap_set_dma_transfer_params(lch, params->data_type,
401 params->elem_count, params->frame_count,
402 params->sync_mode, params->trigger,
403 params->src_or_dst_synch);
404 omap_set_dma_src_params(lch, params->src_port,
405 params->src_amode, params->src_start,
406 params->src_ei, params->src_fi);
408 omap_set_dma_dest_params(lch, params->dst_port,
409 params->dst_amode, params->dst_start,
410 params->dst_ei, params->dst_fi);
411 if (params->read_prio || params->write_prio)
412 omap_dma_set_prio_lch(lch, params->read_prio,
415 EXPORT_SYMBOL(omap_set_dma_params);
417 void omap_set_dma_src_index(int lch, int eidx, int fidx)
419 if (cpu_class_is_omap2())
422 p->dma_write(eidx, CSEI, lch);
423 p->dma_write(fidx, CSFI, lch);
425 EXPORT_SYMBOL(omap_set_dma_src_index);
427 void omap_set_dma_src_data_pack(int lch, int enable)
431 l = p->dma_read(CSDP, lch);
435 p->dma_write(l, CSDP, lch);
437 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
439 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
441 unsigned int burst = 0;
444 l = p->dma_read(CSDP, lch);
447 switch (burst_mode) {
448 case OMAP_DMA_DATA_BURST_DIS:
450 case OMAP_DMA_DATA_BURST_4:
451 if (cpu_class_is_omap2())
456 case OMAP_DMA_DATA_BURST_8:
457 if (cpu_class_is_omap2()) {
462 * not supported by current hardware on OMAP1
466 case OMAP_DMA_DATA_BURST_16:
467 if (cpu_class_is_omap2()) {
472 * OMAP1 don't support burst 16
480 p->dma_write(l, CSDP, lch);
482 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
484 /* Note that dest_port is only for OMAP1 */
485 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
486 unsigned long dest_start,
487 int dst_ei, int dst_fi)
491 if (cpu_class_is_omap1()) {
492 l = p->dma_read(CSDP, lch);
495 p->dma_write(l, CSDP, lch);
498 l = p->dma_read(CCR, lch);
500 l |= dest_amode << 14;
501 p->dma_write(l, CCR, lch);
503 p->dma_write(dest_start, CDSA, lch);
505 p->dma_write(dst_ei, CDEI, lch);
506 p->dma_write(dst_fi, CDFI, lch);
508 EXPORT_SYMBOL(omap_set_dma_dest_params);
510 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
512 if (cpu_class_is_omap2())
515 p->dma_write(eidx, CDEI, lch);
516 p->dma_write(fidx, CDFI, lch);
518 EXPORT_SYMBOL(omap_set_dma_dest_index);
520 void omap_set_dma_dest_data_pack(int lch, int enable)
524 l = p->dma_read(CSDP, lch);
528 p->dma_write(l, CSDP, lch);
530 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
532 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
534 unsigned int burst = 0;
537 l = p->dma_read(CSDP, lch);
540 switch (burst_mode) {
541 case OMAP_DMA_DATA_BURST_DIS:
543 case OMAP_DMA_DATA_BURST_4:
544 if (cpu_class_is_omap2())
549 case OMAP_DMA_DATA_BURST_8:
550 if (cpu_class_is_omap2())
555 case OMAP_DMA_DATA_BURST_16:
556 if (cpu_class_is_omap2()) {
561 * OMAP1 don't support burst 16
565 printk(KERN_ERR "Invalid DMA burst mode\n");
570 p->dma_write(l, CSDP, lch);
572 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
574 static inline void omap_enable_channel_irq(int lch)
579 if (cpu_class_is_omap1())
580 status = p->dma_read(CSR, lch);
581 else if (cpu_class_is_omap2())
582 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
584 /* Enable some nice interrupts. */
585 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
588 static void omap_disable_channel_irq(int lch)
590 if (cpu_class_is_omap2())
591 p->dma_write(0, CICR, lch);
594 void omap_enable_dma_irq(int lch, u16 bits)
596 dma_chan[lch].enabled_irqs |= bits;
598 EXPORT_SYMBOL(omap_enable_dma_irq);
600 void omap_disable_dma_irq(int lch, u16 bits)
602 dma_chan[lch].enabled_irqs &= ~bits;
604 EXPORT_SYMBOL(omap_disable_dma_irq);
606 static inline void enable_lnk(int lch)
610 l = p->dma_read(CLNK_CTRL, lch);
612 if (cpu_class_is_omap1())
615 /* Set the ENABLE_LNK bits */
616 if (dma_chan[lch].next_lch != -1)
617 l = dma_chan[lch].next_lch | (1 << 15);
619 #ifndef CONFIG_ARCH_OMAP1
620 if (cpu_class_is_omap2())
621 if (dma_chan[lch].next_linked_ch != -1)
622 l = dma_chan[lch].next_linked_ch | (1 << 15);
625 p->dma_write(l, CLNK_CTRL, lch);
628 static inline void disable_lnk(int lch)
632 l = p->dma_read(CLNK_CTRL, lch);
634 /* Disable interrupts */
635 if (cpu_class_is_omap1()) {
636 p->dma_write(0, CICR, lch);
637 /* Set the STOP_LNK bit */
641 if (cpu_class_is_omap2()) {
642 omap_disable_channel_irq(lch);
643 /* Clear the ENABLE_LNK bit */
647 p->dma_write(l, CLNK_CTRL, lch);
648 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
651 static inline void omap2_enable_irq_lch(int lch)
656 if (!cpu_class_is_omap2())
659 spin_lock_irqsave(&dma_chan_lock, flags);
660 val = p->dma_read(IRQENABLE_L0, lch);
662 p->dma_write(val, IRQENABLE_L0, lch);
663 spin_unlock_irqrestore(&dma_chan_lock, flags);
666 static inline void omap2_disable_irq_lch(int lch)
671 if (!cpu_class_is_omap2())
674 spin_lock_irqsave(&dma_chan_lock, flags);
675 val = p->dma_read(IRQENABLE_L0, lch);
677 p->dma_write(val, IRQENABLE_L0, lch);
678 spin_unlock_irqrestore(&dma_chan_lock, flags);
681 int omap_request_dma(int dev_id, const char *dev_name,
682 void (*callback)(int lch, u16 ch_status, void *data),
683 void *data, int *dma_ch_out)
685 int ch, free_ch = -1;
687 struct omap_dma_lch *chan;
689 spin_lock_irqsave(&dma_chan_lock, flags);
690 for (ch = 0; ch < dma_chan_count; ch++) {
691 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
698 spin_unlock_irqrestore(&dma_chan_lock, flags);
701 chan = dma_chan + free_ch;
702 chan->dev_id = dev_id;
704 if (p->clear_lch_regs)
705 p->clear_lch_regs(free_ch);
707 if (cpu_class_is_omap2())
708 omap_clear_dma(free_ch);
710 spin_unlock_irqrestore(&dma_chan_lock, flags);
712 chan->dev_name = dev_name;
713 chan->callback = callback;
717 #ifndef CONFIG_ARCH_OMAP1
718 if (cpu_class_is_omap2()) {
720 chan->next_linked_ch = -1;
724 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
726 if (cpu_class_is_omap1())
727 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
728 else if (cpu_class_is_omap2())
729 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
730 OMAP2_DMA_TRANS_ERR_IRQ;
732 if (cpu_is_omap16xx()) {
733 /* If the sync device is set, configure it dynamically. */
735 set_gdma_dev(free_ch + 1, dev_id);
736 dev_id = free_ch + 1;
739 * Disable the 1510 compatibility mode and set the sync device
742 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
743 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
744 p->dma_write(dev_id, CCR, free_ch);
747 if (cpu_class_is_omap2()) {
748 omap2_enable_irq_lch(free_ch);
749 omap_enable_channel_irq(free_ch);
750 /* Clear the CSR register and IRQ status register */
751 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
752 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
755 *dma_ch_out = free_ch;
759 EXPORT_SYMBOL(omap_request_dma);
761 void omap_free_dma(int lch)
765 if (dma_chan[lch].dev_id == -1) {
766 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
771 if (cpu_class_is_omap1()) {
772 /* Disable all DMA interrupts for the channel. */
773 p->dma_write(0, CICR, lch);
774 /* Make sure the DMA transfer is stopped. */
775 p->dma_write(0, CCR, lch);
778 if (cpu_class_is_omap2()) {
779 omap2_disable_irq_lch(lch);
781 /* Clear the CSR register and IRQ status register */
782 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
783 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
785 /* Disable all DMA interrupts for the channel. */
786 p->dma_write(0, CICR, lch);
788 /* Make sure the DMA transfer is stopped. */
789 p->dma_write(0, CCR, lch);
793 spin_lock_irqsave(&dma_chan_lock, flags);
794 dma_chan[lch].dev_id = -1;
795 dma_chan[lch].next_lch = -1;
796 dma_chan[lch].callback = NULL;
797 spin_unlock_irqrestore(&dma_chan_lock, flags);
799 EXPORT_SYMBOL(omap_free_dma);
802 * @brief omap_dma_set_global_params : Set global priority settings for dma
805 * @param max_fifo_depth
806 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
807 * DMA_THREAD_RESERVE_ONET
808 * DMA_THREAD_RESERVE_TWOT
809 * DMA_THREAD_RESERVE_THREET
812 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
816 if (!cpu_class_is_omap2()) {
817 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
821 if (max_fifo_depth == 0)
826 reg = 0xff & max_fifo_depth;
827 reg |= (0x3 & tparams) << 12;
828 reg |= (arb_rate & 0xff) << 16;
830 p->dma_write(reg, GCR, 0);
832 EXPORT_SYMBOL(omap_dma_set_global_params);
835 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
838 * @param read_prio - Read priority
839 * @param write_prio - Write priority
840 * Both of the above can be set with one of the following values :
841 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
844 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
845 unsigned char write_prio)
849 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
850 printk(KERN_ERR "Invalid channel id\n");
853 l = p->dma_read(CCR, lch);
854 l &= ~((1 << 6) | (1 << 26));
855 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
856 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
858 l |= ((read_prio & 0x1) << 6);
860 p->dma_write(l, CCR, lch);
864 EXPORT_SYMBOL(omap_dma_set_prio_lch);
867 * Clears any DMA state so the DMA engine is ready to restart with new buffers
868 * through omap_start_dma(). Any buffers in flight are discarded.
870 void omap_clear_dma(int lch)
874 local_irq_save(flags);
876 local_irq_restore(flags);
878 EXPORT_SYMBOL(omap_clear_dma);
880 void omap_start_dma(int lch)
885 * The CPC/CDAC register needs to be initialized to zero
886 * before starting dma transfer.
888 if (cpu_is_omap15xx())
889 p->dma_write(0, CPC, lch);
891 p->dma_write(0, CDAC, lch);
893 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
894 int next_lch, cur_lch;
895 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
897 dma_chan_link_map[lch] = 1;
898 /* Set the link register of the first channel */
901 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
902 cur_lch = dma_chan[lch].next_lch;
904 next_lch = dma_chan[cur_lch].next_lch;
906 /* The loop case: we've been here already */
907 if (dma_chan_link_map[cur_lch])
909 /* Mark the current channel */
910 dma_chan_link_map[cur_lch] = 1;
913 omap_enable_channel_irq(cur_lch);
916 } while (next_lch != -1);
917 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
918 p->dma_write(lch, CLNK_CTRL, lch);
920 omap_enable_channel_irq(lch);
922 l = p->dma_read(CCR, lch);
924 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
925 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
926 l |= OMAP_DMA_CCR_EN;
929 * As dma_write() uses IO accessors which are weakly ordered, there
930 * is no guarantee that data in coherent DMA memory will be visible
931 * to the DMA device. Add a memory barrier here to ensure that any
932 * such data is visible prior to enabling DMA.
935 p->dma_write(l, CCR, lch);
937 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
939 EXPORT_SYMBOL(omap_start_dma);
941 void omap_stop_dma(int lch)
945 /* Disable all interrupts on the channel */
946 if (cpu_class_is_omap1())
947 p->dma_write(0, CICR, lch);
949 l = p->dma_read(CCR, lch);
950 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
951 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
955 /* Configure No-Standby */
956 l = p->dma_read(OCP_SYSCONFIG, lch);
958 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
959 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
960 p->dma_write(l , OCP_SYSCONFIG, 0);
962 l = p->dma_read(CCR, lch);
963 l &= ~OMAP_DMA_CCR_EN;
964 p->dma_write(l, CCR, lch);
966 /* Wait for sDMA FIFO drain */
967 l = p->dma_read(CCR, lch);
968 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
969 OMAP_DMA_CCR_WR_ACTIVE))) {
972 l = p->dma_read(CCR, lch);
975 printk(KERN_ERR "DMA drain did not complete on "
977 /* Restore OCP_SYSCONFIG */
978 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
980 l &= ~OMAP_DMA_CCR_EN;
981 p->dma_write(l, CCR, lch);
985 * Ensure that data transferred by DMA is visible to any access
986 * after DMA has been disabled. This is important for coherent
991 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
992 int next_lch, cur_lch = lch;
993 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
995 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
997 /* The loop case: we've been here already */
998 if (dma_chan_link_map[cur_lch])
1000 /* Mark the current channel */
1001 dma_chan_link_map[cur_lch] = 1;
1003 disable_lnk(cur_lch);
1005 next_lch = dma_chan[cur_lch].next_lch;
1007 } while (next_lch != -1);
1010 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1012 EXPORT_SYMBOL(omap_stop_dma);
1015 * Allows changing the DMA callback function or data. This may be needed if
1016 * the driver shares a single DMA channel for multiple dma triggers.
1018 int omap_set_dma_callback(int lch,
1019 void (*callback)(int lch, u16 ch_status, void *data),
1022 unsigned long flags;
1027 spin_lock_irqsave(&dma_chan_lock, flags);
1028 if (dma_chan[lch].dev_id == -1) {
1029 printk(KERN_ERR "DMA callback for not set for free channel\n");
1030 spin_unlock_irqrestore(&dma_chan_lock, flags);
1033 dma_chan[lch].callback = callback;
1034 dma_chan[lch].data = data;
1035 spin_unlock_irqrestore(&dma_chan_lock, flags);
1039 EXPORT_SYMBOL(omap_set_dma_callback);
1042 * Returns current physical source address for the given DMA channel.
1043 * If the channel is running the caller must disable interrupts prior calling
1044 * this function and process the returned value before re-enabling interrupt to
1045 * prevent races with the interrupt handler. Note that in continuous mode there
1046 * is a chance for CSSA_L register overflow between the two reads resulting
1047 * in incorrect return value.
1049 dma_addr_t omap_get_dma_src_pos(int lch)
1051 dma_addr_t offset = 0;
1053 if (cpu_is_omap15xx())
1054 offset = p->dma_read(CPC, lch);
1056 offset = p->dma_read(CSAC, lch);
1058 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1059 offset = p->dma_read(CSAC, lch);
1061 if (!cpu_is_omap15xx()) {
1063 * CDAC == 0 indicates that the DMA transfer on the channel has
1064 * not been started (no data has been transferred so far).
1065 * Return the programmed source start address in this case.
1067 if (likely(p->dma_read(CDAC, lch)))
1068 offset = p->dma_read(CSAC, lch);
1070 offset = p->dma_read(CSSA, lch);
1073 if (cpu_class_is_omap1())
1074 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1078 EXPORT_SYMBOL(omap_get_dma_src_pos);
1081 * Returns current physical destination address for the given DMA channel.
1082 * If the channel is running the caller must disable interrupts prior calling
1083 * this function and process the returned value before re-enabling interrupt to
1084 * prevent races with the interrupt handler. Note that in continuous mode there
1085 * is a chance for CDSA_L register overflow between the two reads resulting
1086 * in incorrect return value.
1088 dma_addr_t omap_get_dma_dst_pos(int lch)
1090 dma_addr_t offset = 0;
1092 if (cpu_is_omap15xx())
1093 offset = p->dma_read(CPC, lch);
1095 offset = p->dma_read(CDAC, lch);
1098 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1099 * read before the DMA controller finished disabling the channel.
1101 if (!cpu_is_omap15xx() && offset == 0) {
1102 offset = p->dma_read(CDAC, lch);
1104 * CDAC == 0 indicates that the DMA transfer on the channel has
1105 * not been started (no data has been transferred so far).
1106 * Return the programmed destination start address in this case.
1108 if (unlikely(!offset))
1109 offset = p->dma_read(CDSA, lch);
1112 if (cpu_class_is_omap1())
1113 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1117 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1119 int omap_get_dma_active_status(int lch)
1121 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1123 EXPORT_SYMBOL(omap_get_dma_active_status);
1125 int omap_dma_running(void)
1129 if (cpu_class_is_omap1())
1130 if (omap_lcd_dma_running())
1133 for (lch = 0; lch < dma_chan_count; lch++)
1134 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1141 * lch_queue DMA will start right after lch_head one is finished.
1142 * For this DMA link to start, you still need to start (see omap_start_dma)
1143 * the first one. That will fire up the entire queue.
1145 void omap_dma_link_lch(int lch_head, int lch_queue)
1147 if (omap_dma_in_1510_mode()) {
1148 if (lch_head == lch_queue) {
1149 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1153 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1158 if ((dma_chan[lch_head].dev_id == -1) ||
1159 (dma_chan[lch_queue].dev_id == -1)) {
1160 printk(KERN_ERR "omap_dma: trying to link "
1161 "non requested channels\n");
1165 dma_chan[lch_head].next_lch = lch_queue;
1167 EXPORT_SYMBOL(omap_dma_link_lch);
1170 * Once the DMA queue is stopped, we can destroy it.
1172 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1174 if (omap_dma_in_1510_mode()) {
1175 if (lch_head == lch_queue) {
1176 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1180 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1185 if (dma_chan[lch_head].next_lch != lch_queue ||
1186 dma_chan[lch_head].next_lch == -1) {
1187 printk(KERN_ERR "omap_dma: trying to unlink "
1188 "non linked channels\n");
1192 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1193 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1194 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1195 "before unlinking\n");
1199 dma_chan[lch_head].next_lch = -1;
1201 EXPORT_SYMBOL(omap_dma_unlink_lch);
1203 #ifndef CONFIG_ARCH_OMAP1
1204 /* Create chain of DMA channesls */
1205 static void create_dma_lch_chain(int lch_head, int lch_queue)
1209 /* Check if this is the first link in chain */
1210 if (dma_chan[lch_head].next_linked_ch == -1) {
1211 dma_chan[lch_head].next_linked_ch = lch_queue;
1212 dma_chan[lch_head].prev_linked_ch = lch_queue;
1213 dma_chan[lch_queue].next_linked_ch = lch_head;
1214 dma_chan[lch_queue].prev_linked_ch = lch_head;
1217 /* a link exists, link the new channel in circular chain */
1219 dma_chan[lch_queue].next_linked_ch =
1220 dma_chan[lch_head].next_linked_ch;
1221 dma_chan[lch_queue].prev_linked_ch = lch_head;
1222 dma_chan[lch_head].next_linked_ch = lch_queue;
1223 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1227 l = p->dma_read(CLNK_CTRL, lch_head);
1230 p->dma_write(l, CLNK_CTRL, lch_head);
1232 l = p->dma_read(CLNK_CTRL, lch_queue);
1234 l |= (dma_chan[lch_queue].next_linked_ch);
1235 p->dma_write(l, CLNK_CTRL, lch_queue);
1239 * @brief omap_request_dma_chain : Request a chain of DMA channels
1241 * @param dev_id - Device id using the dma channel
1242 * @param dev_name - Device name
1243 * @param callback - Call back function
1245 * @no_of_chans - Number of channels requested
1246 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1247 * OMAP_DMA_DYNAMIC_CHAIN
1248 * @params - Channel parameters
1250 * @return - Success : 0
1251 * Failure: -EINVAL/-ENOMEM
1253 int omap_request_dma_chain(int dev_id, const char *dev_name,
1254 void (*callback) (int lch, u16 ch_status,
1256 int *chain_id, int no_of_chans, int chain_mode,
1257 struct omap_dma_channel_params params)
1262 /* Is the chain mode valid ? */
1263 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1264 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1265 printk(KERN_ERR "Invalid chain mode requested\n");
1269 if (unlikely((no_of_chans < 1
1270 || no_of_chans > dma_lch_count))) {
1271 printk(KERN_ERR "Invalid Number of channels requested\n");
1276 * Allocate a queue to maintain the status of the channels
1279 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1280 if (channels == NULL) {
1281 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1285 /* request and reserve DMA channels for the chain */
1286 for (i = 0; i < no_of_chans; i++) {
1287 err = omap_request_dma(dev_id, dev_name,
1288 callback, NULL, &channels[i]);
1291 for (j = 0; j < i; j++)
1292 omap_free_dma(channels[j]);
1294 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1297 dma_chan[channels[i]].prev_linked_ch = -1;
1298 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1301 * Allowing client drivers to set common parameters now,
1302 * so that later only relevant (src_start, dest_start
1303 * and element count) can be set
1305 omap_set_dma_params(channels[i], ¶ms);
1308 *chain_id = channels[0];
1309 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1310 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1311 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1312 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1314 for (i = 0; i < no_of_chans; i++)
1315 dma_chan[channels[i]].chain_id = *chain_id;
1317 /* Reset the Queue pointers */
1318 OMAP_DMA_CHAIN_QINIT(*chain_id);
1320 /* Set up the chain */
1321 if (no_of_chans == 1)
1322 create_dma_lch_chain(channels[0], channels[0]);
1324 for (i = 0; i < (no_of_chans - 1); i++)
1325 create_dma_lch_chain(channels[i], channels[i + 1]);
1330 EXPORT_SYMBOL(omap_request_dma_chain);
1333 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1334 * params after setting it. Dont do this while dma is running!!
1336 * @param chain_id - Chained logical channel id.
1339 * @return - Success : 0
1342 int omap_modify_dma_chain_params(int chain_id,
1343 struct omap_dma_channel_params params)
1348 /* Check for input params */
1349 if (unlikely((chain_id < 0
1350 || chain_id >= dma_lch_count))) {
1351 printk(KERN_ERR "Invalid chain id\n");
1355 /* Check if the chain exists */
1356 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1357 printk(KERN_ERR "Chain doesn't exists\n");
1360 channels = dma_linked_lch[chain_id].linked_dmach_q;
1362 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1364 * Allowing client drivers to set common parameters now,
1365 * so that later only relevant (src_start, dest_start
1366 * and element count) can be set
1368 omap_set_dma_params(channels[i], ¶ms);
1373 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1376 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1380 * @return - Success : 0
1383 int omap_free_dma_chain(int chain_id)
1388 /* Check for input params */
1389 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1390 printk(KERN_ERR "Invalid chain id\n");
1394 /* Check if the chain exists */
1395 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1396 printk(KERN_ERR "Chain doesn't exists\n");
1400 channels = dma_linked_lch[chain_id].linked_dmach_q;
1401 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1402 dma_chan[channels[i]].next_linked_ch = -1;
1403 dma_chan[channels[i]].prev_linked_ch = -1;
1404 dma_chan[channels[i]].chain_id = -1;
1405 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1406 omap_free_dma(channels[i]);
1411 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1412 dma_linked_lch[chain_id].chain_mode = -1;
1413 dma_linked_lch[chain_id].chain_state = -1;
1417 EXPORT_SYMBOL(omap_free_dma_chain);
1420 * @brief omap_dma_chain_status - Check if the chain is in
1421 * active / inactive state.
1424 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1427 int omap_dma_chain_status(int chain_id)
1429 /* Check for input params */
1430 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1431 printk(KERN_ERR "Invalid chain id\n");
1435 /* Check if the chain exists */
1436 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1437 printk(KERN_ERR "Chain doesn't exists\n");
1440 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1441 dma_linked_lch[chain_id].q_count);
1443 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1444 return OMAP_DMA_CHAIN_INACTIVE;
1446 return OMAP_DMA_CHAIN_ACTIVE;
1448 EXPORT_SYMBOL(omap_dma_chain_status);
1451 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1452 * set the params and start the transfer.
1455 * @param src_start - buffer start address
1456 * @param dest_start - Dest address
1458 * @param frame_count
1459 * @param callbk_data - channel callback parameter data.
1461 * @return - Success : 0
1462 * Failure: -EINVAL/-EBUSY
1464 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1465 int elem_count, int frame_count, void *callbk_data)
1472 * if buffer size is less than 1 then there is
1473 * no use of starting the chain
1475 if (elem_count < 1) {
1476 printk(KERN_ERR "Invalid buffer size\n");
1480 /* Check for input params */
1481 if (unlikely((chain_id < 0
1482 || chain_id >= dma_lch_count))) {
1483 printk(KERN_ERR "Invalid chain id\n");
1487 /* Check if the chain exists */
1488 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1489 printk(KERN_ERR "Chain doesn't exist\n");
1493 /* Check if all the channels in chain are in use */
1494 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1497 /* Frame count may be negative in case of indexed transfers */
1498 channels = dma_linked_lch[chain_id].linked_dmach_q;
1500 /* Get a free channel */
1501 lch = channels[dma_linked_lch[chain_id].q_tail];
1503 /* Store the callback data */
1504 dma_chan[lch].data = callbk_data;
1506 /* Increment the q_tail */
1507 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1509 /* Set the params to the free channel */
1511 p->dma_write(src_start, CSSA, lch);
1512 if (dest_start != 0)
1513 p->dma_write(dest_start, CDSA, lch);
1515 /* Write the buffer size */
1516 p->dma_write(elem_count, CEN, lch);
1517 p->dma_write(frame_count, CFN, lch);
1520 * If the chain is dynamically linked,
1521 * then we may have to start the chain if its not active
1523 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1526 * In Dynamic chain, if the chain is not started,
1529 if (dma_linked_lch[chain_id].chain_state ==
1530 DMA_CHAIN_NOTSTARTED) {
1531 /* Enable the link in previous channel */
1532 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1534 enable_lnk(dma_chan[lch].prev_linked_ch);
1535 dma_chan[lch].state = DMA_CH_QUEUED;
1539 * Chain is already started, make sure its active,
1540 * if not then start the chain
1545 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1547 enable_lnk(dma_chan[lch].prev_linked_ch);
1548 dma_chan[lch].state = DMA_CH_QUEUED;
1550 if (0 == ((1 << 7) & p->dma_read(
1551 CCR, dma_chan[lch].prev_linked_ch))) {
1552 disable_lnk(dma_chan[lch].
1554 pr_debug("\n prev ch is stopped\n");
1559 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1561 enable_lnk(dma_chan[lch].prev_linked_ch);
1562 dma_chan[lch].state = DMA_CH_QUEUED;
1565 omap_enable_channel_irq(lch);
1567 l = p->dma_read(CCR, lch);
1569 if ((0 == (l & (1 << 24))))
1573 if (start_dma == 1) {
1574 if (0 == (l & (1 << 7))) {
1576 dma_chan[lch].state = DMA_CH_STARTED;
1577 pr_debug("starting %d\n", lch);
1578 p->dma_write(l, CCR, lch);
1582 if (0 == (l & (1 << 7)))
1583 p->dma_write(l, CCR, lch);
1585 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1591 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1594 * @brief omap_start_dma_chain_transfers - Start the chain
1598 * @return - Success : 0
1599 * Failure : -EINVAL/-EBUSY
1601 int omap_start_dma_chain_transfers(int chain_id)
1606 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1607 printk(KERN_ERR "Invalid chain id\n");
1611 channels = dma_linked_lch[chain_id].linked_dmach_q;
1613 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1614 printk(KERN_ERR "Chain is already started\n");
1618 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1619 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1621 enable_lnk(channels[i]);
1622 omap_enable_channel_irq(channels[i]);
1625 omap_enable_channel_irq(channels[0]);
1628 l = p->dma_read(CCR, channels[0]);
1630 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1631 dma_chan[channels[0]].state = DMA_CH_STARTED;
1633 if ((0 == (l & (1 << 24))))
1637 p->dma_write(l, CCR, channels[0]);
1639 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1643 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1646 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1650 * @return - Success : 0
1653 int omap_stop_dma_chain_transfers(int chain_id)
1659 /* Check for input params */
1660 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1661 printk(KERN_ERR "Invalid chain id\n");
1665 /* Check if the chain exists */
1666 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1667 printk(KERN_ERR "Chain doesn't exists\n");
1670 channels = dma_linked_lch[chain_id].linked_dmach_q;
1672 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1673 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1675 /* Middle mode reg set no Standby */
1676 l &= ~((1 << 12)|(1 << 13));
1677 p->dma_write(l, OCP_SYSCONFIG, 0);
1680 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1682 /* Stop the Channel transmission */
1683 l = p->dma_read(CCR, channels[i]);
1685 p->dma_write(l, CCR, channels[i]);
1687 /* Disable the link in all the channels */
1688 disable_lnk(channels[i]);
1689 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1692 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1694 /* Reset the Queue pointers */
1695 OMAP_DMA_CHAIN_QINIT(chain_id);
1697 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1698 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1702 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1704 /* Get the index of the ongoing DMA in chain */
1706 * @brief omap_get_dma_chain_index - Get the element and frame index
1707 * of the ongoing DMA in chain
1710 * @param ei - Element index
1711 * @param fi - Frame index
1713 * @return - Success : 0
1716 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1721 /* Check for input params */
1722 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1723 printk(KERN_ERR "Invalid chain id\n");
1727 /* Check if the chain exists */
1728 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1729 printk(KERN_ERR "Chain doesn't exists\n");
1735 channels = dma_linked_lch[chain_id].linked_dmach_q;
1737 /* Get the current channel */
1738 lch = channels[dma_linked_lch[chain_id].q_head];
1740 *ei = p->dma_read(CCEN, lch);
1741 *fi = p->dma_read(CCFN, lch);
1745 EXPORT_SYMBOL(omap_get_dma_chain_index);
1748 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1749 * ongoing DMA in chain
1753 * @return - Success : Destination position
1756 int omap_get_dma_chain_dst_pos(int chain_id)
1761 /* Check for input params */
1762 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1763 printk(KERN_ERR "Invalid chain id\n");
1767 /* Check if the chain exists */
1768 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1769 printk(KERN_ERR "Chain doesn't exists\n");
1773 channels = dma_linked_lch[chain_id].linked_dmach_q;
1775 /* Get the current channel */
1776 lch = channels[dma_linked_lch[chain_id].q_head];
1778 return p->dma_read(CDAC, lch);
1780 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1783 * @brief omap_get_dma_chain_src_pos - Get the source position
1784 * of the ongoing DMA in chain
1787 * @return - Success : Destination position
1790 int omap_get_dma_chain_src_pos(int chain_id)
1795 /* Check for input params */
1796 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1797 printk(KERN_ERR "Invalid chain id\n");
1801 /* Check if the chain exists */
1802 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1803 printk(KERN_ERR "Chain doesn't exists\n");
1807 channels = dma_linked_lch[chain_id].linked_dmach_q;
1809 /* Get the current channel */
1810 lch = channels[dma_linked_lch[chain_id].q_head];
1812 return p->dma_read(CSAC, lch);
1814 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1815 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1817 /*----------------------------------------------------------------------------*/
1819 #ifdef CONFIG_ARCH_OMAP1
1821 static int omap1_dma_handle_ch(int ch)
1825 if (enable_1510_mode && ch >= 6) {
1826 csr = dma_chan[ch].saved_csr;
1827 dma_chan[ch].saved_csr = 0;
1829 csr = p->dma_read(CSR, ch);
1830 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1831 dma_chan[ch + 6].saved_csr = csr >> 7;
1834 if ((csr & 0x3f) == 0)
1836 if (unlikely(dma_chan[ch].dev_id == -1)) {
1837 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1838 "%d (CSR %04x)\n", ch, csr);
1841 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1842 printk(KERN_WARNING "DMA timeout with device %d\n",
1843 dma_chan[ch].dev_id);
1844 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1845 printk(KERN_WARNING "DMA synchronization event drop occurred "
1846 "with device %d\n", dma_chan[ch].dev_id);
1847 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1848 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1849 if (likely(dma_chan[ch].callback != NULL))
1850 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1855 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1857 int ch = ((int) dev_id) - 1;
1861 int handled_now = 0;
1863 handled_now += omap1_dma_handle_ch(ch);
1864 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1865 handled_now += omap1_dma_handle_ch(ch + 6);
1868 handled += handled_now;
1871 return handled ? IRQ_HANDLED : IRQ_NONE;
1875 #define omap1_dma_irq_handler NULL
1878 #ifdef CONFIG_ARCH_OMAP2PLUS
1880 static int omap2_dma_handle_ch(int ch)
1882 u32 status = p->dma_read(CSR, ch);
1885 if (printk_ratelimit())
1886 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1888 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1891 if (unlikely(dma_chan[ch].dev_id == -1)) {
1892 if (printk_ratelimit())
1893 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1894 "channel %d\n", status, ch);
1897 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1899 "DMA synchronization event drop occurred with device "
1900 "%d\n", dma_chan[ch].dev_id);
1901 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1902 printk(KERN_INFO "DMA transaction error with device %d\n",
1903 dma_chan[ch].dev_id);
1904 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1907 ccr = p->dma_read(CCR, ch);
1908 ccr &= ~OMAP_DMA_CCR_EN;
1909 p->dma_write(ccr, CCR, ch);
1910 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1913 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1914 printk(KERN_INFO "DMA secure error with device %d\n",
1915 dma_chan[ch].dev_id);
1916 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1917 printk(KERN_INFO "DMA misaligned error with device %d\n",
1918 dma_chan[ch].dev_id);
1920 p->dma_write(status, CSR, ch);
1921 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1922 /* read back the register to flush the write */
1923 p->dma_read(IRQSTATUS_L0, ch);
1925 /* If the ch is not chained then chain_id will be -1 */
1926 if (dma_chan[ch].chain_id != -1) {
1927 int chain_id = dma_chan[ch].chain_id;
1928 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1929 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1930 dma_chan[dma_chan[ch].next_linked_ch].state =
1932 if (dma_linked_lch[chain_id].chain_mode ==
1933 OMAP_DMA_DYNAMIC_CHAIN)
1936 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1937 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1939 status = p->dma_read(CSR, ch);
1940 p->dma_write(status, CSR, ch);
1943 if (likely(dma_chan[ch].callback != NULL))
1944 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1949 /* STATUS register count is from 1-32 while our is 0-31 */
1950 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1952 u32 val, enable_reg;
1955 val = p->dma_read(IRQSTATUS_L0, 0);
1957 if (printk_ratelimit())
1958 printk(KERN_WARNING "Spurious DMA IRQ\n");
1961 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1962 val &= enable_reg; /* Dispatch only relevant interrupts */
1963 for (i = 0; i < dma_lch_count && val != 0; i++) {
1965 omap2_dma_handle_ch(i);
1972 static struct irqaction omap24xx_dma_irq = {
1974 .handler = omap2_dma_irq_handler,
1975 .flags = IRQF_DISABLED
1979 static struct irqaction omap24xx_dma_irq;
1982 /*----------------------------------------------------------------------------*/
1984 void omap_dma_global_context_save(void)
1986 omap_dma_global_context.dma_irqenable_l0 =
1987 p->dma_read(IRQENABLE_L0, 0);
1988 omap_dma_global_context.dma_ocp_sysconfig =
1989 p->dma_read(OCP_SYSCONFIG, 0);
1990 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1993 void omap_dma_global_context_restore(void)
1997 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1998 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2000 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
2003 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
2004 p->dma_write(0x3 , IRQSTATUS_L0, 0);
2006 for (ch = 0; ch < dma_chan_count; ch++)
2007 if (dma_chan[ch].dev_id != -1)
2011 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2018 p = pdev->dev.platform_data;
2020 dev_err(&pdev->dev, "%s: System DMA initialized without"
2021 "platform data\n", __func__);
2028 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2029 && (omap_dma_reserve_channels <= dma_lch_count))
2030 d->lch_count = omap_dma_reserve_channels;
2032 dma_lch_count = d->lch_count;
2033 dma_chan_count = dma_lch_count;
2035 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2037 if (cpu_class_is_omap2()) {
2038 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2039 dma_lch_count, GFP_KERNEL);
2040 if (!dma_linked_lch) {
2042 goto exit_dma_lch_fail;
2046 spin_lock_init(&dma_chan_lock);
2047 for (ch = 0; ch < dma_chan_count; ch++) {
2049 if (cpu_class_is_omap2())
2050 omap2_disable_irq_lch(ch);
2052 dma_chan[ch].dev_id = -1;
2053 dma_chan[ch].next_lch = -1;
2055 if (ch >= 6 && enable_1510_mode)
2058 if (cpu_class_is_omap1()) {
2060 * request_irq() doesn't like dev_id (ie. ch) being
2061 * zero, so we have to kludge around this.
2063 sprintf(&irq_name[0], "%d", ch);
2064 dma_irq = platform_get_irq_byname(pdev, irq_name);
2068 goto exit_dma_irq_fail;
2071 /* INT_DMA_LCD is handled in lcd_dma.c */
2072 if (dma_irq == INT_DMA_LCD)
2075 ret = request_irq(dma_irq,
2076 omap1_dma_irq_handler, 0, "DMA",
2079 goto exit_dma_irq_fail;
2083 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2084 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2085 DMA_DEFAULT_FIFO_DEPTH, 0);
2087 if (cpu_class_is_omap2()) {
2088 strcpy(irq_name, "0");
2089 dma_irq = platform_get_irq_byname(pdev, irq_name);
2091 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2092 goto exit_dma_lch_fail;
2094 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2096 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2097 "for DMA (error %d)\n", dma_irq, ret);
2098 goto exit_dma_lch_fail;
2102 /* reserve dma channels 0 and 1 in high security devices */
2103 if (cpu_is_omap34xx() &&
2104 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2105 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2107 dma_chan[0].dev_id = 0;
2108 dma_chan[1].dev_id = 1;
2114 dev_err(&pdev->dev, "unable to request IRQ %d"
2115 "for DMA (error %d)\n", dma_irq, ret);
2116 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2117 dma_irq = platform_get_irq(pdev, irq_rel);
2118 free_irq(dma_irq, (void *)(irq_rel + 1));
2128 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2132 if (cpu_class_is_omap2()) {
2134 strcpy(irq_name, "0");
2135 dma_irq = platform_get_irq_byname(pdev, irq_name);
2136 remove_irq(dma_irq, &omap24xx_dma_irq);
2139 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2140 dma_irq = platform_get_irq(pdev, irq_rel);
2141 free_irq(dma_irq, (void *)(irq_rel + 1));
2150 static struct platform_driver omap_system_dma_driver = {
2151 .probe = omap_system_dma_probe,
2152 .remove = __devexit_p(omap_system_dma_remove),
2154 .name = "omap_dma_system"
2158 static int __init omap_system_dma_init(void)
2160 return platform_driver_register(&omap_system_dma_driver);
2162 arch_initcall(omap_system_dma_init);
2164 static void __exit omap_system_dma_exit(void)
2166 platform_driver_unregister(&omap_system_dma_driver);
2169 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2170 MODULE_LICENSE("GPL");
2171 MODULE_ALIAS("platform:" DRIVER_NAME);
2172 MODULE_AUTHOR("Texas Instruments Inc");
2175 * Reserve the omap SDMA channels using cmdline bootarg
2176 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2178 static int __init omap_dma_cmdline_reserve_ch(char *str)
2180 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2181 omap_dma_reserve_channels = 0;
2185 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);