2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <asm/hardware.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
31 * OMAP1510 GPIO registers
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42 #define OMAP1510_IH_GPIO_BASE 64
45 * OMAP1610 specific GPIO registers
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70 * OMAP730 specific GPIO registers
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
86 * omap24xx specific GPIO registers
88 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP24XX_GPIO_REVISION 0x0000
93 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
94 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
95 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
96 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
97 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
98 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
99 #define OMAP24XX_GPIO_CTRL 0x0030
100 #define OMAP24XX_GPIO_OE 0x0034
101 #define OMAP24XX_GPIO_DATAIN 0x0038
102 #define OMAP24XX_GPIO_DATAOUT 0x003c
103 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
104 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
105 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
106 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
107 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
108 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
109 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
110 #define OMAP24XX_GPIO_SETWKUENA 0x0084
111 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
112 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
117 u16 virtual_irq_start;
120 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
124 #ifdef CONFIG_ARCH_OMAP24XX
125 u32 non_wakeup_gpios;
126 u32 enabled_non_wakeup_gpios;
129 u32 saved_fallingdetect;
130 u32 saved_risingdetect;
135 #define METHOD_MPUIO 0
136 #define METHOD_GPIO_1510 1
137 #define METHOD_GPIO_1610 2
138 #define METHOD_GPIO_730 3
139 #define METHOD_GPIO_24XX 4
141 #ifdef CONFIG_ARCH_OMAP16XX
142 static struct gpio_bank gpio_bank_1610[5] = {
143 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
144 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
145 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
146 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
147 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
151 #ifdef CONFIG_ARCH_OMAP15XX
152 static struct gpio_bank gpio_bank_1510[2] = {
153 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
154 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
158 #ifdef CONFIG_ARCH_OMAP730
159 static struct gpio_bank gpio_bank_730[7] = {
160 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
161 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
162 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
163 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
164 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
165 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
166 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
170 #ifdef CONFIG_ARCH_OMAP24XX
171 static struct gpio_bank gpio_bank_24xx[4] = {
172 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
173 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
174 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
175 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
179 static struct gpio_bank *gpio_bank;
180 static int gpio_bank_count;
182 static inline struct gpio_bank *get_gpio_bank(int gpio)
184 #ifdef CONFIG_ARCH_OMAP15XX
185 if (cpu_is_omap15xx()) {
186 if (OMAP_GPIO_IS_MPUIO(gpio))
187 return &gpio_bank[0];
188 return &gpio_bank[1];
191 #if defined(CONFIG_ARCH_OMAP16XX)
192 if (cpu_is_omap16xx()) {
193 if (OMAP_GPIO_IS_MPUIO(gpio))
194 return &gpio_bank[0];
195 return &gpio_bank[1 + (gpio >> 4)];
198 #ifdef CONFIG_ARCH_OMAP730
199 if (cpu_is_omap730()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 5)];
205 #ifdef CONFIG_ARCH_OMAP24XX
206 if (cpu_is_omap24xx())
207 return &gpio_bank[gpio >> 5];
211 static inline int get_gpio_index(int gpio)
213 #ifdef CONFIG_ARCH_OMAP730
214 if (cpu_is_omap730())
217 #ifdef CONFIG_ARCH_OMAP24XX
218 if (cpu_is_omap24xx())
224 static inline int gpio_valid(int gpio)
228 #ifndef CONFIG_ARCH_OMAP24XX
229 if (OMAP_GPIO_IS_MPUIO(gpio)) {
230 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
235 #ifdef CONFIG_ARCH_OMAP15XX
236 if (cpu_is_omap15xx() && gpio < 16)
239 #if defined(CONFIG_ARCH_OMAP16XX)
240 if ((cpu_is_omap16xx()) && gpio < 64)
243 #ifdef CONFIG_ARCH_OMAP730
244 if (cpu_is_omap730() && gpio < 192)
247 #ifdef CONFIG_ARCH_OMAP24XX
248 if (cpu_is_omap24xx() && gpio < 128)
254 static int check_gpio(int gpio)
256 if (unlikely(gpio_valid(gpio)) < 0) {
257 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
264 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
266 void __iomem *reg = bank->base;
269 switch (bank->method) {
271 reg += OMAP_MPUIO_IO_CNTL;
273 case METHOD_GPIO_1510:
274 reg += OMAP1510_GPIO_DIR_CONTROL;
276 case METHOD_GPIO_1610:
277 reg += OMAP1610_GPIO_DIRECTION;
279 case METHOD_GPIO_730:
280 reg += OMAP730_GPIO_DIR_CONTROL;
282 case METHOD_GPIO_24XX:
283 reg += OMAP24XX_GPIO_OE;
286 l = __raw_readl(reg);
291 __raw_writel(l, reg);
294 void omap_set_gpio_direction(int gpio, int is_input)
296 struct gpio_bank *bank;
298 if (check_gpio(gpio) < 0)
300 bank = get_gpio_bank(gpio);
301 spin_lock(&bank->lock);
302 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
303 spin_unlock(&bank->lock);
306 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
308 void __iomem *reg = bank->base;
311 switch (bank->method) {
313 reg += OMAP_MPUIO_OUTPUT;
314 l = __raw_readl(reg);
320 case METHOD_GPIO_1510:
321 reg += OMAP1510_GPIO_DATA_OUTPUT;
322 l = __raw_readl(reg);
328 case METHOD_GPIO_1610:
330 reg += OMAP1610_GPIO_SET_DATAOUT;
332 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
335 case METHOD_GPIO_730:
336 reg += OMAP730_GPIO_DATA_OUTPUT;
337 l = __raw_readl(reg);
343 case METHOD_GPIO_24XX:
345 reg += OMAP24XX_GPIO_SETDATAOUT;
347 reg += OMAP24XX_GPIO_CLEARDATAOUT;
354 __raw_writel(l, reg);
357 void omap_set_gpio_dataout(int gpio, int enable)
359 struct gpio_bank *bank;
361 if (check_gpio(gpio) < 0)
363 bank = get_gpio_bank(gpio);
364 spin_lock(&bank->lock);
365 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
366 spin_unlock(&bank->lock);
369 int omap_get_gpio_datain(int gpio)
371 struct gpio_bank *bank;
374 if (check_gpio(gpio) < 0)
376 bank = get_gpio_bank(gpio);
378 switch (bank->method) {
380 reg += OMAP_MPUIO_INPUT_LATCH;
382 case METHOD_GPIO_1510:
383 reg += OMAP1510_GPIO_DATA_INPUT;
385 case METHOD_GPIO_1610:
386 reg += OMAP1610_GPIO_DATAIN;
388 case METHOD_GPIO_730:
389 reg += OMAP730_GPIO_DATA_INPUT;
391 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_DATAIN;
398 return (__raw_readl(reg)
399 & (1 << get_gpio_index(gpio))) != 0;
402 #define MOD_REG_BIT(reg, bit_mask, set) \
404 int l = __raw_readl(base + reg); \
405 if (set) l |= bit_mask; \
406 else l &= ~bit_mask; \
407 __raw_writel(l, base + reg); \
410 #ifdef CONFIG_ARCH_OMAP24XX
411 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
413 void __iomem *base = bank->base;
414 u32 gpio_bit = 1 << gpio;
416 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
417 trigger & __IRQT_LOWLVL);
418 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
419 trigger & __IRQT_HIGHLVL);
420 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
421 trigger & __IRQT_RISEDGE);
422 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
423 trigger & __IRQT_FALEDGE);
424 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
426 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
428 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
431 bank->enabled_non_wakeup_gpios |= gpio_bit;
433 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
435 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
436 * triggering requested. */
440 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
442 void __iomem *reg = bank->base;
445 switch (bank->method) {
447 reg += OMAP_MPUIO_GPIO_INT_EDGE;
448 l = __raw_readl(reg);
449 if (trigger & __IRQT_RISEDGE)
451 else if (trigger & __IRQT_FALEDGE)
456 case METHOD_GPIO_1510:
457 reg += OMAP1510_GPIO_INT_CONTROL;
458 l = __raw_readl(reg);
459 if (trigger & __IRQT_RISEDGE)
461 else if (trigger & __IRQT_FALEDGE)
466 #ifdef CONFIG_ARCH_OMAP16XX
467 case METHOD_GPIO_1610:
469 reg += OMAP1610_GPIO_EDGE_CTRL2;
471 reg += OMAP1610_GPIO_EDGE_CTRL1;
473 /* We allow only edge triggering, i.e. two lowest bits */
474 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
476 l = __raw_readl(reg);
477 l &= ~(3 << (gpio << 1));
478 if (trigger & __IRQT_RISEDGE)
479 l |= 2 << (gpio << 1);
480 if (trigger & __IRQT_FALEDGE)
481 l |= 1 << (gpio << 1);
483 /* Enable wake-up during idle for dynamic tick */
484 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
486 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
489 #ifdef CONFIG_ARCH_OMAP730
490 case METHOD_GPIO_730:
491 reg += OMAP730_GPIO_INT_CONTROL;
492 l = __raw_readl(reg);
493 if (trigger & __IRQT_RISEDGE)
495 else if (trigger & __IRQT_FALEDGE)
501 #ifdef CONFIG_ARCH_OMAP24XX
502 case METHOD_GPIO_24XX:
503 set_24xx_gpio_triggering(bank, gpio, trigger);
510 __raw_writel(l, reg);
516 static int gpio_irq_type(unsigned irq, unsigned type)
518 struct gpio_bank *bank;
522 if (irq > IH_MPUIO_BASE)
523 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
525 gpio = irq - IH_GPIO_BASE;
527 if (check_gpio(gpio) < 0)
530 if (type & IRQT_PROBE)
532 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
535 bank = get_gpio_bank(gpio);
536 spin_lock(&bank->lock);
537 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
539 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
540 irq_desc[irq].status |= type;
542 spin_unlock(&bank->lock);
546 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
548 void __iomem *reg = bank->base;
550 switch (bank->method) {
552 /* MPUIO irqstatus is reset by reading the status register,
553 * so do nothing here */
555 case METHOD_GPIO_1510:
556 reg += OMAP1510_GPIO_INT_STATUS;
558 case METHOD_GPIO_1610:
559 reg += OMAP1610_GPIO_IRQSTATUS1;
561 case METHOD_GPIO_730:
562 reg += OMAP730_GPIO_INT_STATUS;
564 case METHOD_GPIO_24XX:
565 reg += OMAP24XX_GPIO_IRQSTATUS1;
571 __raw_writel(gpio_mask, reg);
573 /* Workaround for clearing DSP GPIO interrupts to allow retention */
574 if (cpu_is_omap2420())
575 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
578 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
580 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
583 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
585 void __iomem *reg = bank->base;
590 switch (bank->method) {
592 reg += OMAP_MPUIO_GPIO_MASKIT;
596 case METHOD_GPIO_1510:
597 reg += OMAP1510_GPIO_INT_MASK;
601 case METHOD_GPIO_1610:
602 reg += OMAP1610_GPIO_IRQENABLE1;
605 case METHOD_GPIO_730:
606 reg += OMAP730_GPIO_INT_MASK;
610 case METHOD_GPIO_24XX:
611 reg += OMAP24XX_GPIO_IRQENABLE1;
619 l = __raw_readl(reg);
626 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
628 void __iomem *reg = bank->base;
631 switch (bank->method) {
633 reg += OMAP_MPUIO_GPIO_MASKIT;
634 l = __raw_readl(reg);
640 case METHOD_GPIO_1510:
641 reg += OMAP1510_GPIO_INT_MASK;
642 l = __raw_readl(reg);
648 case METHOD_GPIO_1610:
650 reg += OMAP1610_GPIO_SET_IRQENABLE1;
652 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
655 case METHOD_GPIO_730:
656 reg += OMAP730_GPIO_INT_MASK;
657 l = __raw_readl(reg);
663 case METHOD_GPIO_24XX:
665 reg += OMAP24XX_GPIO_SETIRQENABLE1;
667 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
674 __raw_writel(l, reg);
677 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
679 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
683 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
684 * 1510 does not seem to have a wake-up register. If JTAG is connected
685 * to the target, system will wake up always on GPIO events. While
686 * system is running all registered GPIO interrupts need to have wake-up
687 * enabled. When system is suspended, only selected GPIO interrupts need
688 * to have wake-up enabled.
690 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
692 switch (bank->method) {
693 #ifdef CONFIG_ARCH_OMAP16XX
694 case METHOD_GPIO_1610:
695 spin_lock(&bank->lock);
697 bank->suspend_wakeup |= (1 << gpio);
699 bank->suspend_wakeup &= ~(1 << gpio);
700 spin_unlock(&bank->lock);
703 #ifdef CONFIG_ARCH_OMAP24XX
704 case METHOD_GPIO_24XX:
705 spin_lock(&bank->lock);
707 if (bank->non_wakeup_gpios & (1 << gpio)) {
708 printk(KERN_ERR "Unable to enable wakeup on "
709 "non-wakeup GPIO%d\n",
710 (bank - gpio_bank) * 32 + gpio);
711 spin_unlock(&bank->lock);
714 bank->suspend_wakeup |= (1 << gpio);
716 bank->suspend_wakeup &= ~(1 << gpio);
717 spin_unlock(&bank->lock);
721 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
727 static void _reset_gpio(struct gpio_bank *bank, int gpio)
729 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
730 _set_gpio_irqenable(bank, gpio, 0);
731 _clear_gpio_irqstatus(bank, gpio);
732 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
735 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
736 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
738 unsigned int gpio = irq - IH_GPIO_BASE;
739 struct gpio_bank *bank;
742 if (check_gpio(gpio) < 0)
744 bank = get_gpio_bank(gpio);
745 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
750 int omap_request_gpio(int gpio)
752 struct gpio_bank *bank;
754 if (check_gpio(gpio) < 0)
757 bank = get_gpio_bank(gpio);
758 spin_lock(&bank->lock);
759 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
760 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
762 spin_unlock(&bank->lock);
765 bank->reserved_map |= (1 << get_gpio_index(gpio));
767 /* Set trigger to none. You need to enable the desired trigger with
768 * request_irq() or set_irq_type().
770 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
772 #ifdef CONFIG_ARCH_OMAP15XX
773 if (bank->method == METHOD_GPIO_1510) {
776 /* Claim the pin for MPU */
777 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
778 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
781 spin_unlock(&bank->lock);
786 void omap_free_gpio(int gpio)
788 struct gpio_bank *bank;
790 if (check_gpio(gpio) < 0)
792 bank = get_gpio_bank(gpio);
793 spin_lock(&bank->lock);
794 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
795 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
797 spin_unlock(&bank->lock);
800 #ifdef CONFIG_ARCH_OMAP16XX
801 if (bank->method == METHOD_GPIO_1610) {
802 /* Disable wake-up during idle for dynamic tick */
803 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
804 __raw_writel(1 << get_gpio_index(gpio), reg);
807 #ifdef CONFIG_ARCH_OMAP24XX
808 if (bank->method == METHOD_GPIO_24XX) {
809 /* Disable wake-up during idle for dynamic tick */
810 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
811 __raw_writel(1 << get_gpio_index(gpio), reg);
814 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
815 _reset_gpio(bank, gpio);
816 spin_unlock(&bank->lock);
820 * We need to unmask the GPIO bank interrupt as soon as possible to
821 * avoid missing GPIO interrupts for other lines in the bank.
822 * Then we need to mask-read-clear-unmask the triggered GPIO lines
823 * in the bank to avoid missing nested interrupts for a GPIO line.
824 * If we wait to unmask individual GPIO lines in the bank after the
825 * line's interrupt handler has been run, we may miss some nested
828 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
830 void __iomem *isr_reg = NULL;
832 unsigned int gpio_irq;
833 struct gpio_bank *bank;
837 desc->chip->ack(irq);
839 bank = get_irq_data(irq);
840 if (bank->method == METHOD_MPUIO)
841 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
842 #ifdef CONFIG_ARCH_OMAP15XX
843 if (bank->method == METHOD_GPIO_1510)
844 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
846 #if defined(CONFIG_ARCH_OMAP16XX)
847 if (bank->method == METHOD_GPIO_1610)
848 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
850 #ifdef CONFIG_ARCH_OMAP730
851 if (bank->method == METHOD_GPIO_730)
852 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
854 #ifdef CONFIG_ARCH_OMAP24XX
855 if (bank->method == METHOD_GPIO_24XX)
856 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
859 u32 isr_saved, level_mask = 0;
862 enabled = _get_gpio_irqbank_mask(bank);
863 isr_saved = isr = __raw_readl(isr_reg) & enabled;
865 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
868 if (cpu_is_omap24xx()) {
870 __raw_readl(bank->base +
871 OMAP24XX_GPIO_LEVELDETECT0) |
872 __raw_readl(bank->base +
873 OMAP24XX_GPIO_LEVELDETECT1);
874 level_mask &= enabled;
877 /* clear edge sensitive interrupts before handler(s) are
878 called so that we don't miss any interrupt occurred while
880 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
881 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
882 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
884 /* if there is only edge sensitive GPIO pin interrupts
885 configured, we could unmask GPIO bank interrupt immediately */
886 if (!level_mask && !unmasked) {
888 desc->chip->unmask(irq);
896 gpio_irq = bank->virtual_irq_start;
897 for (; isr != 0; isr >>= 1, gpio_irq++) {
902 d = irq_desc + gpio_irq;
903 /* Don't run the handler if it's already running
904 * or was disabled lazely.
906 if (unlikely((d->depth ||
907 (d->status & IRQ_INPROGRESS)))) {
909 (gpio_irq - bank->virtual_irq_start);
910 /* The unmasking will be done by
911 * enable_irq in case it is disabled or
912 * after returning from the handler if
913 * it's already running.
915 _enable_gpio_irqbank(bank, irq_mask, 0);
917 /* Level triggered interrupts
918 * won't ever be reentered
920 BUG_ON(level_mask & irq_mask);
921 d->status |= IRQ_PENDING;
926 desc_handle_irq(gpio_irq, d);
928 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
930 (gpio_irq - bank->virtual_irq_start);
931 d->status &= ~IRQ_PENDING;
932 _enable_gpio_irqbank(bank, irq_mask, 1);
933 retrigger |= irq_mask;
937 if (cpu_is_omap24xx()) {
938 /* clear level sensitive interrupts after handler(s) */
939 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
940 _clear_gpio_irqbank(bank, isr_saved & level_mask);
941 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
945 /* if bank has any level sensitive GPIO pin interrupt
946 configured, we must unmask the bank interrupt only after
947 handler(s) are executed in order to avoid spurious bank
950 desc->chip->unmask(irq);
954 static void gpio_irq_shutdown(unsigned int irq)
956 unsigned int gpio = irq - IH_GPIO_BASE;
957 struct gpio_bank *bank = get_gpio_bank(gpio);
959 _reset_gpio(bank, gpio);
962 static void gpio_ack_irq(unsigned int irq)
964 unsigned int gpio = irq - IH_GPIO_BASE;
965 struct gpio_bank *bank = get_gpio_bank(gpio);
967 _clear_gpio_irqstatus(bank, gpio);
970 static void gpio_mask_irq(unsigned int irq)
972 unsigned int gpio = irq - IH_GPIO_BASE;
973 struct gpio_bank *bank = get_gpio_bank(gpio);
975 _set_gpio_irqenable(bank, gpio, 0);
978 static void gpio_unmask_irq(unsigned int irq)
980 unsigned int gpio = irq - IH_GPIO_BASE;
981 unsigned int gpio_idx = get_gpio_index(gpio);
982 struct gpio_bank *bank = get_gpio_bank(gpio);
984 _set_gpio_irqenable(bank, gpio_idx, 1);
987 static void mpuio_ack_irq(unsigned int irq)
989 /* The ISR is reset automatically, so do nothing here. */
992 static void mpuio_mask_irq(unsigned int irq)
994 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
995 struct gpio_bank *bank = get_gpio_bank(gpio);
997 _set_gpio_irqenable(bank, gpio, 0);
1000 static void mpuio_unmask_irq(unsigned int irq)
1002 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1003 struct gpio_bank *bank = get_gpio_bank(gpio);
1005 _set_gpio_irqenable(bank, gpio, 1);
1008 static struct irq_chip gpio_irq_chip = {
1010 .shutdown = gpio_irq_shutdown,
1011 .ack = gpio_ack_irq,
1012 .mask = gpio_mask_irq,
1013 .unmask = gpio_unmask_irq,
1014 .set_type = gpio_irq_type,
1015 .set_wake = gpio_wake_enable,
1018 static struct irq_chip mpuio_irq_chip = {
1020 .ack = mpuio_ack_irq,
1021 .mask = mpuio_mask_irq,
1022 .unmask = mpuio_unmask_irq,
1023 .set_type = gpio_irq_type,
1026 static int initialized;
1027 static struct clk * gpio_ick;
1028 static struct clk * gpio_fck;
1030 static int __init _omap_gpio_init(void)
1033 struct gpio_bank *bank;
1037 if (cpu_is_omap15xx()) {
1038 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1039 if (IS_ERR(gpio_ick))
1040 printk("Could not get arm_gpio_ck\n");
1042 clk_enable(gpio_ick);
1044 if (cpu_is_omap24xx()) {
1045 gpio_ick = clk_get(NULL, "gpios_ick");
1046 if (IS_ERR(gpio_ick))
1047 printk("Could not get gpios_ick\n");
1049 clk_enable(gpio_ick);
1050 gpio_fck = clk_get(NULL, "gpios_fck");
1051 if (IS_ERR(gpio_fck))
1052 printk("Could not get gpios_fck\n");
1054 clk_enable(gpio_fck);
1057 #ifdef CONFIG_ARCH_OMAP15XX
1058 if (cpu_is_omap15xx()) {
1059 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1060 gpio_bank_count = 2;
1061 gpio_bank = gpio_bank_1510;
1064 #if defined(CONFIG_ARCH_OMAP16XX)
1065 if (cpu_is_omap16xx()) {
1068 gpio_bank_count = 5;
1069 gpio_bank = gpio_bank_1610;
1070 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1071 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1072 (rev >> 4) & 0x0f, rev & 0x0f);
1075 #ifdef CONFIG_ARCH_OMAP730
1076 if (cpu_is_omap730()) {
1077 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1078 gpio_bank_count = 7;
1079 gpio_bank = gpio_bank_730;
1082 #ifdef CONFIG_ARCH_OMAP24XX
1083 if (cpu_is_omap24xx()) {
1086 gpio_bank_count = 4;
1087 gpio_bank = gpio_bank_24xx;
1088 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1089 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1090 (rev >> 4) & 0x0f, rev & 0x0f);
1093 for (i = 0; i < gpio_bank_count; i++) {
1094 int j, gpio_count = 16;
1096 bank = &gpio_bank[i];
1097 bank->reserved_map = 0;
1098 bank->base = IO_ADDRESS(bank->base);
1099 spin_lock_init(&bank->lock);
1100 if (bank->method == METHOD_MPUIO) {
1101 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1103 #ifdef CONFIG_ARCH_OMAP15XX
1104 if (bank->method == METHOD_GPIO_1510) {
1105 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1106 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1109 #if defined(CONFIG_ARCH_OMAP16XX)
1110 if (bank->method == METHOD_GPIO_1610) {
1111 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1112 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1113 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1116 #ifdef CONFIG_ARCH_OMAP730
1117 if (bank->method == METHOD_GPIO_730) {
1118 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1119 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1121 gpio_count = 32; /* 730 has 32-bit GPIOs */
1124 #ifdef CONFIG_ARCH_OMAP24XX
1125 if (bank->method == METHOD_GPIO_24XX) {
1126 static const u32 non_wakeup_gpios[] = {
1127 0xe203ffc0, 0x08700040
1130 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1131 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1132 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1134 /* Initialize interface clock ungated, module enabled */
1135 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1136 if (i < ARRAY_SIZE(non_wakeup_gpios))
1137 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1141 for (j = bank->virtual_irq_start;
1142 j < bank->virtual_irq_start + gpio_count; j++) {
1143 if (bank->method == METHOD_MPUIO)
1144 set_irq_chip(j, &mpuio_irq_chip);
1146 set_irq_chip(j, &gpio_irq_chip);
1147 set_irq_handler(j, handle_simple_irq);
1148 set_irq_flags(j, IRQF_VALID);
1150 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1151 set_irq_data(bank->irq, bank);
1154 /* Enable system clock for GPIO module.
1155 * The CAM_CLK_CTRL *is* really the right place. */
1156 if (cpu_is_omap16xx())
1157 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1159 #ifdef CONFIG_ARCH_OMAP24XX
1160 /* Enable autoidle for the OCP interface */
1161 if (cpu_is_omap24xx())
1162 omap_writel(1 << 0, 0x48019010);
1168 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1169 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1173 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1176 for (i = 0; i < gpio_bank_count; i++) {
1177 struct gpio_bank *bank = &gpio_bank[i];
1178 void __iomem *wake_status;
1179 void __iomem *wake_clear;
1180 void __iomem *wake_set;
1182 switch (bank->method) {
1183 case METHOD_GPIO_1610:
1184 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1185 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1186 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1188 case METHOD_GPIO_24XX:
1189 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1190 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1191 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1197 spin_lock(&bank->lock);
1198 bank->saved_wakeup = __raw_readl(wake_status);
1199 __raw_writel(0xffffffff, wake_clear);
1200 __raw_writel(bank->suspend_wakeup, wake_set);
1201 spin_unlock(&bank->lock);
1207 static int omap_gpio_resume(struct sys_device *dev)
1211 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1214 for (i = 0; i < gpio_bank_count; i++) {
1215 struct gpio_bank *bank = &gpio_bank[i];
1216 void __iomem *wake_clear;
1217 void __iomem *wake_set;
1219 switch (bank->method) {
1220 case METHOD_GPIO_1610:
1221 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1222 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1224 case METHOD_GPIO_24XX:
1225 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1226 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1232 spin_lock(&bank->lock);
1233 __raw_writel(0xffffffff, wake_clear);
1234 __raw_writel(bank->saved_wakeup, wake_set);
1235 spin_unlock(&bank->lock);
1241 static struct sysdev_class omap_gpio_sysclass = {
1242 set_kset_name("gpio"),
1243 .suspend = omap_gpio_suspend,
1244 .resume = omap_gpio_resume,
1247 static struct sys_device omap_gpio_device = {
1249 .cls = &omap_gpio_sysclass,
1254 #ifdef CONFIG_ARCH_OMAP24XX
1256 static int workaround_enabled;
1258 void omap2_gpio_prepare_for_retention(void)
1262 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1263 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1264 for (i = 0; i < gpio_bank_count; i++) {
1265 struct gpio_bank *bank = &gpio_bank[i];
1268 if (!(bank->enabled_non_wakeup_gpios))
1270 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1271 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1272 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1273 bank->saved_fallingdetect = l1;
1274 bank->saved_risingdetect = l2;
1275 l1 &= ~bank->enabled_non_wakeup_gpios;
1276 l2 &= ~bank->enabled_non_wakeup_gpios;
1277 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1278 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1282 workaround_enabled = 0;
1285 workaround_enabled = 1;
1288 void omap2_gpio_resume_after_retention(void)
1292 if (!workaround_enabled)
1294 for (i = 0; i < gpio_bank_count; i++) {
1295 struct gpio_bank *bank = &gpio_bank[i];
1298 if (!(bank->enabled_non_wakeup_gpios))
1300 __raw_writel(bank->saved_fallingdetect,
1301 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1302 __raw_writel(bank->saved_risingdetect,
1303 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1304 /* Check if any of the non-wakeup interrupt GPIOs have changed
1305 * state. If so, generate an IRQ by software. This is
1306 * horribly racy, but it's the best we can do to work around
1307 * this silicon bug. */
1308 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1309 l ^= bank->saved_datain;
1310 l &= bank->non_wakeup_gpios;
1314 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1315 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1316 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1317 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1318 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1319 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1328 * This may get called early from board specific init
1329 * for boards that have interrupts routed via FPGA.
1331 int omap_gpio_init(void)
1334 return _omap_gpio_init();
1339 static int __init omap_gpio_sysinit(void)
1344 ret = _omap_gpio_init();
1346 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1347 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1349 ret = sysdev_class_register(&omap_gpio_sysclass);
1351 ret = sysdev_register(&omap_gpio_device);
1359 EXPORT_SYMBOL(omap_request_gpio);
1360 EXPORT_SYMBOL(omap_free_gpio);
1361 EXPORT_SYMBOL(omap_set_gpio_direction);
1362 EXPORT_SYMBOL(omap_set_gpio_dataout);
1363 EXPORT_SYMBOL(omap_get_gpio_datain);
1365 arch_initcall(omap_gpio_sysinit);
1368 #ifdef CONFIG_DEBUG_FS
1370 #include <linux/debugfs.h>
1371 #include <linux/seq_file.h>
1373 static int gpio_is_input(struct gpio_bank *bank, int mask)
1375 void __iomem *reg = bank->base;
1377 switch (bank->method) {
1379 reg += OMAP_MPUIO_IO_CNTL;
1381 case METHOD_GPIO_1510:
1382 reg += OMAP1510_GPIO_DIR_CONTROL;
1384 case METHOD_GPIO_1610:
1385 reg += OMAP1610_GPIO_DIRECTION;
1387 case METHOD_GPIO_730:
1388 reg += OMAP730_GPIO_DIR_CONTROL;
1390 case METHOD_GPIO_24XX:
1391 reg += OMAP24XX_GPIO_OE;
1394 return __raw_readl(reg) & mask;
1398 static int dbg_gpio_show(struct seq_file *s, void *unused)
1400 unsigned i, j, gpio;
1402 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1403 struct gpio_bank *bank = gpio_bank + i;
1404 unsigned bankwidth = 16;
1407 if (!cpu_is_omap24xx() && bank->method == METHOD_MPUIO)
1408 gpio = OMAP_MPUIO(0);
1409 else if (cpu_is_omap24xx() || cpu_is_omap730())
1412 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1413 unsigned irq, value, is_in, irqstat;
1415 if (!(bank->reserved_map & mask))
1418 irq = bank->virtual_irq_start + j;
1419 value = omap_get_gpio_datain(gpio);
1420 is_in = gpio_is_input(bank, mask);
1422 if (!cpu_is_omap24xx() && bank->method == METHOD_MPUIO)
1423 seq_printf(s, "MPUIO %2d: ", j);
1425 seq_printf(s, "GPIO %3d: ", gpio);
1426 seq_printf(s, "%s %s",
1427 is_in ? "in " : "out",
1428 value ? "hi" : "lo");
1430 irqstat = irq_desc[irq].status;
1431 if (is_in && ((bank->suspend_wakeup & mask)
1432 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1433 char *trigger = NULL;
1435 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1436 case IRQ_TYPE_EDGE_FALLING:
1437 trigger = "falling";
1439 case IRQ_TYPE_EDGE_RISING:
1442 case IRQ_TYPE_EDGE_BOTH:
1443 trigger = "bothedge";
1445 case IRQ_TYPE_LEVEL_LOW:
1448 case IRQ_TYPE_LEVEL_HIGH:
1452 trigger = "(unspecified)";
1455 seq_printf(s, ", irq-%d %s%s",
1457 (bank->suspend_wakeup & mask)
1460 seq_printf(s, "\n");
1463 if (!cpu_is_omap24xx() && bank->method == METHOD_MPUIO) {
1464 seq_printf(s, "\n");
1471 static int dbg_gpio_open(struct inode *inode, struct file *file)
1473 return single_open(file, dbg_gpio_show, inode->u.generic_ip/*i_private*/);
1476 static const struct file_operations debug_fops = {
1477 .open = dbg_gpio_open,
1479 .llseek = seq_lseek,
1480 .release = single_release,
1483 static int __init omap_gpio_debuginit(void)
1485 (void) debugfs_create_file("omap_gpio", S_IRUGO, NULL, NULL, &debug_fops);
1488 late_initcall(omap_gpio_debuginit);