2 * arch/arm/plat-orion/addr-map.c
4 * Address map functions for Marvell Orion based SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/mbus.h>
16 #include <plat/addr-map.h>
18 struct mbus_dram_target_info orion_mbus_dram_info;
20 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
22 return &orion_mbus_dram_info;
24 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
27 * DDR target is the same on all Orion platforms.
32 * Helpers to get DDR bank info
34 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
35 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
38 * CPU Address Decode Windows registers
40 #define WIN_CTRL_OFF 0x0000
41 #define WIN_BASE_OFF 0x0004
42 #define WIN_REMAP_LO_OFF 0x0008
43 #define WIN_REMAP_HI_OFF 0x000c
45 #define ATTR_HW_COHERENCY (0x1 << 4)
48 * Default implementation
50 static void __init __iomem *
51 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
53 return cfg->bridge_virt_base + (win << 4);
57 * Default implementation
59 static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
62 if (win < cfg->remappable_wins)
68 void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
69 const int win, const u32 base,
70 const u32 size, const u8 target,
71 const u8 attr, const int remap)
73 void __iomem *addr = cfg->win_cfg_base(cfg, win);
74 u32 ctrl, base_high, remap_addr;
76 if (win >= cfg->num_wins) {
77 printk(KERN_ERR "setup_cpu_win: trying to allocate window "
78 "%d when only %d allowed\n", win, cfg->num_wins);
81 base_high = base & 0xffff0000;
82 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
84 writel(base_high, addr + WIN_BASE_OFF);
85 writel(ctrl, addr + WIN_CTRL_OFF);
86 if (cfg->cpu_win_can_remap(cfg, win)) {
91 writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
92 writel(0, addr + WIN_REMAP_HI_OFF);
97 * Configure a number of windows.
99 static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
100 const struct orion_addr_map_info *info)
102 while (info->win != -1) {
103 orion_setup_cpu_win(cfg, info->win, info->base, info->size,
104 info->target, info->attr, info->remap);
109 static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
114 for (i = 0; i < cfg->num_wins; i++) {
115 addr = cfg->win_cfg_base(cfg, i);
117 writel(0, addr + WIN_BASE_OFF);
118 writel(0, addr + WIN_CTRL_OFF);
119 if (cfg->cpu_win_can_remap(cfg, i)) {
120 writel(0, addr + WIN_REMAP_LO_OFF);
121 writel(0, addr + WIN_REMAP_HI_OFF);
127 * Disable, clear and configure windows.
129 void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
130 const struct orion_addr_map_info *info)
132 if (!cfg->cpu_win_can_remap)
133 cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
135 if (!cfg->win_cfg_base)
136 cfg->win_cfg_base = orion_win_cfg_base;
138 orion_disable_wins(cfg);
141 orion_setup_cpu_wins(cfg, info);
145 * Setup MBUS dram target info.
147 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
148 const void __iomem *ddr_window_cpu_base)
153 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
155 for (i = 0, cs = 0; i < 4; i++) {
156 u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
157 u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
160 * We only take care of entries for which the chip
161 * select is enabled, and that don't have high base
162 * address bits set (devices can only access the first
163 * 32 bits of the memory).
165 if ((size & 1) && !(base & 0xF)) {
166 struct mbus_dram_window *w;
168 w = &orion_mbus_dram_info.cs[cs++];
170 w->mbus_attr = 0xf & ~(1 << i);
171 if (cfg->hw_io_coherency)
172 w->mbus_attr |= ATTR_HW_COHERENCY;
173 w->base = base & 0xffff0000;
174 w->size = (size | 0x0000ffff) + 1;
177 orion_mbus_dram_info.num_cs = cs;