arch/arm/plat-rk/ddr_freq.c

   1 #define pr_fmt(fmt) "ddrfreq: " fmt
   2 #include <linux/clk.h>
   3 #include <linux/cpu.h>
   4 #include <linux/cpufreq.h>
   5 #include <linux/delay.h>
   6 #include <linux/earlysuspend.h>
   7 #include <linux/freezer.h>
   8 #include <linux/fs.h>
   9 #include <linux/kthread.h>
  10 #include <linux/miscdevice.h>
  11 #include <linux/module.h>
  12 #include <linux/reboot.h>
  13 #include <linux/slab.h>
  14 #include <linux/uaccess.h>
  15
  16 #include <mach/board.h>
  17 #include <mach/clock.h>
  18 #include <mach/ddr.h>
  19 #include <mach/dvfs.h>
  20
  21 #include <linux/rk_fb.h>
  22 //#include <linux/delay.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/tlbflush.h>
  26 #include <linux/vmalloc.h>
  27
  28 enum {
  29         DEBUG_DDR = 1U << 0,
  30         DEBUG_VIDEO_STATE = 1U << 1,
  31         DEBUG_SUSPEND = 1U << 2,
  32         DEBUG_VERBOSE = 1U << 3,
  33 };
  34 static int debug_mask = DEBUG_DDR;
  35 module_param(debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  36 #define dprintk(mask, fmt, ...) do { if (mask & debug_mask) pr_info(fmt, ##__VA_ARGS__); } while (0)
  37
  38 #define MHZ     (1000*1000)
  39 #define KHZ     1000
  40
  41 enum SYS_STATUS {
  42         SYS_STATUS_SUSPEND = 0, // 0x01
  43         SYS_STATUS_VIDEO,       // 0x02
  44         SYS_STATUS_VIDEO_720P,       // 0x04
  45         SYS_STATUS_VIDEO_1080P,       // 0x08
  46         SYS_STATUS_GPU,         // 0x10
  47         SYS_STATUS_RGA,         // 0x20
  48         SYS_STATUS_CIF0,        // 0x40
  49         SYS_STATUS_CIF1,        // 0x80
  50         SYS_STATUS_REBOOT,      // 0x100
  51         SYS_STATUS_LCDC0,       // 0x200
  52         SYS_STATUS_LCDC1,       // 0x400
  53 };
  54
  55 struct ddr {
  56 #ifdef CONFIG_HAS_EARLYSUSPEND
  57         struct early_suspend early_suspend;
  58 #endif
  59         struct clk *pll;
  60         struct clk *clk;
  61         unsigned long normal_rate;
  62         unsigned long video_rate;
  63         unsigned long video_low_rate;
  64        unsigned long dualview_rate;
  65         unsigned long idle_rate;
  66         unsigned long suspend_rate;
  67         unsigned long reboot_rate;
  68         char video_state;
  69         bool auto_self_refresh;
  70         char *mode;
  71         unsigned long sys_status;
  72         struct task_struct *task;
  73         wait_queue_head_t wait;
  74 };
  75 static struct ddr ddr;
  76
  77 module_param_named(sys_status, ddr.sys_status, ulong, S_IRUGO);
  78 module_param_named(video_state, ddr.video_state, byte, S_IRUGO);
  79 module_param_named(auto_self_refresh, ddr.auto_self_refresh, bool, S_IRUGO);
  80 module_param_named(mode, ddr.mode, charp, S_IRUGO);
  81
  82 static noinline void ddrfreq_set_sys_status(enum SYS_STATUS status)
  83 {
  84         set_bit(status, &ddr.sys_status);
  85         wake_up(&ddr.wait);
  86 }
  87
  88 static noinline void ddrfreq_clear_sys_status(enum SYS_STATUS status)
  89 {
  90         clear_bit(status, &ddr.sys_status);
  91         wake_up(&ddr.wait);
  92 }
  93
  94 static void ddrfreq_mode(bool auto_self_refresh, unsigned long *target_rate, char *name)
  95 {
  96         ddr.mode = name;
  97         if (auto_self_refresh != ddr.auto_self_refresh) {
  98                 ddr_set_auto_self_refresh(auto_self_refresh);
  99                 ddr.auto_self_refresh = auto_self_refresh;
 100                 dprintk(DEBUG_DDR, "change auto self refresh to %d when %s\n", auto_self_refresh, name);
 101         }
 102         if (*target_rate != clk_get_rate(ddr.clk)) {
 103                 if (clk_set_rate(ddr.clk, *target_rate) == 0) {
 104                         *target_rate = clk_get_rate(ddr.clk);
 105                         dprintk(DEBUG_DDR, "change freq to %lu MHz when %s\n", *target_rate / MHZ, name);
 106                 }
 107         }
 108 }
 109
 110 static noinline void ddrfreq_work(unsigned long sys_status)
 111 {
 112         static struct clk *cpu = NULL;
 113         static struct clk *gpu = NULL;
 114         unsigned long s = sys_status;
 115
 116         if (!cpu)
 117                 cpu = clk_get(NULL, "cpu");
 118         if (!gpu)
 119                 gpu = clk_get(NULL, "gpu");
 120         dprintk(DEBUG_VERBOSE, "sys_status %02lx\n", sys_status);
 121         if (ddr.reboot_rate && (s & (1 << SYS_STATUS_REBOOT))) {
 122                 ddrfreq_mode(false, &ddr.reboot_rate, "shutdown/reboot");
 123         } else if (ddr.suspend_rate && (s & (1 << SYS_STATUS_SUSPEND))) {
 124                 ddrfreq_mode(true, &ddr.suspend_rate, "suspend");
 125         } else if (ddr.dualview_rate
 126               && (s & (1 << SYS_STATUS_LCDC0))
 127               && (s & (1 << SYS_STATUS_LCDC1))
 128               ) {
 129                 ddrfreq_mode(false, &ddr.dualview_rate, "dual-view");
 130         } else if ((ddr.video_rate || ddr.video_low_rate) && (s & (1 << SYS_STATUS_VIDEO))) {
 131                 if(ddr.video_low_rate && (s & (1 << SYS_STATUS_VIDEO_720P)))
 132                         ddrfreq_mode(false, &ddr.video_low_rate, "video low");
 133                 else if(ddr.video_rate && (s & (1 << SYS_STATUS_VIDEO_1080P)))
 134                         ddrfreq_mode(false, &ddr.video_rate, "video");
 135                 else
 136                         ddrfreq_mode(false, &ddr.normal_rate, "video normal");
 137         } else if (ddr.idle_rate
 138                 && !(s & (1 << SYS_STATUS_GPU))
 139                 && !(s & (1 << SYS_STATUS_RGA))
 140                 && !(s & (1 << SYS_STATUS_CIF0))
 141                 && !(s & (1 << SYS_STATUS_CIF1))
 142                 && (clk_get_rate(cpu) < 816 * MHZ)
 143                 && (clk_get_rate(gpu) <= 200 * MHZ)
 144                 ) {
 145                 ddrfreq_mode(false, &ddr.idle_rate, "idle");
 146         } else {
 147                 ddrfreq_mode(false, &ddr.normal_rate, "normal");
 148         }
 149 }
 150
 151 static int ddrfreq_task(void *data)
 152 {
 153         set_freezable();
 154
 155         do {
 156                 unsigned long status = ddr.sys_status;
 157                 ddrfreq_work(status);
 158                 wait_event_freezable(ddr.wait, (status != ddr.sys_status) || kthread_should_stop());
 159         } while (!kthread_should_stop());
 160
 161         return 0;
 162 }
 163
 164 #ifdef CONFIG_SMP
 165 static volatile bool __sramdata cpu_pause[NR_CPUS];
 166 static inline bool is_cpu_paused(unsigned int cpu) { smp_rmb(); return cpu_pause[cpu]; }
 167 static inline void set_cpu_pause(unsigned int cpu, bool pause) { cpu_pause[cpu] = pause; smp_wmb(); }
 168 static inline void set_other_cpus_pause(bool pause)
 169 {
 170         unsigned int cpu;
 171         for (cpu = 0; cpu < NR_CPUS; cpu++)
 172                 cpu_pause[cpu] = pause;
 173         smp_wmb();
 174 }
 175 #define MAX_TIMEOUT (16000000UL << 6) //>0.64s
 176
 177 /* Do not use stack, safe on SMP */
 178 static void __sramfunc pause_cpu(void *info)
 179 {
 180         u32 timeout = MAX_TIMEOUT;
 181         unsigned long flags;
 182         unsigned int cpu = raw_smp_processor_id();
 183
 184         local_irq_save(flags);
 185
 186         set_cpu_pause(cpu, true);
 187         while (is_cpu_paused(cpu) && --timeout);
 188
 189         local_irq_restore(flags);
 190 }
 191
 192 static int _ddr_change_freq_(uint32_t nMHz,struct ddr_freq_t ddr_freq_t)
 193 {
 194         u32 timeout = MAX_TIMEOUT;
 195         unsigned int cpu;
 196         unsigned int this_cpu = smp_processor_id();
 197         int ret;
 198
 199         cpu_maps_update_begin();
 200
 201         set_other_cpus_pause(false);
 202
 203         smp_call_function((smp_call_func_t)pause_cpu, NULL, 0);
 204         for_each_online_cpu(cpu) {
 205                 if (cpu == this_cpu)
 206                         continue;
 207                 while (!is_cpu_paused(cpu) && --timeout);
 208                 if (timeout == 0) {
 209                         pr_err("pause cpu %d timeout\n", cpu);
 210                         goto out;
 211                 }
 212         }
 213
 214 #ifdef CONFIG_ARCH_RK3026
 215         ret = ddr_change_freq(nMHz);
 216 #else
 217         ret = ddr_change_freq_sram(nMHz,ddr_freq_t);
 218 #endif
 219         set_other_cpus_pause(false);
 220
 221 out:
 222         cpu_maps_update_done();
 223
 224         return ret;
 225 }
 226
 227 static void _ddr_change_freq(uint32_t nMHz)
 228 {
 229         struct ddr_freq_t ddr_freq_t;
 230         int test_count=0;
 231
 232         ddr_freq_t.screen_ft_us = 0;
 233         ddr_freq_t.t0 = 0;
 234         ddr_freq_t.t1 = 0;
 235
 236 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
 237         do
 238         {
 239                 if(rk_fb_poll_wait_frame_complete() == true)
 240                 {
 241                         ddr_freq_t.t0 = cpu_clock(0);
 242                         ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
 243
 244                         test_count++;
 245                         //dprintk(DEBUG_VERBOSE,"test_count=%d\n",test_count);
 246                         usleep_range(ddr_freq_t.screen_ft_us-test_count*1000,ddr_freq_t.screen_ft_us-test_count*1000);
 247
 248                         flush_cache_all();
 249                         outer_flush_all();
 250                         flush_tlb_all();
 251                 }
 252         }while(_ddr_change_freq_(nMHz,ddr_freq_t)==0);
 253 #else
 254         _ddr_change_freq_(nMHz,ddr_freq_t);
 255 #endif
 256 }
 257 #else
 258 static void _ddr_change_freq(uint32_t nMHz)
 259 {
 260         ddr_change_freq(nMHz);
 261 }
 262 #endif
 263
 264 static void ddr_set_rate(uint32_t nMHz)
 265 {
 266         _ddr_change_freq(nMHz);
 267         ddr.clk->rate = ddr.clk->recalc(ddr.clk);
 268 }
 269
 270 #ifdef CONFIG_HAS_EARLYSUSPEND
 271 static void ddrfreq_early_suspend(struct early_suspend *h)
 272 {
 273         dprintk(DEBUG_SUSPEND, "early suspend\n");
 274         ddrfreq_set_sys_status(SYS_STATUS_SUSPEND);
 275 }
 276
 277 static void ddrfreq_late_resume(struct early_suspend *h)
 278 {
 279         dprintk(DEBUG_SUSPEND, "late resume\n");
 280         ddrfreq_clear_sys_status(SYS_STATUS_SUSPEND);
 281 }
 282 #endif
 283
 284 static int video_state_release(struct inode *inode, struct file *file)
 285 {
 286         dprintk(DEBUG_VIDEO_STATE, "video_state release\n");
 287         ddr.video_state = '0';
 288         ddrfreq_clear_sys_status(SYS_STATUS_VIDEO);
 289         return 0;
 290 }
 291
 292 #define VIDEO_LOW_RESOLUTION       (1080*720)
 293 static ssize_t video_state_write(struct file *file, const char __user *buffer,
 294                                  size_t count, loff_t *ppos)
 295 {
 296         char state;
 297         char *cookie_pot;
 298         char *p;
 299         char *buf = vzalloc(count);
 300         uint32_t v_width=0,v_height=0,v_sync=0;
 301         cookie_pot = buf;
 302
 303         if (count < 1)
 304                 return count;
 305         if (copy_from_user(cookie_pot, buffer, count)) {
 306                 return -EFAULT;
 307         }
 308
 309         dprintk(DEBUG_VIDEO_STATE, "video_state write %s,len %d\n", cookie_pot,count);
 310
 311         state=cookie_pot[0];
 312         if( (count>=3) && (cookie_pot[2]=='w') )
 313         {
 314                 strsep(&cookie_pot,",");
 315                 strsep(&cookie_pot,"=");
 316                 p=strsep(&cookie_pot,",");
 317                 v_width = simple_strtol(p,NULL,10);
 318                 strsep(&cookie_pot,"=");
 319                 p=strsep(&cookie_pot,",");
 320                 v_height= simple_strtol(p,NULL,10);
 321                 strsep(&cookie_pot,"=");
 322                 p=strsep(&cookie_pot,",");
 323                 v_sync= simple_strtol(p,NULL,10);
 324                 dprintk(DEBUG_VIDEO_STATE, "video_state %c,width=%d,height=%d,sync=%d\n", state,v_width,v_height,v_sync);
 325         }
 326
 327         switch (state) {
 328         case '0':
 329                 ddrfreq_clear_sys_status(SYS_STATUS_VIDEO);
 330                 ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_720P);
 331                 ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_1080P);
 332                 break;
 333         case '1':
 334                 ddrfreq_set_sys_status(SYS_STATUS_VIDEO);
 335
 336                 if( (v_width == 0) && (v_height == 0)){
 337                         ddrfreq_set_sys_status(SYS_STATUS_VIDEO_1080P);
 338                 }
 339                 else if(v_sync==1){
 340                         if(ddr.video_low_rate && ((v_width*v_height) <= VIDEO_LOW_RESOLUTION) )
 341                                 ddrfreq_set_sys_status(SYS_STATUS_VIDEO_720P);
 342                         else
 343                                 ddrfreq_set_sys_status(SYS_STATUS_VIDEO_1080P);
 344                 }
 345                 else{
 346                         ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_720P);
 347                         ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_1080P);
 348                 }
 349                 break;
 350         default:
 351                 return -EINVAL;
 352
 353         }
 354         ddr.video_state = state;
 355         return count;
 356 }
 357
 358 static const struct file_operations video_state_fops = {
 359         .owner  = THIS_MODULE,
 360         .release= video_state_release,
 361         .write  = video_state_write,
 362 };
 363
 364 static struct miscdevice video_state_dev = {
 365         .fops   = &video_state_fops,
 366         .name   = "video_state",
 367         .minor  = MISC_DYNAMIC_MINOR,
 368 };
 369
 370 static int ddrfreq_clk_event(enum SYS_STATUS status, unsigned long event)
 371 {
 372         switch (event) {
 373         case CLK_PRE_ENABLE:
 374                 ddrfreq_set_sys_status(status);
 375                 break;
 376         case CLK_ABORT_ENABLE:
 377         case CLK_POST_DISABLE:
 378                 ddrfreq_clear_sys_status(status);
 379                 break;
 380         }
 381
 382         return NOTIFY_OK;
 383 }
 384
 385 #define CLK_NOTIFIER(name, status) \
 386 static int ddrfreq_clk_##name##_event(struct notifier_block *this, unsigned long event, void *ptr) \
 387 { \
 388         return ddrfreq_clk_event(SYS_STATUS_##status, event); \
 389 } \
 390 static struct notifier_block ddrfreq_clk_##name##_notifier = { .notifier_call = ddrfreq_clk_##name##_event };
 391
 392 #define REGISTER_CLK_NOTIFIER(name) \
 393 do { \
 394         struct clk *clk = clk_get(NULL, #name); \
 395         clk_notifier_register(clk, &ddrfreq_clk_##name##_notifier); \
 396         clk_put(clk); \
 397 } while (0)
 398
 399 #define UNREGISTER_CLK_NOTIFIER(name) \
 400 do { \
 401         struct clk *clk = clk_get(NULL, #name); \
 402         clk_notifier_unregister(clk, &ddrfreq_clk_##name##_notifier); \
 403         clk_put(clk); \
 404 } while (0)
 405
 406 CLK_NOTIFIER(pd_gpu, GPU);
 407 CLK_NOTIFIER(pd_rga, RGA);
 408 CLK_NOTIFIER(pd_cif0, CIF0);
 409 CLK_NOTIFIER(pd_cif1, CIF1);
 410 CLK_NOTIFIER(pd_lcdc0, LCDC0);
 411 CLK_NOTIFIER(pd_lcdc1, LCDC1);
 412
 413 static int ddrfreq_reboot_notifier_event(struct notifier_block *this, unsigned long event, void *ptr)
 414 {
 415         u32 timeout = 1000; // 10s
 416         ddrfreq_set_sys_status(SYS_STATUS_REBOOT);
 417         while (clk_get_rate(ddr.clk) != ddr.reboot_rate && --timeout) {
 418                 msleep(10);
 419         }
 420         if (!timeout) {
 421                 pr_err("failed to set ddr clk from %luMHz to %luMHz when shutdown/reboot\n", clk_get_rate(ddr.clk) / MHZ, ddr.reboot_rate / MHZ);
 422         }
 423         return NOTIFY_OK;
 424 }
 425
 426 static struct notifier_block ddrfreq_reboot_notifier = {
 427         .notifier_call = ddrfreq_reboot_notifier_event,
 428 };
 429
 430 static int ddr_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
 431 {
 432         ddr_set_rate(rate/(1000*1000));
 433         /* return 0 when ok */
 434         return !( (clk_get_rate(clk)/MHZ) == (rate/MHZ));
 435 }
 436
 437 #if defined(CONFIG_ARCH_RK3066B)
 438 static int ddrfreq_scanfreq_datatraing_3168(void)
 439 {
 440     struct cpufreq_frequency_table *table;
 441     uint32_t dqstr_freq,dqstr_value;
 442     uint32_t min_freq,max_freq;
 443     int i;
 444     table = dvfs_get_freq_volt_table(clk_get(NULL, "ddr"));
 445     if (!table)
 446     {
 447         pr_err("failed to get ddr freq volt table\n");
 448     }
 449     for (i = 0; table && table[i].frequency != CPUFREQ_TABLE_END; i++)
 450     {
 451         if(i == 0)
 452             min_freq = table[i].frequency / 1000;
 453
 454         max_freq = table[i].frequency / 1000;
 455     }
 456
 457     //get data training value for RK3066B ddr_change_freq
 458     for(dqstr_freq=min_freq; dqstr_freq<=max_freq; dqstr_freq=dqstr_freq+50)
 459     {
 460         if (clk_set_rate(ddr.clk, dqstr_freq*MHZ) != 0)
 461         {
 462             pr_err("failed to clk_set_rate ddr.clk %dhz\n",dqstr_freq*MHZ);
 463         }
 464         dqstr_value=(dqstr_freq-min_freq+1)/50;
 465
 466         ddr_get_datatraing_value_3168(false,dqstr_value,min_freq);
 467     }
 468     ddr_get_datatraing_value_3168(true,0,min_freq);
 469     dprintk(DEBUG_DDR,"get datatraing from %dMhz to %dMhz\n",min_freq,max_freq);
 470     return 0;
 471 }
 472 #endif
 473
 474 static int ddrfreq_init(void)
 475 {
 476         int i, ret;
 477         struct cpufreq_frequency_table *table;
 478         int ddrfreq_version = 0;
 479
 480         init_waitqueue_head(&ddr.wait);
 481         ddr.video_state = '0';
 482         ddr.mode = "normal";
 483
 484         ddr.pll = clk_get(NULL, "ddr_pll");
 485         ddr.clk = clk_get(NULL, "ddr");
 486         if (IS_ERR(ddr.clk)) {
 487                 ret = PTR_ERR(ddr.clk);
 488                 ddr.clk = NULL;
 489                 pr_err("failed to get ddr clk, error %d\n", ret);
 490                 return ret;
 491         }
 492         dvfs_clk_register_set_rate_callback(ddr.clk, ddr_scale_rate_for_dvfs);
 493
 494         ddr.normal_rate = clk_get_rate(ddr.clk);
 495         ddr.reboot_rate = ddr.normal_rate;
 496
 497         table = dvfs_get_freq_volt_table(ddr.clk);
 498         if (!table) {
 499                 pr_err("failed to get ddr freq volt table\n");
 500         }
 501
 502         for (i = 0; table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
 503                 if (table[i].frequency % 1000) {
 504                         ddrfreq_version = 1;
 505                 }
 506
 507                 if (table[i].frequency % 1000 > 100) {
 508                         ddrfreq_version = 2;
 509                         break;
 510                 }
 511         }
 512
 513         if (ddrfreq_version==0) {
 514                 ddr.video_rate = 300 * MHZ;
 515                 ddr.dualview_rate = ddr.normal_rate;
 516                 ddr.suspend_rate = 200 * MHZ;
 517         }
 518
 519         for (i = 0; ddrfreq_version == 1 && table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
 520                 unsigned int mode = table[i].frequency % 1000;
 521                 unsigned long rate;
 522
 523                 table[i].frequency -= mode;
 524                 rate = table[i].frequency * 1000;
 525
 526                 switch (mode) {
 527                 case DDR_FREQ_NORMAL:
 528                         ddr.normal_rate = rate;
 529                         break;
 530                 case DDR_FREQ_VIDEO_LOW:
 531                         ddr.video_low_rate = rate;
 532                         break;
 533                 case DDR_FREQ_VIDEO:
 534                         ddr.video_rate = rate;
 535                         break;
 536                 case DDR_FREQ_DUALVIEW:
 537                         ddr.dualview_rate= rate;
 538                         break;
 539                 case DDR_FREQ_IDLE:
 540                         ddr.idle_rate = rate;
 541                         break;
 542                 case DDR_FREQ_SUSPEND:
 543                         ddr.suspend_rate = rate;
 544                         break;
 545                 }
 546         }
 547
 548         for (i = 0; ddrfreq_version == 2 && table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
 549                 unsigned int mode = table[i].frequency % 1000;
 550                 unsigned long rate;
 551
 552                 table[i].frequency -= mode;
 553                 rate = table[i].frequency * 1000;
 554
 555                 if( (mode&DDR_FREQ_NORMAL) == DDR_FREQ_NORMAL)
 556                         ddr.normal_rate = rate;
 557
 558                 if( (mode&DDR_FREQ_VIDEO_LOW) == DDR_FREQ_VIDEO_LOW)
 559                         ddr.video_low_rate = rate;
 560
 561                 if( (mode&DDR_FREQ_VIDEO) == DDR_FREQ_VIDEO)
 562                         ddr.video_rate = rate;
 563
 564                 if( (mode&DDR_FREQ_DUALVIEW) == DDR_FREQ_DUALVIEW)
 565                         ddr.dualview_rate= rate;
 566
 567                 if( (mode&DDR_FREQ_IDLE) == DDR_FREQ_IDLE)
 568                         ddr.idle_rate = rate;
 569
 570                 if( (mode&DDR_FREQ_SUSPEND) == DDR_FREQ_SUSPEND)
 571                         ddr.suspend_rate = rate;
 572         }
 573
 574         if (ddr.idle_rate) {
 575                 REGISTER_CLK_NOTIFIER(pd_gpu);
 576                 REGISTER_CLK_NOTIFIER(pd_rga);
 577                 REGISTER_CLK_NOTIFIER(pd_cif0);
 578                 REGISTER_CLK_NOTIFIER(pd_cif1);
 579         }
 580
 581         if (ddr.dualview_rate) {
 582              REGISTER_CLK_NOTIFIER(pd_lcdc0);
 583              REGISTER_CLK_NOTIFIER(pd_lcdc1);
 584         }
 585
 586         return 0;
 587
 588 }
 589 core_initcall(ddrfreq_init);
 590
 591 static int ddrfreq_late_init(void)
 592 {
 593         int ret;
 594         struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
 595
 596         if (!ddr.clk) {
 597                 return -EINVAL;
 598         }
 599
 600         ret = misc_register(&video_state_dev);
 601         if (unlikely(ret)) {
 602                 pr_err("failed to register video_state misc device! error %d\n", ret);
 603                 goto err;
 604         }
 605
 606 #ifdef CONFIG_HAS_EARLYSUSPEND
 607         ddr.early_suspend.suspend = ddrfreq_early_suspend;
 608         ddr.early_suspend.resume = ddrfreq_late_resume;
 609         ddr.early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 50;
 610         register_early_suspend(&ddr.early_suspend);
 611 #endif
 612
 613 #if defined(CONFIG_ARCH_RK3066B)
 614        ddrfreq_scanfreq_datatraing_3168();
 615 #endif
 616
 617         ddr.task = kthread_create(ddrfreq_task, NULL, "ddrfreqd");
 618         if (IS_ERR(ddr.task)) {
 619                 ret = PTR_ERR(ddr.task);
 620                 pr_err("failed to create kthread! error %d\n", ret);
 621                 goto err1;
 622         }
 623
 624         sched_setscheduler_nocheck(ddr.task, SCHED_FIFO, &param);
 625         get_task_struct(ddr.task);
 626         kthread_bind(ddr.task, 0);
 627         wake_up_process(ddr.task);
 628
 629         register_reboot_notifier(&ddrfreq_reboot_notifier);
 630
 631         pr_info("verion 3.1 20130805 1\n");
 632         dprintk(DEBUG_DDR, "normal %luMHz video %luMHz video_low %luMHz dualview %luMHz idle %luMHz suspend %luMHz reboot %luMHz\n",
 633                 ddr.normal_rate / MHZ, ddr.video_rate / MHZ, ddr.video_low_rate / MHZ, ddr.dualview_rate / MHZ, ddr.idle_rate / MHZ, ddr.suspend_rate / MHZ, ddr.reboot_rate / MHZ);
 634
 635         return 0;
 636
 637 err1:
 638 #ifdef CONFIG_HAS_EARLYSUSPEND
 639         unregister_early_suspend(&ddr.early_suspend);
 640 #endif
 641         misc_deregister(&video_state_dev);
 642 err:
 643         if (ddr.idle_rate) {
 644                 UNREGISTER_CLK_NOTIFIER(pd_gpu);
 645                 UNREGISTER_CLK_NOTIFIER(pd_rga);
 646                 UNREGISTER_CLK_NOTIFIER(pd_cif0);
 647                 UNREGISTER_CLK_NOTIFIER(pd_cif1);
 648         }
 649        if (ddr.dualview_rate) {
 650         UNREGISTER_CLK_NOTIFIER(pd_lcdc0);
 651         UNREGISTER_CLK_NOTIFIER(pd_lcdc1);
 652        }
 653
 654         return ret;
 655 }
 656 late_initcall(ddrfreq_late_init);