arch/arm/plat-rk/vpu_service.c

   1 /* arch/arm/mach-rk29/vpu.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  * author: chenhengming chm@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifdef CONFIG_RK29_VPU_DEBUG
  18 #define DEBUG
  19 #define pr_fmt(fmt) "VPU_SERVICE: %s: " fmt, __func__
  20 #else
  21 #define pr_fmt(fmt) "VPU_SERVICE: " fmt
  22 #endif
  23
  24
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/fs.h>
  33 #include <linux/ioport.h>
  34 #include <linux/miscdevice.h>
  35 #include <linux/mm.h>
  36 #include <linux/poll.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/wakelock.h>
  41
  42 #include <asm/uaccess.h>
  43
  44 #include <mach/irqs.h>
  45 #include <mach/pmu.h>
  46 #include <mach/cru.h>
  47
  48 #include <plat/vpu_service.h>
  49 #include <plat/cpu.h>
  50
  51 typedef enum {
  52         VPU_DEC_ID_9190         = 0x6731,
  53         VPU_ID_8270             = 0x8270,
  54         VPU_ID_4831             = 0x4831,
  55 } VPU_HW_ID;
  56
  57 typedef enum {
  58         VPU_DEC_TYPE_9190       = 0,
  59         VPU_ENC_TYPE_8270       = 0x100,
  60         VPU_ENC_TYPE_4831       ,
  61 } VPU_HW_TYPE_E;
  62
  63 typedef enum VPU_FREQ {
  64         VPU_FREQ_200M,
  65         VPU_FREQ_266M,
  66         VPU_FREQ_300M,
  67         VPU_FREQ_400M,
  68         VPU_FREQ_DEFAULT,
  69 } VPU_FREQ;
  70
  71 typedef struct {
  72         VPU_HW_ID               hw_id;
  73         unsigned long           hw_addr;
  74         unsigned long           enc_offset;
  75         unsigned long           enc_reg_num;
  76         unsigned long           enc_io_size;
  77         unsigned long           dec_offset;
  78         unsigned long           dec_reg_num;
  79         unsigned long           dec_io_size;
  80 } VPU_HW_INFO_E;
  81
  82 #define MHZ                                     (1000*1000)
  83
  84 #define VCODEC_PHYS                             (0x10104000)
  85
  86 #define REG_NUM_9190_DEC                        (60)
  87 #define REG_NUM_9190_PP                         (41)
  88 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
  89
  90 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
  91
  92 #define REG_NUM_ENC_8270                        (96)
  93 #define REG_SIZE_ENC_8270                       (0x200)
  94 #define REG_NUM_ENC_4831                        (164)
  95 #define REG_SIZE_ENC_4831                       (0x400)
  96
  97 #define SIZE_REG(reg)                           ((reg)*4)
  98
  99 VPU_HW_INFO_E vpu_hw_set[] = {
 100         [0] = {
 101                 .hw_id          = VPU_ID_8270,
 102                 .hw_addr        = VCODEC_PHYS,
 103                 .enc_offset     = 0x0,
 104                 .enc_reg_num    = REG_NUM_ENC_8270,
 105                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 106                 .dec_offset     = REG_SIZE_ENC_8270,
 107                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 108                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 109         },
 110         [1] = {
 111                 .hw_id          = VPU_ID_4831,
 112                 .hw_addr        = VCODEC_PHYS,
 113                 .enc_offset     = 0x0,
 114                 .enc_reg_num    = REG_NUM_ENC_4831,
 115                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 116                 .dec_offset     = REG_SIZE_ENC_4831,
 117                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 118                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 119         },
 120 };
 121
 122
 123 #define DEC_INTERRUPT_REGISTER                  1
 124 #define PP_INTERRUPT_REGISTER                   60
 125 #define ENC_INTERRUPT_REGISTER                  1
 126
 127 #define DEC_INTERRUPT_BIT                        0x100
 128 #define PP_INTERRUPT_BIT                         0x100
 129 #define ENC_INTERRUPT_BIT                        0x1
 130
 131 #define VPU_REG_EN_ENC                          14
 132 #define VPU_REG_ENC_GATE                        2
 133 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 134
 135 #define VPU_REG_EN_DEC                          1
 136 #define VPU_REG_DEC_GATE                        2
 137 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 138 #define VPU_REG_EN_PP                           0
 139 #define VPU_REG_PP_GATE                         1
 140 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 141 #define VPU_REG_EN_DEC_PP                       1
 142 #define VPU_REG_DEC_PP_GATE                     61
 143 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 144
 145 /**
 146  * struct for process session which connect to vpu
 147  *
 148  * @author ChenHengming (2011-5-3)
 149  */
 150 typedef struct vpu_session {
 151         VPU_CLIENT_TYPE         type;
 152         /* a linked list of data so we can access them for debugging */
 153         struct list_head        list_session;
 154         /* a linked list of register data waiting for process */
 155         struct list_head        waiting;
 156         /* a linked list of register data in processing */
 157         struct list_head        running;
 158         /* a linked list of register data processed */
 159         struct list_head        done;
 160         wait_queue_head_t       wait;
 161         pid_t                   pid;
 162         atomic_t                task_running;
 163 } vpu_session;
 164
 165 /**
 166  * struct for process register set
 167  *
 168  * @author ChenHengming (2011-5-4)
 169  */
 170 typedef struct vpu_reg {
 171         VPU_CLIENT_TYPE         type;
 172         VPU_FREQ                freq;
 173         vpu_session             *session;
 174         struct list_head        session_link;           /* link to vpu service session */
 175         struct list_head        status_link;            /* link to register set list */
 176         unsigned long           size;
 177         unsigned long           *reg;
 178 } vpu_reg;
 179
 180 typedef struct vpu_device {
 181         atomic_t                irq_count_codec;
 182         atomic_t                irq_count_pp;
 183         unsigned long           iobaseaddr;
 184         unsigned int            iosize;
 185         volatile u32            *hwregs;
 186 } vpu_device;
 187
 188 typedef struct vpu_service_info {
 189         struct wake_lock        wake_lock;
 190         struct delayed_work     power_off_work;
 191         struct mutex            lock;
 192         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */
 193         struct list_head        running;                /* link to link_reg in struct vpu_reg */
 194         struct list_head        done;                   /* link to link_reg in struct vpu_reg */
 195         struct list_head        session;                /* link to list_session in struct vpu_session */
 196         atomic_t                total_running;
 197         bool                    enabled;
 198         vpu_reg                 *reg_codec;
 199         vpu_reg                 *reg_pproc;
 200         vpu_reg                 *reg_resev;
 201         VPUHwDecConfig_t        dec_config;
 202         VPUHwEncConfig_t        enc_config;
 203         VPU_HW_INFO_E           *hw_info;
 204         unsigned long           reg_size;
 205         bool                    auto_freq;
 206 } vpu_service_info;
 207
 208 typedef struct vpu_request
 209 {
 210         unsigned long   *req;
 211         unsigned long   size;
 212 } vpu_request;
 213
 214 static struct clk *pd_video;
 215 static struct clk *aclk_vepu;
 216 static struct clk *hclk_vepu;
 217 static struct clk *aclk_ddr_vepu;
 218 static struct clk *hclk_cpu_vcodec;
 219 static vpu_service_info service;
 220 static vpu_device       dec_dev;
 221 static vpu_device       enc_dev;
 222
 223 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 224 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 225
 226 static void vpu_get_clk(void)
 227 {
 228         pd_video        = clk_get(NULL, "pd_video");
 229         aclk_vepu       = clk_get(NULL, "aclk_vepu");
 230         hclk_vepu       = clk_get(NULL, "hclk_vepu");
 231         aclk_ddr_vepu   = clk_get(NULL, "aclk_ddr_vepu");
 232         hclk_cpu_vcodec = clk_get(NULL, "hclk_cpu_vcodec");
 233 }
 234
 235 static void vpu_put_clk(void)
 236 {
 237         clk_put(pd_video);
 238         clk_put(aclk_vepu);
 239         clk_put(hclk_vepu);
 240         clk_put(aclk_ddr_vepu);
 241         clk_put(hclk_cpu_vcodec);
 242 }
 243
 244 static void vpu_reset(void)
 245 {
 246 #if defined(CONFIG_ARCH_RK29)
 247         clk_disable(aclk_ddr_vepu);
 248         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 249         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 250         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 251         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 252         mdelay(10);
 253         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 254         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 255         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 256         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 257         clk_enable(aclk_ddr_vepu);
 258 #elif defined(CONFIG_ARCH_RK30)
 259         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 260         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 261         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 262         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 263         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 264         mdelay(1);
 265         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 266         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 267         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 268         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 269         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 270 #endif
 271         service.reg_codec = NULL;
 272         service.reg_pproc = NULL;
 273         service.reg_resev = NULL;
 274 }
 275
 276 static void reg_deinit(vpu_reg *reg);
 277 static void vpu_service_session_clear(vpu_session *session)
 278 {
 279         vpu_reg *reg, *n;
 280         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 281                 reg_deinit(reg);
 282         }
 283         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 284                 reg_deinit(reg);
 285         }
 286         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 287                 reg_deinit(reg);
 288         }
 289 }
 290
 291 static void vpu_service_dump(void)
 292 {
 293         int running;
 294         vpu_reg *reg, *reg_tmp;
 295         vpu_session *session, *session_tmp;
 296
 297         running = atomic_read(&service.total_running);
 298         printk("total_running %d\n", running);
 299
 300         printk("reg_codec 0x%.8x\n", (unsigned int)service.reg_codec);
 301         printk("reg_pproc 0x%.8x\n", (unsigned int)service.reg_pproc);
 302         printk("reg_resev 0x%.8x\n", (unsigned int)service.reg_resev);
 303
 304         list_for_each_entry_safe(session, session_tmp, &service.session, list_session) {
 305                 printk("session pid %d type %d:\n", session->pid, session->type);
 306                 running = atomic_read(&session->task_running);
 307                 printk("task_running %d\n", running);
 308                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
 309                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);
 310                 }
 311                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
 312                         printk("running register set 0x%.8x\n", (unsigned int)reg);
 313                 }
 314                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
 315                         printk("done    register set 0x%.8x\n", (unsigned int)reg);
 316                 }
 317         }
 318 }
 319
 320 static void vpu_service_power_off(void)
 321 {
 322         int total_running;
 323         if (!service.enabled) {
 324                 return;
 325         }
 326
 327         service.enabled = false;
 328         total_running = atomic_read(&service.total_running);
 329         if (total_running) {
 330                 pr_alert("alert: power off when %d task running!!\n", total_running);
 331                 mdelay(50);
 332                 pr_alert("alert: delay 50 ms for running task\n");
 333                 vpu_service_dump();
 334         }
 335
 336         printk("vpu: power off...");
 337 #ifdef CONFIG_ARCH_RK29
 338         pmu_set_power_domain(PD_VCODEC, false);
 339 #else
 340         clk_disable(pd_video);
 341 #endif
 342         udelay(10);
 343         clk_disable(hclk_cpu_vcodec);
 344         clk_disable(aclk_ddr_vepu);
 345         clk_disable(hclk_vepu);
 346         clk_disable(aclk_vepu);
 347         wake_unlock(&service.wake_lock);
 348         printk("done\n");
 349 }
 350
 351 static inline void vpu_queue_power_off_work(void)
 352 {
 353         queue_delayed_work(system_nrt_wq, &service.power_off_work, VPU_POWER_OFF_DELAY);
 354 }
 355
 356 static void vpu_power_off_work(struct work_struct *work)
 357 {
 358         if (mutex_trylock(&service.lock)) {
 359                 vpu_service_power_off();
 360                 mutex_unlock(&service.lock);
 361         } else {
 362                 /* Come back later if the device is busy... */
 363                 vpu_queue_power_off_work();
 364         }
 365 }
 366
 367 static void vpu_service_power_on(void)
 368 {
 369         static ktime_t last;
 370         ktime_t now = ktime_get();
 371         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 372                 cancel_delayed_work_sync(&service.power_off_work);
 373                 vpu_queue_power_off_work();
 374                 last = now;
 375         }
 376         if (service.enabled)
 377                 return ;
 378
 379         service.enabled = true;
 380         printk("vpu: power on\n");
 381
 382         clk_enable(aclk_vepu);
 383         clk_enable(hclk_vepu);
 384         clk_enable(hclk_cpu_vcodec);
 385         udelay(10);
 386 #ifdef CONFIG_ARCH_RK29
 387         pmu_set_power_domain(PD_VCODEC, true);
 388 #else
 389         clk_enable(pd_video);
 390 #endif
 391         udelay(10);
 392         clk_enable(aclk_ddr_vepu);
 393         wake_lock(&service.wake_lock);
 394 }
 395
 396 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 397 {
 398         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
 399         return ((type == 8) || (type == 4));
 400 }
 401
 402 static inline bool reg_check_interlace(vpu_reg *reg)
 403 {
 404         unsigned long type = (reg->reg[3] & (1 << 23));
 405         return (type > 0);
 406 }
 407
 408 static vpu_reg *reg_init(vpu_session *session, void __user *src, unsigned long size)
 409 {
 410         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+service.reg_size, GFP_KERNEL);
 411         if (NULL == reg) {
 412                 pr_err("error: kmalloc fail in reg_init\n");
 413                 return NULL;
 414         }
 415
 416         reg->session = session;
 417         reg->type = session->type;
 418         reg->size = size;
 419         reg->freq = VPU_FREQ_DEFAULT;
 420         reg->reg = (unsigned long *)&reg[1];
 421         INIT_LIST_HEAD(&reg->session_link);
 422         INIT_LIST_HEAD(&reg->status_link);
 423
 424         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
 425                 pr_err("error: copy_from_user failed in reg_init\n");
 426                 kfree(reg);
 427                 return NULL;
 428         }
 429
 430         mutex_lock(&service.lock);
 431         list_add_tail(&reg->status_link, &service.waiting);
 432         list_add_tail(&reg->session_link, &session->waiting);
 433         mutex_unlock(&service.lock);
 434
 435         if (service.auto_freq) {
 436                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 437                         if (reg_check_rmvb_wmv(reg)) {
 438                                 reg->freq = VPU_FREQ_266M;
 439                         } else {
 440                                 if (reg_check_interlace(reg)) {
 441                                         reg->freq = VPU_FREQ_400M;
 442                                 }
 443                         }
 444                 }
 445                 if (reg->type == VPU_PP) {
 446                         reg->freq = VPU_FREQ_400M;
 447                 }
 448         }
 449
 450         return reg;
 451 }
 452
 453 static void reg_deinit(vpu_reg *reg)
 454 {
 455         list_del_init(&reg->session_link);
 456         list_del_init(&reg->status_link);
 457         if (reg == service.reg_codec) service.reg_codec = NULL;
 458         if (reg == service.reg_pproc) service.reg_pproc = NULL;
 459         kfree(reg);
 460 }
 461
 462 static void reg_from_wait_to_run(vpu_reg *reg)
 463 {
 464         list_del_init(&reg->status_link);
 465         list_add_tail(&reg->status_link, &service.running);
 466
 467         list_del_init(&reg->session_link);
 468         list_add_tail(&reg->session_link, &reg->session->running);
 469 }
 470
 471 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
 472 {
 473         int i;
 474         u32 *dst = (u32 *)&reg->reg[0];
 475         for (i = 0; i < count; i++)
 476                 *dst++ = *src++;
 477 }
 478
 479 static void reg_from_run_to_done(vpu_reg *reg)
 480 {
 481         list_del_init(&reg->status_link);
 482         list_add_tail(&reg->status_link, &service.done);
 483
 484         list_del_init(&reg->session_link);
 485         list_add_tail(&reg->session_link, &reg->session->done);
 486
 487         switch (reg->type) {
 488         case VPU_ENC : {
 489                 service.reg_codec = NULL;
 490                 reg_copy_from_hw(reg, enc_dev.hwregs, service.hw_info->enc_reg_num);
 491                 break;
 492         }
 493         case VPU_DEC : {
 494                 service.reg_codec = NULL;
 495                 reg_copy_from_hw(reg, dec_dev.hwregs, REG_NUM_9190_DEC);
 496                 break;
 497         }
 498         case VPU_PP : {
 499                 service.reg_pproc = NULL;
 500                 reg_copy_from_hw(reg, dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
 501                 dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
 502                 break;
 503         }
 504         case VPU_DEC_PP : {
 505                 service.reg_codec = NULL;
 506                 service.reg_pproc = NULL;
 507                 reg_copy_from_hw(reg, dec_dev.hwregs, REG_NUM_9190_DEC_PP);
 508                 dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
 509                 break;
 510         }
 511         default : {
 512                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
 513                 break;
 514         }
 515         }
 516         atomic_sub(1, &reg->session->task_running);
 517         atomic_sub(1, &service.total_running);
 518         wake_up_interruptible_sync(&reg->session->wait);
 519 }
 520
 521 static void vpu_service_set_freq(vpu_reg *reg)
 522 {
 523         switch (reg->freq) {
 524         case VPU_FREQ_200M : {
 525                 clk_set_rate(aclk_vepu, 200*MHZ);
 526         } break;
 527         case VPU_FREQ_266M : {
 528                 clk_set_rate(aclk_vepu, 266*MHZ);
 529         } break;
 530         case VPU_FREQ_300M : {
 531                 clk_set_rate(aclk_vepu, 300*MHZ);
 532         } break;
 533         case VPU_FREQ_400M : {
 534                 clk_set_rate(aclk_vepu, 400*MHZ);
 535         } break;
 536         default : {
 537                 clk_set_rate(aclk_vepu, 300*MHZ);
 538         } break;
 539         }
 540 }
 541
 542 static void reg_copy_to_hw(vpu_reg *reg)
 543 {
 544         int i;
 545         u32 *src = (u32 *)&reg->reg[0];
 546         atomic_add(1, &service.total_running);
 547         atomic_add(1, &reg->session->task_running);
 548         if (service.auto_freq) {
 549                 vpu_service_set_freq(reg);
 550         }
 551         switch (reg->type) {
 552         case VPU_ENC : {
 553                 int enc_count = service.hw_info->enc_reg_num;
 554                 u32 *dst = (u32 *)enc_dev.hwregs;
 555 #if defined(CONFIG_ARCH_RK30)
 556                 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 557                 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 558                 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 559                 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 560 #endif
 561                 service.reg_codec = reg;
 562
 563                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
 564
 565                 for (i = 0; i < VPU_REG_EN_ENC; i++)
 566                         dst[i] = src[i];
 567
 568                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
 569                         dst[i] = src[i];
 570
 571                 dsb();
 572
 573                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
 574                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
 575         } break;
 576         case VPU_DEC : {
 577                 u32 *dst = (u32 *)dec_dev.hwregs;
 578                 service.reg_codec = reg;
 579
 580                 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
 581                         dst[i] = src[i];
 582
 583                 dsb();
 584
 585                 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
 586                 dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];
 587         } break;
 588         case VPU_PP : {
 589                 u32 *dst = (u32 *)dec_dev.hwregs + PP_INTERRUPT_REGISTER;
 590                 service.reg_pproc = reg;
 591
 592                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
 593
 594                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
 595                         dst[i] = src[i];
 596
 597                 dsb();
 598
 599                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
 600         } break;
 601         case VPU_DEC_PP : {
 602                 u32 *dst = (u32 *)dec_dev.hwregs;
 603                 service.reg_codec = reg;
 604                 service.reg_pproc = reg;
 605
 606                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
 607                         dst[i] = src[i];
 608
 609                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
 610                 dsb();
 611
 612                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
 613                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
 614                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
 615         } break;
 616         default : {
 617                 pr_err("error: unsupport session type %d", reg->type);
 618                 atomic_sub(1, &service.total_running);
 619                 atomic_sub(1, &reg->session->task_running);
 620                 break;
 621         }
 622         }
 623 }
 624
 625 static void try_set_reg(void)
 626 {
 627         // first get reg from reg list
 628         if (!list_empty(&service.waiting)) {
 629                 int can_set = 0;
 630                 vpu_reg *reg = list_entry(service.waiting.next, vpu_reg, status_link);
 631
 632                 vpu_service_power_on();
 633
 634                 switch (reg->type) {
 635                 case VPU_ENC : {
 636                         if ((NULL == service.reg_codec) &&  (NULL == service.reg_pproc))
 637                                 can_set = 1;
 638                 } break;
 639                 case VPU_DEC : {
 640                         if (NULL == service.reg_codec)
 641                                 can_set = 1;
 642                         if (service.auto_freq && (NULL != service.reg_pproc)) {
 643                                 can_set = 0;
 644                         }
 645                 } break;
 646                 case VPU_PP : {
 647                         if (NULL == service.reg_codec) {
 648                                 if (NULL == service.reg_pproc)
 649                                         can_set = 1;
 650                         } else {
 651                                 if ((VPU_DEC == service.reg_codec->type) && (NULL == service.reg_pproc))
 652                                         can_set = 1;
 653                                 // can not charge frequency when vpu is working
 654                                 if (service.auto_freq) {
 655                                         can_set = 0;
 656                                 }
 657                         }
 658                 } break;
 659                 case VPU_DEC_PP : {
 660                         if ((NULL == service.reg_codec) && (NULL == service.reg_pproc))
 661                                 can_set = 1;
 662                         } break;
 663                 default : {
 664                         printk("undefined reg type %d\n", reg->type);
 665                 } break;
 666                 }
 667                 if (can_set) {
 668                         reg_from_wait_to_run(reg);
 669                         reg_copy_to_hw(reg);
 670                 }
 671         }
 672 }
 673
 674 static int return_reg(vpu_reg *reg, u32 __user *dst)
 675 {
 676         int ret = 0;
 677         switch (reg->type) {
 678         case VPU_ENC : {
 679                 if (copy_to_user(dst, &reg->reg[0], service.hw_info->enc_io_size))
 680                         ret = -EFAULT;
 681                 break;
 682         }
 683         case VPU_DEC : {
 684                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC)))
 685                         ret = -EFAULT;
 686                 break;
 687         }
 688         case VPU_PP : {
 689                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
 690                         ret = -EFAULT;
 691                 break;
 692         }
 693         case VPU_DEC_PP : {
 694                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
 695                         ret = -EFAULT;
 696                 break;
 697         }
 698         default : {
 699                 ret = -EFAULT;
 700                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);
 701                 break;
 702         }
 703         }
 704         reg_deinit(reg);
 705         return ret;
 706 }
 707
 708 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 709 {
 710         vpu_session *session = (vpu_session *)filp->private_data;
 711         if (NULL == session) {
 712                 return -EINVAL;
 713         }
 714
 715         switch (cmd) {
 716         case VPU_IOC_SET_CLIENT_TYPE : {
 717                 session->type = (VPU_CLIENT_TYPE)arg;
 718                 break;
 719         }
 720         case VPU_IOC_GET_HW_FUSE_STATUS : {
 721                 vpu_request req;
 722                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
 723                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
 724                         return -EFAULT;
 725                 } else {
 726                         if (VPU_ENC != session->type) {
 727                                 if (copy_to_user((void __user *)req.req, &service.dec_config, sizeof(VPUHwDecConfig_t))) {
 728                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
 729                                         return -EFAULT;
 730                                 }
 731                         } else {
 732                                 if (copy_to_user((void __user *)req.req, &service.enc_config, sizeof(VPUHwEncConfig_t))) {
 733                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
 734                                         return -EFAULT;
 735                                 }
 736                         }
 737                 }
 738
 739                 break;
 740         }
 741         case VPU_IOC_SET_REG : {
 742                 vpu_request req;
 743                 vpu_reg *reg;
 744                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
 745                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
 746                         return -EFAULT;
 747                 }
 748
 749                 reg = reg_init(session, (void __user *)req.req, req.size);
 750                 if (NULL == reg) {
 751                         return -EFAULT;
 752                 } else {
 753                         mutex_lock(&service.lock);
 754                         try_set_reg();
 755                         mutex_unlock(&service.lock);
 756                 }
 757
 758                 break;
 759         }
 760         case VPU_IOC_GET_REG : {
 761                 vpu_request req;
 762                 vpu_reg *reg;
 763                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
 764                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
 765                         return -EFAULT;
 766                 } else {
 767                         int ret = wait_event_interruptible_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
 768                         if (!list_empty(&session->done)) {
 769                                 if (ret < 0) {
 770                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
 771                                 }
 772                                 ret = 0;
 773                         } else {
 774                                 if (unlikely(ret < 0)) {
 775                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
 776                                 } else if (0 == ret) {
 777                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
 778                                         ret = -ETIMEDOUT;
 779                                 }
 780                         }
 781                         if (ret < 0) {
 782                                 int task_running = atomic_read(&session->task_running);
 783                                 mutex_lock(&service.lock);
 784                                 vpu_service_dump();
 785                                 if (task_running) {
 786                                         atomic_set(&session->task_running, 0);
 787                                         atomic_sub(task_running, &service.total_running);
 788                                         printk("%d task is running but not return, reset hardware...", task_running);
 789                                         vpu_reset();
 790                                         printk("done\n");
 791                                 }
 792                                 vpu_service_session_clear(session);
 793                                 mutex_unlock(&service.lock);
 794                                 return ret;
 795                         }
 796                 }
 797                 mutex_lock(&service.lock);
 798                 reg = list_entry(session->done.next, vpu_reg, session_link);
 799                 return_reg(reg, (u32 __user *)req.req);
 800                 mutex_unlock(&service.lock);
 801                 break;
 802         }
 803         default : {
 804                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
 805                 break;
 806         }
 807         }
 808
 809         return 0;
 810 }
 811
 812 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
 813 {
 814         int ret = -EINVAL, i = 0;
 815         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
 816         u32 enc_id = *tmp;
 817         enc_id = (enc_id >> 16) & 0xFFFF;
 818         pr_info("checking hw id %x\n", enc_id);
 819         p->hw_info = NULL;
 820         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
 821                 if (enc_id == vpu_hw_set[i].hw_id) {
 822                         p->hw_info = &vpu_hw_set[i];
 823                         ret = 0;
 824                         break;
 825                 }
 826         }
 827         iounmap((void *)tmp);
 828         return ret;
 829 }
 830
 831 static void vpu_service_release_io(void)
 832 {
 833         if (dec_dev.hwregs) {
 834                 iounmap((void *)dec_dev.hwregs);
 835                 dec_dev.hwregs = NULL;
 836         }
 837         if (dec_dev.iobaseaddr) {
 838                 release_mem_region(dec_dev.iobaseaddr, dec_dev.iosize);
 839                 dec_dev.iobaseaddr = 0;
 840                 dec_dev.iosize = 0;
 841         }
 842
 843         if (enc_dev.hwregs) {
 844                 iounmap((void *)enc_dev.hwregs);
 845                 enc_dev.hwregs = NULL;
 846         }
 847         if (enc_dev.iobaseaddr) {
 848                 release_mem_region(enc_dev.iobaseaddr, enc_dev.iosize);
 849                 enc_dev.iobaseaddr = 0;
 850                 enc_dev.iosize = 0;
 851         }
 852 }
 853
 854 static int vpu_service_reserve_io(void)
 855 {
 856         unsigned long iobaseaddr;
 857         unsigned long iosize;
 858
 859         iobaseaddr      = dec_dev.iobaseaddr;
 860         iosize          = dec_dev.iosize;
 861
 862         if (!request_mem_region(iobaseaddr, iosize, "vdpu_io")) {
 863                 pr_info("failed to reserve dec HW regs\n");
 864                 return -EBUSY;
 865         }
 866
 867         dec_dev.hwregs = (volatile u32 *)ioremap_nocache(iobaseaddr, iosize);
 868
 869         if (dec_dev.hwregs == NULL) {
 870                 pr_info("failed to ioremap dec HW regs\n");
 871                 goto err;
 872         }
 873
 874         iobaseaddr      = enc_dev.iobaseaddr;
 875         iosize          = enc_dev.iosize;
 876
 877         if (!request_mem_region(iobaseaddr, iosize, "vepu_io")) {
 878                 pr_info("failed to reserve enc HW regs\n");
 879                 goto err;
 880         }
 881
 882         enc_dev.hwregs = (volatile u32 *)ioremap_nocache(iobaseaddr, iosize);
 883
 884         if (enc_dev.hwregs == NULL) {
 885                 pr_info("failed to ioremap enc HW regs\n");
 886                 goto err;
 887         }
 888
 889         return 0;
 890
 891 err:
 892         return -EBUSY;
 893 }
 894
 895 static int vpu_service_open(struct inode *inode, struct file *filp)
 896 {
 897         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
 898         if (NULL == session) {
 899                 pr_err("error: unable to allocate memory for vpu_session.");
 900                 return -ENOMEM;
 901         }
 902
 903         session->type   = VPU_TYPE_BUTT;
 904         session->pid    = current->pid;
 905         INIT_LIST_HEAD(&session->waiting);
 906         INIT_LIST_HEAD(&session->running);
 907         INIT_LIST_HEAD(&session->done);
 908         INIT_LIST_HEAD(&session->list_session);
 909         init_waitqueue_head(&session->wait);
 910         atomic_set(&session->task_running, 0);
 911         mutex_lock(&service.lock);
 912         list_add_tail(&session->list_session, &service.session);
 913         filp->private_data = (void *)session;
 914         mutex_unlock(&service.lock);
 915
 916         pr_debug("dev opened\n");
 917         return nonseekable_open(inode, filp);
 918 }
 919
 920 static int vpu_service_release(struct inode *inode, struct file *filp)
 921 {
 922         int task_running;
 923         vpu_session *session = (vpu_session *)filp->private_data;
 924         if (NULL == session)
 925                 return -EINVAL;
 926
 927         task_running = atomic_read(&session->task_running);
 928         if (task_running) {
 929                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
 930                 msleep(50);
 931         }
 932         wake_up_interruptible_sync(&session->wait);
 933
 934         mutex_lock(&service.lock);
 935         /* remove this filp from the asynchronusly notified filp's */
 936         list_del_init(&session->list_session);
 937         vpu_service_session_clear(session);
 938         kfree(session);
 939         filp->private_data = NULL;
 940         mutex_unlock(&service.lock);
 941
 942         pr_debug("dev closed\n");
 943         return 0;
 944 }
 945
 946 static const struct file_operations vpu_service_fops = {
 947         .unlocked_ioctl = vpu_service_ioctl,
 948         .open           = vpu_service_open,
 949         .release        = vpu_service_release,
 950         //.fasync       = vpu_service_fasync,
 951 };
 952
 953 static struct miscdevice vpu_service_misc_device = {
 954         .minor          = MISC_DYNAMIC_MINOR,
 955         .name           = "vpu_service",
 956         .fops           = &vpu_service_fops,
 957 };
 958
 959 static struct platform_device vpu_service_device = {
 960         .name              = "vpu_service",
 961         .id                = -1,
 962 };
 963
 964 static struct platform_driver vpu_service_driver = {
 965         .driver    = {
 966                 .name  = "vpu_service",
 967                 .owner = THIS_MODULE,
 968         },
 969 };
 970
 971 static void get_hw_info(void)
 972 {
 973         VPUHwDecConfig_t *dec = &service.dec_config;
 974         VPUHwEncConfig_t *enc = &service.enc_config;
 975         u32 configReg   = dec_dev.hwregs[VPU_DEC_HWCFG0];
 976         u32 asicID      = dec_dev.hwregs[0];
 977
 978         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;
 979         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
 980         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
 981                 dec->jpegSupport = JPEG_PROGRESSIVE;
 982         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
 983         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
 984         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
 985         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
 986         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
 987         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
 988         dec->maxDecPicWidth = configReg & 0x07FFU;
 989
 990         /* 2nd Config register */
 991         configReg   = dec_dev.hwregs[VPU_DEC_HWCFG1];
 992         if (dec->refBufSupport) {
 993                 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
 994                         dec->refBufSupport |= 2;
 995                 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
 996                         dec->refBufSupport |= 4;
 997         }
 998         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
 999         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
1000         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
1001         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
1002
1003         /* JPEG xtensions */
1004         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
1005                 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
1006         } else {
1007                 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
1008         }
1009
1010         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {
1011                 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
1012         } else {
1013                 dec->rvSupport = RV_NOT_SUPPORTED;
1014         }
1015
1016         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
1017
1018         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {
1019                 dec->refBufSupport |= 8; /* enable HW support for offset */
1020         }
1021
1022         {
1023         VPUHwFuseStatus_t hwFuseSts;
1024         /* Decoder fuse configuration */
1025         u32 fuseReg = dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
1026
1027         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
1028         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
1029         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
1030         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
1031         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
1032         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
1033         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
1034         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
1035         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
1036         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
1037         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
1038         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
1039         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
1040         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
1041
1042         /* check max. decoder output width */
1043
1044         if (fuseReg & 0x8000U)
1045                 hwFuseSts.maxDecPicWidthFuse = 1920;
1046         else if (fuseReg & 0x4000U)
1047                 hwFuseSts.maxDecPicWidthFuse = 1280;
1048         else if (fuseReg & 0x2000U)
1049                 hwFuseSts.maxDecPicWidthFuse = 720;
1050         else if (fuseReg & 0x1000U)
1051                 hwFuseSts.maxDecPicWidthFuse = 352;
1052         else    /* remove warning */
1053                 hwFuseSts.maxDecPicWidthFuse = 352;
1054
1055         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
1056
1057         /* Pp configuration */
1058         configReg = dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
1059
1060         if ((configReg >> DWL_PP_E) & 0x01U) {
1061                 dec->ppSupport = 1;
1062                 dec->maxPpOutPicWidth = configReg & 0x07FFU;
1063                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
1064                 dec->ppConfig = configReg;
1065         } else {
1066                 dec->ppSupport = 0;
1067                 dec->maxPpOutPicWidth = 0;
1068                 dec->ppConfig = 0;
1069         }
1070
1071         /* check the HW versio */
1072         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
1073                 /* Pp configuration */
1074                 configReg = dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
1075
1076                 if ((configReg >> DWL_PP_E) & 0x01U) {
1077                         /* Pp fuse configuration */
1078                         u32 fuseRegPp = dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
1079
1080                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
1081                                 hwFuseSts.ppSupportFuse = 1;
1082                                 /* check max. pp output width */
1083                                 if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;
1084                                 else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;
1085                                 else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;
1086                                 else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;
1087                                 else                          hwFuseSts.maxPpOutPicWidthFuse = 352;
1088                                 hwFuseSts.ppConfigFuse = fuseRegPp;
1089                         } else {
1090                                 hwFuseSts.ppSupportFuse = 0;
1091                                 hwFuseSts.maxPpOutPicWidthFuse = 0;
1092                                 hwFuseSts.ppConfigFuse = 0;
1093                         }
1094                 } else {
1095                         hwFuseSts.ppSupportFuse = 0;
1096                         hwFuseSts.maxPpOutPicWidthFuse = 0;
1097                         hwFuseSts.ppConfigFuse = 0;
1098                 }
1099
1100                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
1101                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
1102                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
1103                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
1104                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
1105                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
1106                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
1107                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
1108                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
1109                         dec->jpegSupport = JPEG_BASELINE;
1110                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
1111                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
1112                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
1113                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
1114                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
1115                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
1116
1117                 /* check the pp config vs fuse status */
1118                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
1119                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
1120                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
1121                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
1122                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
1123
1124                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
1125                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
1126                 }
1127                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
1128                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
1129                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;
1130                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;
1131                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;
1132         }
1133         }
1134         configReg = enc_dev.hwregs[63];
1135         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
1136         enc->h264Enabled = (configReg >> 27) & 1;
1137         enc->mpeg4Enabled = (configReg >> 26) & 1;
1138         enc->jpegEnabled = (configReg >> 25) & 1;
1139         enc->vsEnabled = (configReg >> 24) & 1;
1140         enc->rgbEnabled = (configReg >> 28) & 1;
1141         //enc->busType = (configReg >> 20) & 15;
1142         //enc->synthesisLanguage = (configReg >> 16) & 15;
1143         //enc->busWidth = (configReg >> 12) & 15;
1144         enc->reg_size = service.reg_size;
1145         enc->reserv[0] = enc->reserv[1] = 0;
1146
1147         service.auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();
1148         if (service.auto_freq) {
1149                 printk("vpu_service set to auto frequency mode\n");
1150         }
1151 }
1152
1153 static irqreturn_t vdpu_irq(int irq, void *dev_id)
1154 {
1155         vpu_device *dev = (vpu_device *) dev_id;
1156         u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
1157
1158         pr_debug("vdpu_irq\n");
1159
1160         if (irq_status & DEC_INTERRUPT_BIT) {
1161                 pr_debug("vdpu_isr dec %x\n", irq_status);
1162                 if ((irq_status & 0x40001) == 0x40001)
1163                 {
1164                         do {
1165                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
1166                         } while ((irq_status & 0x40001) == 0x40001);
1167                 }
1168                 /* clear dec IRQ */
1169                 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
1170                 atomic_add(1, &dev->irq_count_codec);
1171         }
1172
1173         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
1174         if (irq_status & PP_INTERRUPT_BIT) {
1175                 pr_debug("vdpu_isr pp  %x\n", irq_status);
1176                 /* clear pp IRQ */
1177                 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
1178                 atomic_add(1, &dev->irq_count_pp);
1179         }
1180
1181         return IRQ_WAKE_THREAD;
1182 }
1183
1184 static irqreturn_t vdpu_isr(int irq, void *dev_id)
1185 {
1186         vpu_device *dev = (vpu_device *) dev_id;
1187
1188         mutex_lock(&service.lock);
1189         if (atomic_read(&dev->irq_count_codec)) {
1190                 atomic_sub(1, &dev->irq_count_codec);
1191                 if (NULL == service.reg_codec) {
1192                         pr_err("error: dec isr with no task waiting\n");
1193                 } else {
1194                         reg_from_run_to_done(service.reg_codec);
1195                 }
1196         }
1197
1198         if (atomic_read(&dev->irq_count_pp)) {
1199                 atomic_sub(1, &dev->irq_count_pp);
1200                 if (NULL == service.reg_pproc) {
1201                         pr_err("error: pp isr with no task waiting\n");
1202                 } else {
1203                         reg_from_run_to_done(service.reg_pproc);
1204                 }
1205         }
1206         try_set_reg();
1207         mutex_unlock(&service.lock);
1208         return IRQ_HANDLED;
1209 }
1210
1211 static irqreturn_t vepu_irq(int irq, void *dev_id)
1212 {
1213         struct vpu_device *dev = (struct vpu_device *) dev_id;
1214         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
1215
1216         pr_debug("vepu_irq irq status %x\n", irq_status);
1217
1218         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
1219                 /* clear enc IRQ */
1220                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
1221                 atomic_add(1, &dev->irq_count_codec);
1222         }
1223
1224         return IRQ_WAKE_THREAD;
1225 }
1226
1227 static irqreturn_t vepu_isr(int irq, void *dev_id)
1228 {
1229         struct vpu_device *dev = (struct vpu_device *) dev_id;
1230
1231         mutex_lock(&service.lock);
1232         if (atomic_read(&dev->irq_count_codec)) {
1233                 atomic_sub(1, &dev->irq_count_codec);
1234                 if (NULL == service.reg_codec) {
1235                         pr_err("error: enc isr with no task waiting\n");
1236                 } else {
1237                         reg_from_run_to_done(service.reg_codec);
1238                 }
1239         }
1240         try_set_reg();
1241         mutex_unlock(&service.lock);
1242         return IRQ_HANDLED;
1243 }
1244
1245 static int __init vpu_service_proc_init(void);
1246 static int __init vpu_service_init(void)
1247 {
1248         int ret;
1249
1250         pr_debug("baseaddr = 0x%08x vdpu irq = %d vepu irq = %d\n", VCODEC_PHYS, IRQ_VDPU, IRQ_VEPU);
1251
1252         wake_lock_init(&service.wake_lock, WAKE_LOCK_SUSPEND, "vpu");
1253         INIT_LIST_HEAD(&service.waiting);
1254         INIT_LIST_HEAD(&service.running);
1255         INIT_LIST_HEAD(&service.done);
1256         INIT_LIST_HEAD(&service.session);
1257         mutex_init(&service.lock);
1258         service.reg_codec       = NULL;
1259         service.reg_pproc       = NULL;
1260         atomic_set(&service.total_running, 0);
1261         service.enabled         = false;
1262
1263         vpu_get_clk();
1264
1265         INIT_DELAYED_WORK(&service.power_off_work, vpu_power_off_work);
1266
1267         vpu_service_power_on();
1268         ret = vpu_service_check_hw(&service, VCODEC_PHYS);
1269         if (ret < 0) {
1270                 pr_err("error: hw info check faild\n");
1271                 goto err_hw_id_check;
1272         }
1273
1274         atomic_set(&dec_dev.irq_count_codec, 0);
1275         atomic_set(&dec_dev.irq_count_pp, 0);
1276         dec_dev.iobaseaddr      = service.hw_info->hw_addr + service.hw_info->dec_offset;
1277         dec_dev.iosize          = service.hw_info->dec_io_size;
1278         atomic_set(&enc_dev.irq_count_codec, 0);
1279         atomic_set(&enc_dev.irq_count_pp, 0);
1280         enc_dev.iobaseaddr      = service.hw_info->hw_addr + service.hw_info->enc_offset;
1281         enc_dev.iosize          = service.hw_info->enc_io_size;;
1282         service.reg_size        = max(dec_dev.iosize, enc_dev.iosize);
1283
1284         ret = vpu_service_reserve_io();
1285         if (ret < 0) {
1286                 pr_err("error: reserve io failed\n");
1287                 goto err_reserve_io;
1288         }
1289
1290         /* get the IRQ line */
1291         ret = request_threaded_irq(IRQ_VDPU, vdpu_irq, vdpu_isr, IRQF_SHARED, "vdpu", (void *)&dec_dev);
1292         if (ret) {
1293                 pr_err("error: can't request vdpu irq %d\n", IRQ_VDPU);
1294                 goto err_req_vdpu_irq;
1295         }
1296
1297         ret = request_threaded_irq(IRQ_VEPU, vepu_irq, vepu_isr, IRQF_SHARED, "vepu", (void *)&enc_dev);
1298         if (ret) {
1299                 pr_err("error: can't request vepu irq %d\n", IRQ_VEPU);
1300                 goto err_req_vepu_irq;
1301         }
1302
1303         ret = misc_register(&vpu_service_misc_device);
1304         if (ret) {
1305                 pr_err("error: misc_register failed\n");
1306                 goto err_register;
1307         }
1308
1309         platform_device_register(&vpu_service_device);
1310         platform_driver_probe(&vpu_service_driver, NULL);
1311         get_hw_info();
1312         vpu_service_power_off();
1313         pr_info("init success\n");
1314
1315         vpu_service_proc_init();
1316         return 0;
1317
1318 err_register:
1319         free_irq(IRQ_VEPU, (void *)&enc_dev);
1320 err_req_vepu_irq:
1321         free_irq(IRQ_VDPU, (void *)&dec_dev);
1322 err_req_vdpu_irq:
1323         pr_info("init failed\n");
1324 err_reserve_io:
1325         vpu_service_release_io();
1326 err_hw_id_check:
1327         vpu_service_power_off();
1328         vpu_put_clk();
1329         wake_lock_destroy(&service.wake_lock);
1330         pr_info("init failed\n");
1331         return ret;
1332 }
1333
1334 static void __exit vpu_service_proc_release(void);
1335 static void __exit vpu_service_exit(void)
1336 {
1337         vpu_service_proc_release();
1338         vpu_service_power_off();
1339         platform_device_unregister(&vpu_service_device);
1340         platform_driver_unregister(&vpu_service_driver);
1341         misc_deregister(&vpu_service_misc_device);
1342         free_irq(IRQ_VEPU, (void *)&enc_dev);
1343         free_irq(IRQ_VDPU, (void *)&dec_dev);
1344         vpu_service_release_io();
1345         vpu_put_clk();
1346         wake_lock_destroy(&service.wake_lock);
1347 }
1348
1349 module_init(vpu_service_init);
1350 module_exit(vpu_service_exit);
1351
1352 #ifdef CONFIG_PROC_FS
1353 #include <linux/proc_fs.h>
1354 #include <linux/seq_file.h>
1355
1356 static int proc_vpu_service_show(struct seq_file *s, void *v)
1357 {
1358         unsigned int i, n;
1359         vpu_reg *reg, *reg_tmp;
1360         vpu_session *session, *session_tmp;
1361
1362         mutex_lock(&service.lock);
1363         vpu_service_power_on();
1364         seq_printf(s, "\nENC Registers:\n");
1365         n = enc_dev.iosize >> 2;
1366         for (i = 0; i < n; i++) {
1367                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(enc_dev.hwregs + i));
1368         }
1369         seq_printf(s, "\nDEC Registers:\n");
1370         n = dec_dev.iosize >> 2;
1371         for (i = 0; i < n; i++) {
1372                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(dec_dev.hwregs + i));
1373         }
1374
1375         seq_printf(s, "\nvpu service status:\n");
1376         list_for_each_entry_safe(session, session_tmp, &service.session, list_session) {
1377                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
1378                 //seq_printf(s, "waiting reg set %d\n");
1379                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
1380                         seq_printf(s, "waiting register set\n");
1381                 }
1382                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
1383                         seq_printf(s, "running register set\n");
1384                 }
1385                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
1386                         seq_printf(s, "done    register set\n");
1387                 }
1388         }
1389         mutex_unlock(&service.lock);
1390
1391         return 0;
1392 }
1393
1394 static int proc_vpu_service_open(struct inode *inode, struct file *file)
1395 {
1396         return single_open(file, proc_vpu_service_show, NULL);
1397 }
1398
1399 static const struct file_operations proc_vpu_service_fops = {
1400         .open           = proc_vpu_service_open,
1401         .read           = seq_read,
1402         .llseek         = seq_lseek,
1403         .release        = single_release,
1404 };
1405
1406 static int __init vpu_service_proc_init(void)
1407 {
1408         proc_create("vpu_service", 0, NULL, &proc_vpu_service_fops);
1409         return 0;
1410
1411 }
1412 static void __exit vpu_service_proc_release(void)
1413 {
1414         remove_proc_entry("vpu_service", NULL);
1415 }
1416 #endif /* CONFIG_PROC_FS */
1417