2 * linux/arch/arm/plat-versatile/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/jiffies.h>
16 #include <linux/smp.h>
17 #include <linux/irqchip/arm-gic.h>
19 #include <asm/cacheflush.h>
20 #include <asm/smp_plat.h>
23 * Write pen_release in a way that is guaranteed to be visible to all
24 * observers, irrespective of whether they're taking part in coherency
25 * or not. This is necessary for the hotplug code to work reliably.
27 static void __cpuinit write_pen_release(int val)
31 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
32 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
35 static DEFINE_SPINLOCK(boot_lock);
37 void __cpuinit versatile_secondary_init(unsigned int cpu)
40 * if any interrupts are already enabled for the primary
41 * core (e.g. timer irq), then they will not have been enabled
44 gic_secondary_init(0);
47 * let the primary processor know we're out of the
48 * pen, then head off into the C entry point
50 write_pen_release(-1);
53 * Synchronise with the boot thread.
55 spin_lock(&boot_lock);
56 spin_unlock(&boot_lock);
59 int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
61 unsigned long timeout;
64 * Set synchronisation state between this boot processor
65 * and the secondary one
67 spin_lock(&boot_lock);
70 * This is really belt and braces; we hold unintended secondary
71 * CPUs in the holding pen until we're ready for them. However,
72 * since we haven't sent them a soft interrupt, they shouldn't
75 write_pen_release(cpu_logical_map(cpu));
78 * Send the secondary CPU a soft interrupt, thereby causing
79 * the boot monitor to read the system wide flags register,
80 * and branch to the address found there.
82 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
84 timeout = jiffies + (1 * HZ);
85 while (time_before(jiffies, timeout)) {
87 if (pen_release == -1)
94 * now the secondary core is starting up let it run its
95 * calibrations, then wait for it to finish
97 spin_unlock(&boot_lock);
99 return pen_release != -1 ? -ENOSYS : 0;