3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
23 select BUILDTIME_EXTABLE_SORT
24 select CLONE_BACKWARDS
26 select CPU_PM if (SUSPEND || CPU_IDLE)
27 select DCACHE_WORD_ACCESS
29 select GENERIC_ALLOCATOR
30 select GENERIC_CLOCKEVENTS
31 select GENERIC_CLOCKEVENTS_BROADCAST
32 select GENERIC_CPU_AUTOPROBE
33 select GENERIC_EARLY_IOREMAP
34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
36 select GENERIC_IRQ_SHOW_LEVEL
37 select GENERIC_PCI_IOMAP
38 select GENERIC_SCHED_CLOCK
39 select GENERIC_SMP_IDLE_THREAD
40 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
42 select GENERIC_TIME_VSYSCALL
43 select HANDLE_DOMAIN_IRQ
44 select HARDIRQS_SW_RESEND
45 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
46 select HAVE_ARCH_AUDITSYSCALL
47 select HAVE_ARCH_BITREVERSE
48 select HAVE_ARCH_JUMP_LABEL
50 select HAVE_ARCH_SECCOMP_FILTER
51 select HAVE_ARCH_TRACEHOOK
53 select HAVE_C_RECORDMCOUNT
54 select HAVE_CC_STACKPROTECTOR
55 select HAVE_CMPXCHG_DOUBLE
56 select HAVE_DEBUG_BUGVERBOSE
57 select HAVE_DEBUG_KMEMLEAK
58 select HAVE_DMA_API_DEBUG
60 select HAVE_DMA_CONTIGUOUS
61 select HAVE_DYNAMIC_FTRACE
62 select HAVE_EFFICIENT_UNALIGNED_ACCESS
63 select HAVE_FTRACE_MCOUNT_RECORD
64 select HAVE_FUNCTION_TRACER
65 select HAVE_FUNCTION_GRAPH_TRACER
66 select HAVE_GENERIC_DMA_COHERENT
67 select HAVE_HW_BREAKPOINT if PERF_EVENTS
69 select HAVE_PATA_PLATFORM
70 select HAVE_PERF_EVENTS
72 select HAVE_PERF_USER_STACK_DUMP
73 select HAVE_RCU_TABLE_FREE
74 select HAVE_SYSCALL_TRACEPOINTS
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_RELA
80 select OF_EARLY_FLATTREE
81 select OF_RESERVED_MEM
82 select PERF_USE_VMALLOC
87 select SYSCTL_EXCEPTION_TRACE
88 select HAVE_CONTEXT_TRACKING
90 ARM 64-bit (AArch64) Linux support.
95 config ARCH_PHYS_ADDR_T_64BIT
104 config STACKTRACE_SUPPORT
107 config LOCKDEP_SUPPORT
110 config TRACE_IRQFLAGS_SUPPORT
113 config RWSEM_XCHGADD_ALGORITHM
120 config GENERIC_BUG_RELATIVE_POINTERS
122 depends on GENERIC_BUG
124 config GENERIC_HWEIGHT
130 config GENERIC_CALIBRATE_DELAY
136 config HAVE_GENERIC_RCU_GUP
139 config ARCH_DMA_ADDR_T_64BIT
142 config NEED_DMA_MAP_STATE
145 config NEED_SG_DMA_LENGTH
157 config KERNEL_MODE_NEON
160 config FIX_EARLYCON_MEM
163 config PGTABLE_LEVELS
165 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
166 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
167 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
168 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
170 source "init/Kconfig"
172 source "kernel/Kconfig.freezer"
174 menu "Platform selection"
179 This enables support for Samsung Exynos SoC family
182 bool "ARMv8 based Samsung Exynos7"
184 select COMMON_CLK_SAMSUNG
185 select HAVE_S3C2410_WATCHDOG if WATCHDOG
186 select HAVE_S3C_RTC if RTC_CLASS
188 select PINCTRL_EXYNOS
191 This enables support for Samsung Exynos7 SoC family
193 config ARCH_FSL_LS2085A
194 bool "Freescale LS2085A SOC"
196 This enables support for Freescale LS2085A SOC.
199 bool "Hisilicon SoC Family"
201 This enables support for Hisilicon ARMv8 SoC family
204 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
208 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
211 bool "Qualcomm Platforms"
214 This enables support for the ARMv8 based Qualcomm chipsets.
217 bool "AMD Seattle SoC Family"
219 This enables support for AMD Seattle SOC Family
222 bool "NVIDIA Tegra SoC Family"
223 select ARCH_HAS_RESET_CONTROLLER
224 select ARCH_REQUIRE_GPIOLIB
228 select GENERIC_CLOCKEVENTS
231 select RESET_CONTROLLER
233 This enables support for the NVIDIA Tegra SoC family.
235 config ARCH_TEGRA_132_SOC
236 bool "NVIDIA Tegra132 SoC"
237 depends on ARCH_TEGRA
238 select PINCTRL_TEGRA124
239 select USB_ULPI if USB_PHY
240 select USB_ULPI_VIEWPORT if USB_PHY
242 Enable support for NVIDIA Tegra132 SoC, based on the Denver
243 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
244 but contains an NVIDIA Denver CPU complex in place of
245 Tegra124's "4+1" Cortex-A15 CPU complex.
248 bool "Spreadtrum SoC platform"
250 Support for Spreadtrum ARM based SoCs
253 bool "Cavium Inc. Thunder SoC Family"
255 This enables support for Cavium's Thunder Family of SoCs.
258 bool "ARMv8 software model (Versatile Express)"
259 select ARCH_REQUIRE_GPIOLIB
260 select COMMON_CLK_VERSATILE
261 select POWER_RESET_VEXPRESS
262 select VEXPRESS_CONFIG
264 This enables support for the ARMv8 software model (Versatile
268 bool "AppliedMicro X-Gene SOC Family"
270 This enables support for AppliedMicro X-Gene SOC Family
273 bool "Xilinx ZynqMP Family"
275 This enables support for Xilinx ZynqMP Family
284 This feature enables support for PCI bus system. If you say Y
285 here, the kernel will include drivers and infrastructure code
286 to support PCI bus devices.
291 config PCI_DOMAINS_GENERIC
297 source "drivers/pci/Kconfig"
298 source "drivers/pci/pcie/Kconfig"
299 source "drivers/pci/hotplug/Kconfig"
303 menu "Kernel Features"
305 menu "ARM errata workarounds via the alternatives framework"
307 config ARM64_ERRATUM_826319
308 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
311 This option adds an alternative code sequence to work around ARM
312 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
313 AXI master interface and an L2 cache.
315 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
316 and is unable to accept a certain write via this interface, it will
317 not progress on read data presented on the read data channel and the
320 The workaround promotes data cache clean instructions to
321 data cache clean-and-invalidate.
322 Please note that this does not necessarily enable the workaround,
323 as it depends on the alternative framework, which will only patch
324 the kernel if an affected CPU is detected.
328 config ARM64_ERRATUM_827319
329 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
332 This option adds an alternative code sequence to work around ARM
333 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
334 master interface and an L2 cache.
336 Under certain conditions this erratum can cause a clean line eviction
337 to occur at the same time as another transaction to the same address
338 on the AMBA 5 CHI interface, which can cause data corruption if the
339 interconnect reorders the two transactions.
341 The workaround promotes data cache clean instructions to
342 data cache clean-and-invalidate.
343 Please note that this does not necessarily enable the workaround,
344 as it depends on the alternative framework, which will only patch
345 the kernel if an affected CPU is detected.
349 config ARM64_ERRATUM_824069
350 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
353 This option adds an alternative code sequence to work around ARM
354 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
355 to a coherent interconnect.
357 If a Cortex-A53 processor is executing a store or prefetch for
358 write instruction at the same time as a processor in another
359 cluster is executing a cache maintenance operation to the same
360 address, then this erratum might cause a clean cache line to be
361 incorrectly marked as dirty.
363 The workaround promotes data cache clean instructions to
364 data cache clean-and-invalidate.
365 Please note that this option does not necessarily enable the
366 workaround, as it depends on the alternative framework, which will
367 only patch the kernel if an affected CPU is detected.
371 config ARM64_ERRATUM_819472
372 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
375 This option adds an alternative code sequence to work around ARM
376 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
377 present when it is connected to a coherent interconnect.
379 If the processor is executing a load and store exclusive sequence at
380 the same time as a processor in another cluster is executing a cache
381 maintenance operation to the same address, then this erratum might
382 cause data corruption.
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_832075
393 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
396 This option adds an alternative code sequence to work around ARM
397 erratum 832075 on Cortex-A57 parts up to r1p2.
399 Affected Cortex-A57 parts might deadlock when exclusive load/store
400 instructions to Write-Back memory are mixed with Device loads.
402 The workaround is to promote device loads to use Load-Acquire
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_845719
411 bool "Cortex-A53: 845719: a load might read incorrect data"
415 This option adds an alternative code sequence to work around ARM
416 erratum 845719 on Cortex-A53 parts up to r0p4.
418 When running a compat (AArch32) userspace on an affected Cortex-A53
419 part, a load at EL0 from a virtual address that matches the bottom 32
420 bits of the virtual address used by a recent load at (AArch64) EL1
421 might return incorrect data.
423 The workaround is to write the contextidr_el1 register on exception
424 return to a 32-bit task.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
436 default ARM64_4K_PAGES
438 Page size (translation granule) configuration.
440 config ARM64_4K_PAGES
443 This feature enables 4KB pages support.
445 config ARM64_64K_PAGES
448 This feature enables 64KB pages support (4KB by default)
449 allowing only two levels of page tables and faster TLB
450 look-up. AArch32 emulation is not available when this feature
456 prompt "Virtual address space size"
457 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
458 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
460 Allows choosing one of multiple possible virtual address
461 space sizes. The level of translation table is determined by
462 a combination of page size and virtual address space size.
464 config ARM64_VA_BITS_39
466 depends on ARM64_4K_PAGES
468 config ARM64_VA_BITS_42
470 depends on ARM64_64K_PAGES
472 config ARM64_VA_BITS_48
479 default 39 if ARM64_VA_BITS_39
480 default 42 if ARM64_VA_BITS_42
481 default 48 if ARM64_VA_BITS_48
483 config ARM64_HW_AFDBM
484 bool "Support for hardware updates of the Access and Dirty page flags"
487 The ARMv8.1 architecture extensions introduce support for
488 hardware updates of the access and dirty information in page
489 table entries. When enabled in TCR_EL1 (HA and HD bits) on
490 capable processors, accesses to pages with PTE_AF cleared will
491 set this bit instead of raising an access flag fault.
492 Similarly, writes to read-only pages with the DBM bit set will
493 clear the read-only bit (AP[2]) instead of raising a
496 Kernels built with this configuration option enabled continue
497 to work on pre-ARMv8.1 hardware and the performance impact is
498 minimal. If unsure, say Y.
500 config CPU_BIG_ENDIAN
501 bool "Build big-endian kernel"
503 Say Y if you plan on running a kernel in big-endian mode.
506 bool "Multi-core scheduler support"
508 Multi-core scheduler support improves the CPU scheduler's decision
509 making when dealing with multi-core CPU chips at a cost of slightly
510 increased overhead in some places. If unsure say N here.
513 bool "SMT scheduler support"
515 Improves the CPU scheduler's decision making when dealing with
516 MultiThreading at a cost of slightly increased overhead in some
517 places. If unsure say N here.
520 int "Maximum number of CPUs (2-4096)"
522 # These have to remain sorted largest to smallest
526 bool "Support for hot-pluggable CPUs"
528 Say Y here to experiment with turning CPUs off and on. CPUs
529 can be controlled through /sys/devices/system/cpu.
531 source kernel/Kconfig.preempt
537 config ARCH_HAS_HOLES_MEMORYMODEL
538 def_bool y if SPARSEMEM
540 config ARCH_SPARSEMEM_ENABLE
542 select SPARSEMEM_VMEMMAP_ENABLE
544 config ARCH_SPARSEMEM_DEFAULT
545 def_bool ARCH_SPARSEMEM_ENABLE
547 config ARCH_SELECT_MEMORY_MODEL
548 def_bool ARCH_SPARSEMEM_ENABLE
550 config HAVE_ARCH_PFN_VALID
551 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
553 config HW_PERF_EVENTS
554 bool "Enable hardware performance counter support for perf events"
555 depends on PERF_EVENTS
558 Enable hardware performance counter support for perf events. If
559 disabled, perf events will use software events only.
561 config SYS_SUPPORTS_HUGETLBFS
564 config ARCH_WANT_GENERAL_HUGETLB
567 config ARCH_WANT_HUGE_PMD_SHARE
568 def_bool y if !ARM64_64K_PAGES
570 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
573 config ARCH_HAS_CACHE_LINE_SIZE
579 bool "Enable seccomp to safely compute untrusted bytecode"
581 This kernel feature is useful for number crunching applications
582 that may need to compute untrusted bytecode during their
583 execution. By using pipes or other transports made available to
584 the process as file descriptors supporting the read/write
585 syscalls, it's possible to isolate those applications in
586 their own address space using seccomp. Once seccomp is
587 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
588 and the task is only allowed to execute a few safe syscalls
589 defined by each seccomp mode.
596 bool "Xen guest support on ARM64"
597 depends on ARM64 && OF
600 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
602 config FORCE_MAX_ZONEORDER
604 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
608 bool "Enable support for Privileged Access Never (PAN)"
611 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
612 prevents the kernel or hypervisor from accessing user-space (EL0)
615 Choosing this option will cause any unprotected (not using
616 copy_to_user et al) memory access to fail with a permission fault.
618 The feature is detected at runtime, and will remain as a 'nop'
619 instruction if the cpu does not implement the feature.
621 menuconfig ARMV8_DEPRECATED
622 bool "Emulate deprecated/obsolete ARMv8 instructions"
625 Legacy software support may require certain instructions
626 that have been deprecated or obsoleted in the architecture.
628 Enable this config to enable selective emulation of these
636 bool "Emulate SWP/SWPB instructions"
638 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
639 they are always undefined. Say Y here to enable software
640 emulation of these instructions for userspace using LDXR/STXR.
642 In some older versions of glibc [<=2.8] SWP is used during futex
643 trylock() operations with the assumption that the code will not
644 be preempted. This invalid assumption may be more likely to fail
645 with SWP emulation enabled, leading to deadlock of the user
648 NOTE: when accessing uncached shared regions, LDXR/STXR rely
649 on an external transaction monitoring block called a global
650 monitor to maintain update atomicity. If your system does not
651 implement a global monitor, this option can cause programs that
652 perform SWP operations to uncached memory to deadlock.
656 config CP15_BARRIER_EMULATION
657 bool "Emulate CP15 Barrier instructions"
659 The CP15 barrier instructions - CP15ISB, CP15DSB, and
660 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
661 strongly recommended to use the ISB, DSB, and DMB
662 instructions instead.
664 Say Y here to enable software emulation of these
665 instructions for AArch32 userspace code. When this option is
666 enabled, CP15 barrier usage is traced which can help
667 identify software that needs updating.
671 config SETEND_EMULATION
672 bool "Emulate SETEND instruction"
674 The SETEND instruction alters the data-endianness of the
675 AArch32 EL0, and is deprecated in ARMv8.
677 Say Y here to enable software emulation of the instruction
678 for AArch32 userspace code.
680 Note: All the cpus on the system must have mixed endian support at EL0
681 for this feature to be enabled. If a new CPU - which doesn't support mixed
682 endian - is hotplugged in after this feature has been enabled, there could
683 be unexpected results in the applications.
693 string "Default kernel command string"
696 Provide a set of default command-line options at build time by
697 entering them here. As a minimum, you should specify the the
698 root device (e.g. root=/dev/nfs).
701 bool "Always use the default kernel command string"
703 Always use the default kernel command string, even if the boot
704 loader passes other arguments to the kernel.
705 This is useful if you cannot or don't want to change the
706 command-line options your boot loader passes to the kernel.
712 bool "UEFI runtime support"
713 depends on OF && !CPU_BIG_ENDIAN
716 select EFI_PARAMS_FROM_FDT
717 select EFI_RUNTIME_WRAPPERS
722 This option provides support for runtime services provided
723 by UEFI firmware (such as non-volatile variables, realtime
724 clock, and platform reset). A UEFI stub is also provided to
725 allow the kernel to be booted as an EFI application. This
726 is only useful on systems that have UEFI firmware.
729 bool "Enable support for SMBIOS (DMI) tables"
733 This enables SMBIOS/DMI feature for systems.
735 This option is only useful on systems that have UEFI firmware.
736 However, even with this option, the resultant kernel should
737 continue to boot on existing non-UEFI platforms.
741 menu "Userspace binary formats"
743 source "fs/Kconfig.binfmt"
746 bool "Kernel support for 32-bit EL0"
747 depends on !ARM64_64K_PAGES || EXPERT
748 select COMPAT_BINFMT_ELF
750 select OLD_SIGSUSPEND3
751 select COMPAT_OLD_SIGACTION
753 This option enables support for a 32-bit EL0 running under a 64-bit
754 kernel at EL1. AArch32-specific components such as system calls,
755 the user helper functions, VFP support and the ptrace interface are
756 handled appropriately by the kernel.
758 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
759 will only be able to execute AArch32 binaries that were compiled with
760 64k aligned segments.
762 If you want to execute 32-bit userspace applications, say Y.
764 config SYSVIPC_COMPAT
766 depends on COMPAT && SYSVIPC
770 menu "Power management options"
772 source "kernel/power/Kconfig"
774 config ARCH_SUSPEND_POSSIBLE
779 menu "CPU Power Management"
781 source "drivers/cpuidle/Kconfig"
783 source "drivers/cpufreq/Kconfig"
789 source "drivers/Kconfig"
791 source "drivers/firmware/Kconfig"
793 source "drivers/acpi/Kconfig"
797 source "arch/arm64/kvm/Kconfig"
799 source "arch/arm64/Kconfig.debug"
801 source "security/Kconfig"
803 source "crypto/Kconfig"
805 source "arch/arm64/crypto/Kconfig"