3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
31 select GENERIC_ALLOCATOR
32 select GENERIC_CLOCKEVENTS
33 select GENERIC_CLOCKEVENTS_BROADCAST
34 select GENERIC_CPU_AUTOPROBE
35 select GENERIC_EARLY_IOREMAP
36 select GENERIC_IDLE_POLL_SETUP
37 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
39 select GENERIC_IRQ_SHOW_LEVEL
40 select GENERIC_PCI_IOMAP
41 select GENERIC_SCHED_CLOCK
42 select GENERIC_SMP_IDLE_THREAD
43 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
45 select GENERIC_TIME_VSYSCALL
46 select HANDLE_DOMAIN_IRQ
47 select HARDIRQS_SW_RESEND
48 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
49 select HAVE_ARCH_AUDITSYSCALL
50 select HAVE_ARCH_BITREVERSE
51 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
54 select HAVE_ARCH_MMAP_RND_BITS
55 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
56 select HAVE_ARCH_SECCOMP_FILTER
57 select HAVE_ARCH_TRACEHOOK
59 select HAVE_C_RECORDMCOUNT
60 select HAVE_CC_STACKPROTECTOR
61 select HAVE_CMPXCHG_DOUBLE
62 select HAVE_CMPXCHG_LOCAL
63 select HAVE_DEBUG_BUGVERBOSE
64 select HAVE_DEBUG_KMEMLEAK
65 select HAVE_DMA_API_DEBUG
67 select HAVE_DMA_CONTIGUOUS
68 select HAVE_DYNAMIC_FTRACE
69 select HAVE_EFFICIENT_UNALIGNED_ACCESS
70 select HAVE_FTRACE_MCOUNT_RECORD
71 select HAVE_FUNCTION_TRACER
72 select HAVE_FUNCTION_GRAPH_TRACER
73 select HAVE_GENERIC_DMA_COHERENT
74 select HAVE_HW_BREAKPOINT if PERF_EVENTS
76 select HAVE_PATA_PLATFORM
77 select HAVE_PERF_EVENTS
79 select HAVE_PERF_USER_STACK_DUMP
80 select HAVE_RCU_TABLE_FREE
81 select HAVE_SYSCALL_TRACEPOINTS
82 select IOMMU_DMA if IOMMU_SUPPORT
84 select IRQ_FORCED_THREADING
85 select MODULES_USE_ELF_RELA
88 select OF_EARLY_FLATTREE
89 select OF_RESERVED_MEM
90 select PERF_USE_VMALLOC
95 select SYSCTL_EXCEPTION_TRACE
96 select HAVE_CONTEXT_TRACKING
98 ARM 64-bit (AArch64) Linux support.
103 config ARCH_PHYS_ADDR_T_64BIT
109 config ARCH_MMAP_RND_BITS_MIN
110 default 14 if ARM64_64K_PAGES
111 default 16 if ARM64_16K_PAGES
114 # max bits determined by the following formula:
115 # VA_BITS - PAGE_SHIFT - 3
116 config ARCH_MMAP_RND_BITS_MAX
117 default 19 if ARM64_VA_BITS=36
118 default 24 if ARM64_VA_BITS=39
119 default 27 if ARM64_VA_BITS=42
120 default 30 if ARM64_VA_BITS=47
121 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
122 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
123 default 33 if ARM64_VA_BITS=48
124 default 14 if ARM64_64K_PAGES
125 default 16 if ARM64_16K_PAGES
128 config ARCH_MMAP_RND_COMPAT_BITS_MIN
129 default 7 if ARM64_64K_PAGES
130 default 9 if ARM64_16K_PAGES
133 config ARCH_MMAP_RND_COMPAT_BITS_MAX
139 config ILLEGAL_POINTER_VALUE
141 default 0xdead000000000000
143 config STACKTRACE_SUPPORT
146 config ILLEGAL_POINTER_VALUE
148 default 0xdead000000000000
150 config LOCKDEP_SUPPORT
153 config TRACE_IRQFLAGS_SUPPORT
156 config RWSEM_XCHGADD_ALGORITHM
163 config GENERIC_BUG_RELATIVE_POINTERS
165 depends on GENERIC_BUG
167 config GENERIC_HWEIGHT
173 config GENERIC_CALIBRATE_DELAY
179 config HAVE_GENERIC_RCU_GUP
182 config ARCH_DMA_ADDR_T_64BIT
185 config NEED_DMA_MAP_STATE
188 config NEED_SG_DMA_LENGTH
200 config KERNEL_MODE_NEON
203 config FIX_EARLYCON_MEM
206 config PGTABLE_LEVELS
208 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
209 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
210 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
211 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
212 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
213 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
215 source "init/Kconfig"
217 source "kernel/Kconfig.freezer"
219 source "arch/arm64/Kconfig.platforms"
226 This feature enables support for PCI bus system. If you say Y
227 here, the kernel will include drivers and infrastructure code
228 to support PCI bus devices.
233 config PCI_DOMAINS_GENERIC
239 source "drivers/pci/Kconfig"
240 source "drivers/pci/pcie/Kconfig"
241 source "drivers/pci/hotplug/Kconfig"
245 menu "Kernel Features"
247 menu "ARM errata workarounds via the alternatives framework"
249 config ARM64_ERRATUM_826319
250 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
253 This option adds an alternative code sequence to work around ARM
254 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
255 AXI master interface and an L2 cache.
257 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
258 and is unable to accept a certain write via this interface, it will
259 not progress on read data presented on the read data channel and the
262 The workaround promotes data cache clean instructions to
263 data cache clean-and-invalidate.
264 Please note that this does not necessarily enable the workaround,
265 as it depends on the alternative framework, which will only patch
266 the kernel if an affected CPU is detected.
270 config ARM64_ERRATUM_827319
271 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
274 This option adds an alternative code sequence to work around ARM
275 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
276 master interface and an L2 cache.
278 Under certain conditions this erratum can cause a clean line eviction
279 to occur at the same time as another transaction to the same address
280 on the AMBA 5 CHI interface, which can cause data corruption if the
281 interconnect reorders the two transactions.
283 The workaround promotes data cache clean instructions to
284 data cache clean-and-invalidate.
285 Please note that this does not necessarily enable the workaround,
286 as it depends on the alternative framework, which will only patch
287 the kernel if an affected CPU is detected.
291 config ARM64_ERRATUM_824069
292 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
295 This option adds an alternative code sequence to work around ARM
296 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
297 to a coherent interconnect.
299 If a Cortex-A53 processor is executing a store or prefetch for
300 write instruction at the same time as a processor in another
301 cluster is executing a cache maintenance operation to the same
302 address, then this erratum might cause a clean cache line to be
303 incorrectly marked as dirty.
305 The workaround promotes data cache clean instructions to
306 data cache clean-and-invalidate.
307 Please note that this option does not necessarily enable the
308 workaround, as it depends on the alternative framework, which will
309 only patch the kernel if an affected CPU is detected.
313 config ARM64_ERRATUM_819472
314 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
317 This option adds an alternative code sequence to work around ARM
318 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
319 present when it is connected to a coherent interconnect.
321 If the processor is executing a load and store exclusive sequence at
322 the same time as a processor in another cluster is executing a cache
323 maintenance operation to the same address, then this erratum might
324 cause data corruption.
326 The workaround promotes data cache clean instructions to
327 data cache clean-and-invalidate.
328 Please note that this does not necessarily enable the workaround,
329 as it depends on the alternative framework, which will only patch
330 the kernel if an affected CPU is detected.
334 config ARM64_ERRATUM_832075
335 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
338 This option adds an alternative code sequence to work around ARM
339 erratum 832075 on Cortex-A57 parts up to r1p2.
341 Affected Cortex-A57 parts might deadlock when exclusive load/store
342 instructions to Write-Back memory are mixed with Device loads.
344 The workaround is to promote device loads to use Load-Acquire
346 Please note that this does not necessarily enable the workaround,
347 as it depends on the alternative framework, which will only patch
348 the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_834220
353 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
357 This option adds an alternative code sequence to work around ARM
358 erratum 834220 on Cortex-A57 parts up to r1p2.
360 Affected Cortex-A57 parts might report a Stage 2 translation
361 fault as the result of a Stage 1 fault for load crossing a
362 page boundary when there is a permission or device memory
363 alignment fault at Stage 1 and a translation fault at Stage 2.
365 The workaround is to verify that the Stage 1 translation
366 doesn't generate a fault before handling the Stage 2 fault.
367 Please note that this does not necessarily enable the workaround,
368 as it depends on the alternative framework, which will only patch
369 the kernel if an affected CPU is detected.
373 config ARM64_ERRATUM_845719
374 bool "Cortex-A53: 845719: a load might read incorrect data"
378 This option adds an alternative code sequence to work around ARM
379 erratum 845719 on Cortex-A53 parts up to r0p4.
381 When running a compat (AArch32) userspace on an affected Cortex-A53
382 part, a load at EL0 from a virtual address that matches the bottom 32
383 bits of the virtual address used by a recent load at (AArch64) EL1
384 might return incorrect data.
386 The workaround is to write the contextidr_el1 register on exception
387 return to a 32-bit task.
388 Please note that this does not necessarily enable the workaround,
389 as it depends on the alternative framework, which will only patch
390 the kernel if an affected CPU is detected.
394 config ARM64_ERRATUM_843419
395 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
399 This option builds kernel modules using the large memory model in
400 order to avoid the use of the ADRP instruction, which can cause
401 a subsequent memory access to use an incorrect address on Cortex-A53
404 Note that the kernel itself must be linked with a version of ld
405 which fixes potentially affected ADRP instructions through the
410 config CAVIUM_ERRATUM_22375
411 bool "Cavium erratum 22375, 24313"
414 Enable workaround for erratum 22375, 24313.
416 This implements two gicv3-its errata workarounds for ThunderX. Both
417 with small impact affecting only ITS table allocation.
419 erratum 22375: only alloc 8MB table size
420 erratum 24313: ignore memory access type
422 The fixes are in ITS initialization and basically ignore memory access
423 type and table size provided by the TYPER and BASER registers.
427 config CAVIUM_ERRATUM_23154
428 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
431 The gicv3 of ThunderX requires a modified version for
432 reading the IAR status to ensure data synchronization
433 (access to icc_iar1_el1 is not sync'ed before and after).
442 default ARM64_4K_PAGES
444 Page size (translation granule) configuration.
446 config ARM64_4K_PAGES
449 This feature enables 4KB pages support.
451 config ARM64_16K_PAGES
454 The system will use 16KB pages support. AArch32 emulation
455 requires applications compiled with 16K (or a multiple of 16K)
458 config ARM64_64K_PAGES
461 This feature enables 64KB pages support (4KB by default)
462 allowing only two levels of page tables and faster TLB
463 look-up. AArch32 emulation requires applications compiled
464 with 64K aligned segments.
469 prompt "Virtual address space size"
470 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
471 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
472 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
474 Allows choosing one of multiple possible virtual address
475 space sizes. The level of translation table is determined by
476 a combination of page size and virtual address space size.
478 config ARM64_VA_BITS_36
479 bool "36-bit" if EXPERT
480 depends on ARM64_16K_PAGES
482 config ARM64_VA_BITS_39
484 depends on ARM64_4K_PAGES
486 config ARM64_VA_BITS_42
488 depends on ARM64_64K_PAGES
490 config ARM64_VA_BITS_47
492 depends on ARM64_16K_PAGES
494 config ARM64_VA_BITS_48
501 default 36 if ARM64_VA_BITS_36
502 default 39 if ARM64_VA_BITS_39
503 default 42 if ARM64_VA_BITS_42
504 default 47 if ARM64_VA_BITS_47
505 default 48 if ARM64_VA_BITS_48
507 config CPU_BIG_ENDIAN
508 bool "Build big-endian kernel"
510 Say Y if you plan on running a kernel in big-endian mode.
513 bool "Multi-core scheduler support"
515 Multi-core scheduler support improves the CPU scheduler's decision
516 making when dealing with multi-core CPU chips at a cost of slightly
517 increased overhead in some places. If unsure say N here.
520 bool "SMT scheduler support"
522 Improves the CPU scheduler's decision making when dealing with
523 MultiThreading at a cost of slightly increased overhead in some
524 places. If unsure say N here.
527 int "Maximum number of CPUs (2-4096)"
529 # These have to remain sorted largest to smallest
533 bool "Support for hot-pluggable CPUs"
534 select GENERIC_IRQ_MIGRATION
536 Say Y here to experiment with turning CPUs off and on. CPUs
537 can be controlled through /sys/devices/system/cpu.
539 source kernel/Kconfig.preempt
540 source kernel/Kconfig.hz
542 config ARCH_HAS_HOLES_MEMORYMODEL
543 def_bool y if SPARSEMEM
545 config ARCH_SPARSEMEM_ENABLE
547 select SPARSEMEM_VMEMMAP_ENABLE
549 config ARCH_SPARSEMEM_DEFAULT
550 def_bool ARCH_SPARSEMEM_ENABLE
552 config ARCH_SELECT_MEMORY_MODEL
553 def_bool ARCH_SPARSEMEM_ENABLE
555 config HAVE_ARCH_PFN_VALID
556 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
558 config HW_PERF_EVENTS
562 config SYS_SUPPORTS_HUGETLBFS
565 config ARCH_WANT_GENERAL_HUGETLB
568 config ARCH_WANT_HUGE_PMD_SHARE
569 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
571 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
574 config ARCH_HAS_CACHE_LINE_SIZE
580 bool "Enable seccomp to safely compute untrusted bytecode"
582 This kernel feature is useful for number crunching applications
583 that may need to compute untrusted bytecode during their
584 execution. By using pipes or other transports made available to
585 the process as file descriptors supporting the read/write
586 syscalls, it's possible to isolate those applications in
587 their own address space using seccomp. Once seccomp is
588 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
589 and the task is only allowed to execute a few safe syscalls
590 defined by each seccomp mode.
597 bool "Xen guest support on ARM64"
598 depends on ARM64 && OF
601 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
603 config FORCE_MAX_ZONEORDER
605 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
606 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
609 The kernel memory allocator divides physically contiguous memory
610 blocks into "zones", where each zone is a power of two number of
611 pages. This option selects the largest power of two that the kernel
612 keeps in the memory allocator. If you need to allocate very large
613 blocks of physically contiguous memory, then you may need to
616 This config option is actually maximum order plus one. For example,
617 a value of 11 means that the largest free memory block is 2^10 pages.
619 We make sure that we can allocate upto a HugePage size for each configuration.
621 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
623 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
624 4M allocations matching the default size used by generic code.
626 menuconfig ARMV8_DEPRECATED
627 bool "Emulate deprecated/obsolete ARMv8 instructions"
630 Legacy software support may require certain instructions
631 that have been deprecated or obsoleted in the architecture.
633 Enable this config to enable selective emulation of these
641 bool "Emulate SWP/SWPB instructions"
643 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
644 they are always undefined. Say Y here to enable software
645 emulation of these instructions for userspace using LDXR/STXR.
647 In some older versions of glibc [<=2.8] SWP is used during futex
648 trylock() operations with the assumption that the code will not
649 be preempted. This invalid assumption may be more likely to fail
650 with SWP emulation enabled, leading to deadlock of the user
653 NOTE: when accessing uncached shared regions, LDXR/STXR rely
654 on an external transaction monitoring block called a global
655 monitor to maintain update atomicity. If your system does not
656 implement a global monitor, this option can cause programs that
657 perform SWP operations to uncached memory to deadlock.
661 config CP15_BARRIER_EMULATION
662 bool "Emulate CP15 Barrier instructions"
664 The CP15 barrier instructions - CP15ISB, CP15DSB, and
665 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
666 strongly recommended to use the ISB, DSB, and DMB
667 instructions instead.
669 Say Y here to enable software emulation of these
670 instructions for AArch32 userspace code. When this option is
671 enabled, CP15 barrier usage is traced which can help
672 identify software that needs updating.
676 config SETEND_EMULATION
677 bool "Emulate SETEND instruction"
679 The SETEND instruction alters the data-endianness of the
680 AArch32 EL0, and is deprecated in ARMv8.
682 Say Y here to enable software emulation of the instruction
683 for AArch32 userspace code.
685 Note: All the cpus on the system must have mixed endian support at EL0
686 for this feature to be enabled. If a new CPU - which doesn't support mixed
687 endian - is hotplugged in after this feature has been enabled, there could
688 be unexpected results in the applications.
693 menu "ARMv8.1 architectural features"
695 config ARM64_HW_AFDBM
696 bool "Support for hardware updates of the Access and Dirty page flags"
699 The ARMv8.1 architecture extensions introduce support for
700 hardware updates of the access and dirty information in page
701 table entries. When enabled in TCR_EL1 (HA and HD bits) on
702 capable processors, accesses to pages with PTE_AF cleared will
703 set this bit instead of raising an access flag fault.
704 Similarly, writes to read-only pages with the DBM bit set will
705 clear the read-only bit (AP[2]) instead of raising a
708 Kernels built with this configuration option enabled continue
709 to work on pre-ARMv8.1 hardware and the performance impact is
710 minimal. If unsure, say Y.
713 bool "Enable support for Privileged Access Never (PAN)"
716 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
717 prevents the kernel or hypervisor from accessing user-space (EL0)
720 Choosing this option will cause any unprotected (not using
721 copy_to_user et al) memory access to fail with a permission fault.
723 The feature is detected at runtime, and will remain as a 'nop'
724 instruction if the cpu does not implement the feature.
726 config ARM64_LSE_ATOMICS
727 bool "Atomic instructions"
729 As part of the Large System Extensions, ARMv8.1 introduces new
730 atomic instructions that are designed specifically to scale in
733 Say Y here to make use of these instructions for the in-kernel
734 atomic routines. This incurs a small overhead on CPUs that do
735 not support these instructions and requires the kernel to be
736 built with binutils >= 2.25.
745 string "Default kernel command string"
748 Provide a set of default command-line options at build time by
749 entering them here. As a minimum, you should specify the the
750 root device (e.g. root=/dev/nfs).
753 prompt "Kernel command line type" if CMDLINE != ""
754 default CMDLINE_FROM_BOOTLOADER
756 config CMDLINE_FROM_BOOTLOADER
757 bool "Use bootloader kernel arguments if available"
759 Uses the command-line options passed by the boot loader. If
760 the boot loader doesn't provide any, the default kernel command
761 string provided in CMDLINE will be used.
763 config CMDLINE_EXTEND
764 bool "Extend bootloader kernel arguments"
766 The command-line arguments provided by the boot loader will be
767 appended to the default kernel command string.
770 bool "Always use the default kernel command string"
772 Always use the default kernel command string, even if the boot
773 loader passes other arguments to the kernel.
774 This is useful if you cannot or don't want to change the
775 command-line options your boot loader passes to the kernel.
782 bool "UEFI runtime support"
783 depends on OF && !CPU_BIG_ENDIAN
786 select EFI_PARAMS_FROM_FDT
787 select EFI_RUNTIME_WRAPPERS
792 This option provides support for runtime services provided
793 by UEFI firmware (such as non-volatile variables, realtime
794 clock, and platform reset). A UEFI stub is also provided to
795 allow the kernel to be booted as an EFI application. This
796 is only useful on systems that have UEFI firmware.
799 bool "Enable support for SMBIOS (DMI) tables"
803 This enables SMBIOS/DMI feature for systems.
805 This option is only useful on systems that have UEFI firmware.
806 However, even with this option, the resultant kernel should
807 continue to boot on existing non-UEFI platforms.
809 config BUILD_ARM64_APPENDED_DTB_IMAGE
810 bool "Build a concatenated Image.gz/dtb by default"
813 Enabling this option will cause a concatenated Image.gz and list of
814 DTBs to be built by default (instead of a standalone Image.gz.)
815 The image will built in arch/arm64/boot/Image.gz-dtb
817 config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
818 string "Default dtb names"
819 depends on BUILD_ARM64_APPENDED_DTB_IMAGE
821 Space separated list of names of dtbs to append when
822 building a concatenated Image.gz-dtb.
826 menu "Userspace binary formats"
828 source "fs/Kconfig.binfmt"
831 bool "Kernel support for 32-bit EL0"
832 depends on ARM64_4K_PAGES || EXPERT
833 select COMPAT_BINFMT_ELF
835 select OLD_SIGSUSPEND3
836 select COMPAT_OLD_SIGACTION
838 This option enables support for a 32-bit EL0 running under a 64-bit
839 kernel at EL1. AArch32-specific components such as system calls,
840 the user helper functions, VFP support and the ptrace interface are
841 handled appropriately by the kernel.
843 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
844 that you will only be able to execute AArch32 binaries that were compiled
845 with page size aligned segments.
847 If you want to execute 32-bit userspace applications, say Y.
849 config SYSVIPC_COMPAT
851 depends on COMPAT && SYSVIPC
855 menu "Power management options"
857 source "kernel/power/Kconfig"
859 config ARCH_SUSPEND_POSSIBLE
864 menu "CPU Power Management"
866 source "drivers/cpuidle/Kconfig"
868 source "drivers/cpufreq/Kconfig"
874 source "drivers/Kconfig"
876 source "drivers/firmware/Kconfig"
878 source "drivers/acpi/Kconfig"
882 source "arch/arm64/kvm/Kconfig"
884 source "arch/arm64/Kconfig.debug"
886 source "security/Kconfig"
888 source "crypto/Kconfig"
890 source "arch/arm64/crypto/Kconfig"