3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HARDENED_USERCOPY
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_MMAP_RND_BITS
58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
59 select HAVE_ARCH_SECCOMP_FILTER
60 select HAVE_ARCH_TRACEHOOK
62 select HAVE_C_RECORDMCOUNT
63 select HAVE_CC_STACKPROTECTOR
64 select HAVE_CMPXCHG_DOUBLE
65 select HAVE_CMPXCHG_LOCAL
66 select HAVE_DEBUG_BUGVERBOSE
67 select HAVE_DEBUG_KMEMLEAK
68 select HAVE_DMA_API_DEBUG
70 select HAVE_DMA_CONTIGUOUS
71 select HAVE_DYNAMIC_FTRACE
72 select HAVE_EFFICIENT_UNALIGNED_ACCESS
73 select HAVE_FTRACE_MCOUNT_RECORD
74 select HAVE_FUNCTION_TRACER
75 select HAVE_FUNCTION_GRAPH_TRACER
76 select HAVE_GENERIC_DMA_COHERENT
77 select HAVE_HW_BREAKPOINT if PERF_EVENTS
78 select HAVE_IRQ_TIME_ACCOUNTING
80 select HAVE_PATA_PLATFORM
81 select HAVE_PERF_EVENTS
83 select HAVE_PERF_USER_STACK_DUMP
84 select HAVE_RCU_TABLE_FREE
85 select HAVE_SYSCALL_TRACEPOINTS
86 select IOMMU_DMA if IOMMU_SUPPORT
88 select IRQ_FORCED_THREADING
89 select MODULES_USE_ELF_RELA
92 select OF_EARLY_FLATTREE
93 select OF_RESERVED_MEM
94 select PERF_USE_VMALLOC
99 select SYSCTL_EXCEPTION_TRACE
100 select HAVE_CONTEXT_TRACKING
102 ARM 64-bit (AArch64) Linux support.
107 config ARCH_PHYS_ADDR_T_64BIT
113 config ARCH_MMAP_RND_BITS_MIN
114 default 14 if ARM64_64K_PAGES
115 default 16 if ARM64_16K_PAGES
118 # max bits determined by the following formula:
119 # VA_BITS - PAGE_SHIFT - 3
120 config ARCH_MMAP_RND_BITS_MAX
121 default 19 if ARM64_VA_BITS=36
122 default 24 if ARM64_VA_BITS=39
123 default 27 if ARM64_VA_BITS=42
124 default 30 if ARM64_VA_BITS=47
125 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
126 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
127 default 33 if ARM64_VA_BITS=48
128 default 14 if ARM64_64K_PAGES
129 default 16 if ARM64_16K_PAGES
132 config ARCH_MMAP_RND_COMPAT_BITS_MIN
133 default 7 if ARM64_64K_PAGES
134 default 9 if ARM64_16K_PAGES
137 config ARCH_MMAP_RND_COMPAT_BITS_MAX
143 config ILLEGAL_POINTER_VALUE
145 default 0xdead000000000000
147 config STACKTRACE_SUPPORT
150 config ILLEGAL_POINTER_VALUE
152 default 0xdead000000000000
154 config LOCKDEP_SUPPORT
157 config TRACE_IRQFLAGS_SUPPORT
160 config RWSEM_XCHGADD_ALGORITHM
167 config GENERIC_BUG_RELATIVE_POINTERS
169 depends on GENERIC_BUG
171 config GENERIC_HWEIGHT
177 config GENERIC_CALIBRATE_DELAY
183 config HAVE_GENERIC_RCU_GUP
186 config ARCH_DMA_ADDR_T_64BIT
189 config NEED_DMA_MAP_STATE
192 config NEED_SG_DMA_LENGTH
204 config KERNEL_MODE_NEON
207 config FIX_EARLYCON_MEM
210 config PGTABLE_LEVELS
212 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
213 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
214 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
215 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
216 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
217 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
219 source "init/Kconfig"
221 source "kernel/Kconfig.freezer"
223 source "arch/arm64/Kconfig.platforms"
230 This feature enables support for PCI bus system. If you say Y
231 here, the kernel will include drivers and infrastructure code
232 to support PCI bus devices.
237 config PCI_DOMAINS_GENERIC
243 source "drivers/pci/Kconfig"
244 source "drivers/pci/pcie/Kconfig"
245 source "drivers/pci/hotplug/Kconfig"
249 menu "Kernel Features"
251 menu "ARM errata workarounds via the alternatives framework"
253 config ARM64_ERRATUM_826319
254 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
257 This option adds an alternative code sequence to work around ARM
258 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
259 AXI master interface and an L2 cache.
261 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
262 and is unable to accept a certain write via this interface, it will
263 not progress on read data presented on the read data channel and the
266 The workaround promotes data cache clean instructions to
267 data cache clean-and-invalidate.
268 Please note that this does not necessarily enable the workaround,
269 as it depends on the alternative framework, which will only patch
270 the kernel if an affected CPU is detected.
274 config ARM64_ERRATUM_827319
275 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
278 This option adds an alternative code sequence to work around ARM
279 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
280 master interface and an L2 cache.
282 Under certain conditions this erratum can cause a clean line eviction
283 to occur at the same time as another transaction to the same address
284 on the AMBA 5 CHI interface, which can cause data corruption if the
285 interconnect reorders the two transactions.
287 The workaround promotes data cache clean instructions to
288 data cache clean-and-invalidate.
289 Please note that this does not necessarily enable the workaround,
290 as it depends on the alternative framework, which will only patch
291 the kernel if an affected CPU is detected.
295 config ARM64_ERRATUM_824069
296 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
299 This option adds an alternative code sequence to work around ARM
300 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
301 to a coherent interconnect.
303 If a Cortex-A53 processor is executing a store or prefetch for
304 write instruction at the same time as a processor in another
305 cluster is executing a cache maintenance operation to the same
306 address, then this erratum might cause a clean cache line to be
307 incorrectly marked as dirty.
309 The workaround promotes data cache clean instructions to
310 data cache clean-and-invalidate.
311 Please note that this option does not necessarily enable the
312 workaround, as it depends on the alternative framework, which will
313 only patch the kernel if an affected CPU is detected.
317 config ARM64_ERRATUM_819472
318 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
321 This option adds an alternative code sequence to work around ARM
322 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
323 present when it is connected to a coherent interconnect.
325 If the processor is executing a load and store exclusive sequence at
326 the same time as a processor in another cluster is executing a cache
327 maintenance operation to the same address, then this erratum might
328 cause data corruption.
330 The workaround promotes data cache clean instructions to
331 data cache clean-and-invalidate.
332 Please note that this does not necessarily enable the workaround,
333 as it depends on the alternative framework, which will only patch
334 the kernel if an affected CPU is detected.
338 config ARM64_ERRATUM_832075
339 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
342 This option adds an alternative code sequence to work around ARM
343 erratum 832075 on Cortex-A57 parts up to r1p2.
345 Affected Cortex-A57 parts might deadlock when exclusive load/store
346 instructions to Write-Back memory are mixed with Device loads.
348 The workaround is to promote device loads to use Load-Acquire
350 Please note that this does not necessarily enable the workaround,
351 as it depends on the alternative framework, which will only patch
352 the kernel if an affected CPU is detected.
356 config ARM64_ERRATUM_834220
357 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
361 This option adds an alternative code sequence to work around ARM
362 erratum 834220 on Cortex-A57 parts up to r1p2.
364 Affected Cortex-A57 parts might report a Stage 2 translation
365 fault as the result of a Stage 1 fault for load crossing a
366 page boundary when there is a permission or device memory
367 alignment fault at Stage 1 and a translation fault at Stage 2.
369 The workaround is to verify that the Stage 1 translation
370 doesn't generate a fault before handling the Stage 2 fault.
371 Please note that this does not necessarily enable the workaround,
372 as it depends on the alternative framework, which will only patch
373 the kernel if an affected CPU is detected.
377 config ARM64_ERRATUM_845719
378 bool "Cortex-A53: 845719: a load might read incorrect data"
382 This option adds an alternative code sequence to work around ARM
383 erratum 845719 on Cortex-A53 parts up to r0p4.
385 When running a compat (AArch32) userspace on an affected Cortex-A53
386 part, a load at EL0 from a virtual address that matches the bottom 32
387 bits of the virtual address used by a recent load at (AArch64) EL1
388 might return incorrect data.
390 The workaround is to write the contextidr_el1 register on exception
391 return to a 32-bit task.
392 Please note that this does not necessarily enable the workaround,
393 as it depends on the alternative framework, which will only patch
394 the kernel if an affected CPU is detected.
398 config ARM64_ERRATUM_843419
399 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
402 select ARM64_MODULE_CMODEL_LARGE
404 This option builds kernel modules using the large memory model in
405 order to avoid the use of the ADRP instruction, which can cause
406 a subsequent memory access to use an incorrect address on Cortex-A53
409 Note that the kernel itself must be linked with a version of ld
410 which fixes potentially affected ADRP instructions through the
415 config CAVIUM_ERRATUM_22375
416 bool "Cavium erratum 22375, 24313"
419 Enable workaround for erratum 22375, 24313.
421 This implements two gicv3-its errata workarounds for ThunderX. Both
422 with small impact affecting only ITS table allocation.
424 erratum 22375: only alloc 8MB table size
425 erratum 24313: ignore memory access type
427 The fixes are in ITS initialization and basically ignore memory access
428 type and table size provided by the TYPER and BASER registers.
432 config CAVIUM_ERRATUM_23144
433 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
437 ITS SYNC command hang for cross node io and collections/cpu mapping.
441 config CAVIUM_ERRATUM_23154
442 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
445 The gicv3 of ThunderX requires a modified version for
446 reading the IAR status to ensure data synchronization
447 (access to icc_iar1_el1 is not sync'ed before and after).
451 config CAVIUM_ERRATUM_27456
452 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
455 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
456 instructions may cause the icache to become corrupted if it
457 contains data for a non-current ASID. The fix is to
458 invalidate the icache when changing the mm context.
467 default ARM64_4K_PAGES
469 Page size (translation granule) configuration.
471 config ARM64_4K_PAGES
474 This feature enables 4KB pages support.
476 config ARM64_16K_PAGES
479 The system will use 16KB pages support. AArch32 emulation
480 requires applications compiled with 16K (or a multiple of 16K)
483 config ARM64_64K_PAGES
486 This feature enables 64KB pages support (4KB by default)
487 allowing only two levels of page tables and faster TLB
488 look-up. AArch32 emulation requires applications compiled
489 with 64K aligned segments.
494 prompt "Virtual address space size"
495 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
496 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
497 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
499 Allows choosing one of multiple possible virtual address
500 space sizes. The level of translation table is determined by
501 a combination of page size and virtual address space size.
503 config ARM64_VA_BITS_36
504 bool "36-bit" if EXPERT
505 depends on ARM64_16K_PAGES
507 config ARM64_VA_BITS_39
509 depends on ARM64_4K_PAGES
511 config ARM64_VA_BITS_42
513 depends on ARM64_64K_PAGES
515 config ARM64_VA_BITS_47
517 depends on ARM64_16K_PAGES
519 config ARM64_VA_BITS_48
526 default 36 if ARM64_VA_BITS_36
527 default 39 if ARM64_VA_BITS_39
528 default 42 if ARM64_VA_BITS_42
529 default 47 if ARM64_VA_BITS_47
530 default 48 if ARM64_VA_BITS_48
532 config CPU_BIG_ENDIAN
533 bool "Build big-endian kernel"
535 Say Y if you plan on running a kernel in big-endian mode.
538 bool "Multi-core scheduler support"
540 Multi-core scheduler support improves the CPU scheduler's decision
541 making when dealing with multi-core CPU chips at a cost of slightly
542 increased overhead in some places. If unsure say N here.
545 bool "SMT scheduler support"
547 Improves the CPU scheduler's decision making when dealing with
548 MultiThreading at a cost of slightly increased overhead in some
549 places. If unsure say N here.
552 int "Maximum number of CPUs (2-4096)"
554 # These have to remain sorted largest to smallest
558 bool "Support for hot-pluggable CPUs"
559 select GENERIC_IRQ_MIGRATION
561 Say Y here to experiment with turning CPUs off and on. CPUs
562 can be controlled through /sys/devices/system/cpu.
564 source kernel/Kconfig.preempt
565 source kernel/Kconfig.hz
567 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
570 config ARCH_HAS_HOLES_MEMORYMODEL
571 def_bool y if SPARSEMEM
573 config ARCH_SPARSEMEM_ENABLE
575 select SPARSEMEM_VMEMMAP_ENABLE
577 config ARCH_SPARSEMEM_DEFAULT
578 def_bool ARCH_SPARSEMEM_ENABLE
580 config ARCH_SELECT_MEMORY_MODEL
581 def_bool ARCH_SPARSEMEM_ENABLE
583 config HAVE_ARCH_PFN_VALID
584 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
586 config HW_PERF_EVENTS
590 config SYS_SUPPORTS_HUGETLBFS
593 config ARCH_WANT_HUGE_PMD_SHARE
594 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
596 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
599 config ARCH_HAS_CACHE_LINE_SIZE
605 bool "Enable seccomp to safely compute untrusted bytecode"
607 This kernel feature is useful for number crunching applications
608 that may need to compute untrusted bytecode during their
609 execution. By using pipes or other transports made available to
610 the process as file descriptors supporting the read/write
611 syscalls, it's possible to isolate those applications in
612 their own address space using seccomp. Once seccomp is
613 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
614 and the task is only allowed to execute a few safe syscalls
615 defined by each seccomp mode.
622 bool "Xen guest support on ARM64"
623 depends on ARM64 && OF
626 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
628 config FORCE_MAX_ZONEORDER
630 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
631 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
634 The kernel memory allocator divides physically contiguous memory
635 blocks into "zones", where each zone is a power of two number of
636 pages. This option selects the largest power of two that the kernel
637 keeps in the memory allocator. If you need to allocate very large
638 blocks of physically contiguous memory, then you may need to
641 This config option is actually maximum order plus one. For example,
642 a value of 11 means that the largest free memory block is 2^10 pages.
644 We make sure that we can allocate upto a HugePage size for each configuration.
646 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
648 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
649 4M allocations matching the default size used by generic code.
651 menuconfig ARMV8_DEPRECATED
652 bool "Emulate deprecated/obsolete ARMv8 instructions"
655 Legacy software support may require certain instructions
656 that have been deprecated or obsoleted in the architecture.
658 Enable this config to enable selective emulation of these
666 bool "Emulate SWP/SWPB instructions"
668 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
669 they are always undefined. Say Y here to enable software
670 emulation of these instructions for userspace using LDXR/STXR.
672 In some older versions of glibc [<=2.8] SWP is used during futex
673 trylock() operations with the assumption that the code will not
674 be preempted. This invalid assumption may be more likely to fail
675 with SWP emulation enabled, leading to deadlock of the user
678 NOTE: when accessing uncached shared regions, LDXR/STXR rely
679 on an external transaction monitoring block called a global
680 monitor to maintain update atomicity. If your system does not
681 implement a global monitor, this option can cause programs that
682 perform SWP operations to uncached memory to deadlock.
686 config CP15_BARRIER_EMULATION
687 bool "Emulate CP15 Barrier instructions"
689 The CP15 barrier instructions - CP15ISB, CP15DSB, and
690 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
691 strongly recommended to use the ISB, DSB, and DMB
692 instructions instead.
694 Say Y here to enable software emulation of these
695 instructions for AArch32 userspace code. When this option is
696 enabled, CP15 barrier usage is traced which can help
697 identify software that needs updating.
701 config SETEND_EMULATION
702 bool "Emulate SETEND instruction"
704 The SETEND instruction alters the data-endianness of the
705 AArch32 EL0, and is deprecated in ARMv8.
707 Say Y here to enable software emulation of the instruction
708 for AArch32 userspace code.
710 Note: All the cpus on the system must have mixed endian support at EL0
711 for this feature to be enabled. If a new CPU - which doesn't support mixed
712 endian - is hotplugged in after this feature has been enabled, there could
713 be unexpected results in the applications.
718 menu "ARMv8.1 architectural features"
720 config ARM64_HW_AFDBM
721 bool "Support for hardware updates of the Access and Dirty page flags"
724 The ARMv8.1 architecture extensions introduce support for
725 hardware updates of the access and dirty information in page
726 table entries. When enabled in TCR_EL1 (HA and HD bits) on
727 capable processors, accesses to pages with PTE_AF cleared will
728 set this bit instead of raising an access flag fault.
729 Similarly, writes to read-only pages with the DBM bit set will
730 clear the read-only bit (AP[2]) instead of raising a
733 Kernels built with this configuration option enabled continue
734 to work on pre-ARMv8.1 hardware and the performance impact is
735 minimal. If unsure, say Y.
738 bool "Enable support for Privileged Access Never (PAN)"
741 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
742 prevents the kernel or hypervisor from accessing user-space (EL0)
745 Choosing this option will cause any unprotected (not using
746 copy_to_user et al) memory access to fail with a permission fault.
748 The feature is detected at runtime, and will remain as a 'nop'
749 instruction if the cpu does not implement the feature.
751 config ARM64_LSE_ATOMICS
752 bool "Atomic instructions"
754 As part of the Large System Extensions, ARMv8.1 introduces new
755 atomic instructions that are designed specifically to scale in
758 Say Y here to make use of these instructions for the in-kernel
759 atomic routines. This incurs a small overhead on CPUs that do
760 not support these instructions and requires the kernel to be
761 built with binutils >= 2.25.
766 bool "Enable support for User Access Override (UAO)"
769 User Access Override (UAO; part of the ARMv8.2 Extensions)
770 causes the 'unprivileged' variant of the load/store instructions to
771 be overriden to be privileged.
773 This option changes get_user() and friends to use the 'unprivileged'
774 variant of the load/store instructions. This ensures that user-space
775 really did have access to the supplied memory. When addr_limit is
776 set to kernel memory the UAO bit will be set, allowing privileged
777 access to kernel memory.
779 Choosing this option will cause copy_to_user() et al to use user-space
782 The feature is detected at runtime, the kernel will use the
783 regular load/store instructions if the cpu does not implement the
786 config ARM64_MODULE_CMODEL_LARGE
789 config ARM64_MODULE_PLTS
791 select ARM64_MODULE_CMODEL_LARGE
792 select HAVE_MOD_ARCH_SPECIFIC
797 This builds the kernel as a Position Independent Executable (PIE),
798 which retains all relocation metadata required to relocate the
799 kernel binary at runtime to a different virtual address than the
800 address it was linked at.
801 Since AArch64 uses the RELA relocation format, this requires a
802 relocation pass at runtime even if the kernel is loaded at the
803 same address it was linked at.
805 config RANDOMIZE_BASE
806 bool "Randomize the address of the kernel image"
807 select ARM64_MODULE_PLTS
810 Randomizes the virtual address at which the kernel image is
811 loaded, as a security feature that deters exploit attempts
812 relying on knowledge of the location of kernel internals.
814 It is the bootloader's job to provide entropy, by passing a
815 random u64 value in /chosen/kaslr-seed at kernel entry.
817 When booting via the UEFI stub, it will invoke the firmware's
818 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
819 to the kernel proper. In addition, it will randomise the physical
820 location of the kernel Image as well.
824 config RANDOMIZE_MODULE_REGION_FULL
825 bool "Randomize the module region independently from the core kernel"
826 depends on RANDOMIZE_BASE
829 Randomizes the location of the module region without considering the
830 location of the core kernel. This way, it is impossible for modules
831 to leak information about the location of core kernel data structures
832 but it does imply that function calls between modules and the core
833 kernel will need to be resolved via veneers in the module PLT.
835 When this option is not set, the module region will be randomized over
836 a limited range that contains the [_stext, _etext] interval of the
837 core kernel, so branch relocations are always in range.
843 config ARM64_ACPI_PARKING_PROTOCOL
844 bool "Enable support for the ARM64 ACPI parking protocol"
847 Enable support for the ARM64 ACPI parking protocol. If disabled
848 the kernel will not allow booting through the ARM64 ACPI parking
849 protocol even if the corresponding data is present in the ACPI
853 string "Default kernel command string"
856 Provide a set of default command-line options at build time by
857 entering them here. As a minimum, you should specify the the
858 root device (e.g. root=/dev/nfs).
861 prompt "Kernel command line type" if CMDLINE != ""
862 default CMDLINE_FROM_BOOTLOADER
864 config CMDLINE_FROM_BOOTLOADER
865 bool "Use bootloader kernel arguments if available"
867 Uses the command-line options passed by the boot loader. If
868 the boot loader doesn't provide any, the default kernel command
869 string provided in CMDLINE will be used.
871 config CMDLINE_EXTEND
872 bool "Extend bootloader kernel arguments"
874 The command-line arguments provided by the boot loader will be
875 appended to the default kernel command string.
878 bool "Always use the default kernel command string"
880 Always use the default kernel command string, even if the boot
881 loader passes other arguments to the kernel.
882 This is useful if you cannot or don't want to change the
883 command-line options your boot loader passes to the kernel.
890 bool "UEFI runtime support"
891 depends on OF && !CPU_BIG_ENDIAN
894 select EFI_PARAMS_FROM_FDT
895 select EFI_RUNTIME_WRAPPERS
900 This option provides support for runtime services provided
901 by UEFI firmware (such as non-volatile variables, realtime
902 clock, and platform reset). A UEFI stub is also provided to
903 allow the kernel to be booted as an EFI application. This
904 is only useful on systems that have UEFI firmware.
907 bool "Enable support for SMBIOS (DMI) tables"
911 This enables SMBIOS/DMI feature for systems.
913 This option is only useful on systems that have UEFI firmware.
914 However, even with this option, the resultant kernel should
915 continue to boot on existing non-UEFI platforms.
917 config BUILD_ARM64_APPENDED_DTB_IMAGE
918 bool "Build a concatenated Image.gz/dtb by default"
921 Enabling this option will cause a concatenated Image.gz and list of
922 DTBs to be built by default (instead of a standalone Image.gz.)
923 The image will built in arch/arm64/boot/Image.gz-dtb
925 config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
926 string "Default dtb names"
927 depends on BUILD_ARM64_APPENDED_DTB_IMAGE
929 Space separated list of names of dtbs to append when
930 building a concatenated Image.gz-dtb.
934 menu "Userspace binary formats"
936 source "fs/Kconfig.binfmt"
939 bool "Kernel support for 32-bit EL0"
940 depends on ARM64_4K_PAGES || EXPERT
941 select COMPAT_BINFMT_ELF
943 select OLD_SIGSUSPEND3
944 select COMPAT_OLD_SIGACTION
946 This option enables support for a 32-bit EL0 running under a 64-bit
947 kernel at EL1. AArch32-specific components such as system calls,
948 the user helper functions, VFP support and the ptrace interface are
949 handled appropriately by the kernel.
951 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
952 that you will only be able to execute AArch32 binaries that were compiled
953 with page size aligned segments.
955 If you want to execute 32-bit userspace applications, say Y.
957 config SYSVIPC_COMPAT
959 depends on COMPAT && SYSVIPC
963 menu "Power management options"
965 source "kernel/power/Kconfig"
967 config ARCH_SUSPEND_POSSIBLE
972 menu "CPU Power Management"
974 source "drivers/cpuidle/Kconfig"
976 source "drivers/cpufreq/Kconfig"
982 source "drivers/Kconfig"
984 source "drivers/firmware/Kconfig"
986 source "drivers/acpi/Kconfig"
990 source "arch/arm64/kvm/Kconfig"
992 source "arch/arm64/Kconfig.debug"
994 source "security/Kconfig"
996 source "crypto/Kconfig"
998 source "arch/arm64/crypto/Kconfig"
1001 source "lib/Kconfig"