3 select ACPI_GENERIC_GSI if ACPI
4 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_GCOV_PROFILE_ALL
8 select ARCH_HAS_SG_CHAIN
9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_WANT_OPTIONAL_GPIOLIB
13 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
14 select ARCH_WANT_FRAME_POINTERS
18 select AUDIT_ARCH_COMPAT_GENERIC
19 select ARM_GIC_V2M if PCI_MSI
21 select ARM_GIC_V3_ITS if PCI_MSI
22 select BUILDTIME_EXTABLE_SORT
23 select CLONE_BACKWARDS
25 select CPU_PM if (SUSPEND || CPU_IDLE)
26 select DCACHE_WORD_ACCESS
27 select GENERIC_ALLOCATOR
28 select GENERIC_CLOCKEVENTS
29 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
30 select GENERIC_CPU_AUTOPROBE
31 select GENERIC_EARLY_IOREMAP
32 select GENERIC_IRQ_PROBE
33 select GENERIC_IRQ_SHOW
34 select GENERIC_IRQ_SHOW_LEVEL
35 select GENERIC_PCI_IOMAP
36 select GENERIC_SCHED_CLOCK
37 select GENERIC_SMP_IDLE_THREAD
38 select GENERIC_STRNCPY_FROM_USER
39 select GENERIC_STRNLEN_USER
40 select GENERIC_TIME_VSYSCALL
41 select HANDLE_DOMAIN_IRQ
42 select HARDIRQS_SW_RESEND
43 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
44 select HAVE_ARCH_AUDITSYSCALL
45 select HAVE_ARCH_BITREVERSE
46 select HAVE_ARCH_JUMP_LABEL
48 select HAVE_ARCH_SECCOMP_FILTER
49 select HAVE_ARCH_TRACEHOOK
51 select HAVE_C_RECORDMCOUNT
52 select HAVE_CC_STACKPROTECTOR
53 select HAVE_CMPXCHG_DOUBLE
54 select HAVE_DEBUG_BUGVERBOSE
55 select HAVE_DEBUG_KMEMLEAK
56 select HAVE_DMA_API_DEBUG
58 select HAVE_DMA_CONTIGUOUS
59 select HAVE_DYNAMIC_FTRACE
60 select HAVE_EFFICIENT_UNALIGNED_ACCESS
61 select HAVE_FTRACE_MCOUNT_RECORD
62 select HAVE_FUNCTION_TRACER
63 select HAVE_FUNCTION_GRAPH_TRACER
64 select HAVE_GENERIC_DMA_COHERENT
65 select HAVE_HW_BREAKPOINT if PERF_EVENTS
67 select HAVE_PATA_PLATFORM
68 select HAVE_PERF_EVENTS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE
72 select HAVE_SYSCALL_TRACEPOINTS
74 select MODULES_USE_ELF_RELA
77 select OF_EARLY_FLATTREE
78 select OF_RESERVED_MEM
79 select PERF_USE_VMALLOC
84 select SYSCTL_EXCEPTION_TRACE
85 select HAVE_CONTEXT_TRACKING
87 ARM 64-bit (AArch64) Linux support.
92 config ARCH_PHYS_ADDR_T_64BIT
101 config STACKTRACE_SUPPORT
104 config LOCKDEP_SUPPORT
107 config TRACE_IRQFLAGS_SUPPORT
110 config RWSEM_XCHGADD_ALGORITHM
113 config GENERIC_HWEIGHT
119 config GENERIC_CALIBRATE_DELAY
125 config HAVE_GENERIC_RCU_GUP
128 config ARCH_DMA_ADDR_T_64BIT
131 config NEED_DMA_MAP_STATE
134 config NEED_SG_DMA_LENGTH
143 config KERNEL_MODE_NEON
146 config FIX_EARLYCON_MEM
149 config PGTABLE_LEVELS
151 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
152 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
153 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
154 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
156 source "init/Kconfig"
158 source "kernel/Kconfig.freezer"
160 menu "Platform selection"
165 This enables support for Samsung Exynos SoC family
168 bool "ARMv8 based Samsung Exynos7"
170 select COMMON_CLK_SAMSUNG
171 select HAVE_S3C2410_WATCHDOG if WATCHDOG
172 select HAVE_S3C_RTC if RTC_CLASS
174 select PINCTRL_EXYNOS
177 This enables support for Samsung Exynos7 SoC family
179 config ARCH_FSL_LS2085A
180 bool "Freescale LS2085A SOC"
182 This enables support for Freescale LS2085A SOC.
185 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
189 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
192 bool "Qualcomm Platforms"
195 This enables support for the ARMv8 based Qualcomm chipsets.
198 bool "AMD Seattle SoC Family"
200 This enables support for AMD Seattle SOC Family
203 bool "NVIDIA Tegra SoC Family"
204 select ARCH_HAS_RESET_CONTROLLER
205 select ARCH_REQUIRE_GPIOLIB
209 select GENERIC_CLOCKEVENTS
212 select RESET_CONTROLLER
214 This enables support for the NVIDIA Tegra SoC family.
216 config ARCH_TEGRA_132_SOC
217 bool "NVIDIA Tegra132 SoC"
218 depends on ARCH_TEGRA
219 select PINCTRL_TEGRA124
220 select USB_ULPI if USB_PHY
221 select USB_ULPI_VIEWPORT if USB_PHY
223 Enable support for NVIDIA Tegra132 SoC, based on the Denver
224 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
225 but contains an NVIDIA Denver CPU complex in place of
226 Tegra124's "4+1" Cortex-A15 CPU complex.
229 bool "Spreadtrum SoC platform"
231 Support for Spreadtrum ARM based SoCs
234 bool "Cavium Inc. Thunder SoC Family"
236 This enables support for Cavium's Thunder Family of SoCs.
239 bool "ARMv8 software model (Versatile Express)"
240 select ARCH_REQUIRE_GPIOLIB
241 select COMMON_CLK_VERSATILE
242 select POWER_RESET_VEXPRESS
243 select VEXPRESS_CONFIG
245 This enables support for the ARMv8 software model (Versatile
249 bool "AppliedMicro X-Gene SOC Family"
251 This enables support for AppliedMicro X-Gene SOC Family
254 bool "Xilinx ZynqMP Family"
256 This enables support for Xilinx ZynqMP Family
265 This feature enables support for PCI bus system. If you say Y
266 here, the kernel will include drivers and infrastructure code
267 to support PCI bus devices.
272 config PCI_DOMAINS_GENERIC
278 source "drivers/pci/Kconfig"
279 source "drivers/pci/pcie/Kconfig"
280 source "drivers/pci/hotplug/Kconfig"
284 menu "Kernel Features"
286 menu "ARM errata workarounds via the alternatives framework"
288 config ARM64_ERRATUM_826319
289 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
292 This option adds an alternative code sequence to work around ARM
293 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
294 AXI master interface and an L2 cache.
296 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
297 and is unable to accept a certain write via this interface, it will
298 not progress on read data presented on the read data channel and the
301 The workaround promotes data cache clean instructions to
302 data cache clean-and-invalidate.
303 Please note that this does not necessarily enable the workaround,
304 as it depends on the alternative framework, which will only patch
305 the kernel if an affected CPU is detected.
309 config ARM64_ERRATUM_827319
310 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
313 This option adds an alternative code sequence to work around ARM
314 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
315 master interface and an L2 cache.
317 Under certain conditions this erratum can cause a clean line eviction
318 to occur at the same time as another transaction to the same address
319 on the AMBA 5 CHI interface, which can cause data corruption if the
320 interconnect reorders the two transactions.
322 The workaround promotes data cache clean instructions to
323 data cache clean-and-invalidate.
324 Please note that this does not necessarily enable the workaround,
325 as it depends on the alternative framework, which will only patch
326 the kernel if an affected CPU is detected.
330 config ARM64_ERRATUM_824069
331 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
334 This option adds an alternative code sequence to work around ARM
335 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
336 to a coherent interconnect.
338 If a Cortex-A53 processor is executing a store or prefetch for
339 write instruction at the same time as a processor in another
340 cluster is executing a cache maintenance operation to the same
341 address, then this erratum might cause a clean cache line to be
342 incorrectly marked as dirty.
344 The workaround promotes data cache clean instructions to
345 data cache clean-and-invalidate.
346 Please note that this option does not necessarily enable the
347 workaround, as it depends on the alternative framework, which will
348 only patch the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_819472
353 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
356 This option adds an alternative code sequence to work around ARM
357 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
358 present when it is connected to a coherent interconnect.
360 If the processor is executing a load and store exclusive sequence at
361 the same time as a processor in another cluster is executing a cache
362 maintenance operation to the same address, then this erratum might
363 cause data corruption.
365 The workaround promotes data cache clean instructions to
366 data cache clean-and-invalidate.
367 Please note that this does not necessarily enable the workaround,
368 as it depends on the alternative framework, which will only patch
369 the kernel if an affected CPU is detected.
373 config ARM64_ERRATUM_832075
374 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
377 This option adds an alternative code sequence to work around ARM
378 erratum 832075 on Cortex-A57 parts up to r1p2.
380 Affected Cortex-A57 parts might deadlock when exclusive load/store
381 instructions to Write-Back memory are mixed with Device loads.
383 The workaround is to promote device loads to use Load-Acquire
385 Please note that this does not necessarily enable the workaround,
386 as it depends on the alternative framework, which will only patch
387 the kernel if an affected CPU is detected.
391 config ARM64_ERRATUM_845719
392 bool "Cortex-A53: 845719: a load might read incorrect data"
396 This option adds an alternative code sequence to work around ARM
397 erratum 845719 on Cortex-A53 parts up to r0p4.
399 When running a compat (AArch32) userspace on an affected Cortex-A53
400 part, a load at EL0 from a virtual address that matches the bottom 32
401 bits of the virtual address used by a recent load at (AArch64) EL1
402 might return incorrect data.
404 The workaround is to write the contextidr_el1 register on exception
405 return to a 32-bit task.
406 Please note that this does not necessarily enable the workaround,
407 as it depends on the alternative framework, which will only patch
408 the kernel if an affected CPU is detected.
417 default ARM64_4K_PAGES
419 Page size (translation granule) configuration.
421 config ARM64_4K_PAGES
424 This feature enables 4KB pages support.
426 config ARM64_64K_PAGES
429 This feature enables 64KB pages support (4KB by default)
430 allowing only two levels of page tables and faster TLB
431 look-up. AArch32 emulation is not available when this feature
437 prompt "Virtual address space size"
438 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
439 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
441 Allows choosing one of multiple possible virtual address
442 space sizes. The level of translation table is determined by
443 a combination of page size and virtual address space size.
445 config ARM64_VA_BITS_39
447 depends on ARM64_4K_PAGES
449 config ARM64_VA_BITS_42
451 depends on ARM64_64K_PAGES
453 config ARM64_VA_BITS_48
460 default 39 if ARM64_VA_BITS_39
461 default 42 if ARM64_VA_BITS_42
462 default 48 if ARM64_VA_BITS_48
464 config CPU_BIG_ENDIAN
465 bool "Build big-endian kernel"
467 Say Y if you plan on running a kernel in big-endian mode.
470 bool "Symmetric Multi-Processing"
472 This enables support for systems with more than one CPU. If
473 you say N here, the kernel will run on single and
474 multiprocessor machines, but will use only one CPU of a
475 multiprocessor machine. If you say Y here, the kernel will run
476 on many, but not all, single processor machines. On a single
477 processor machine, the kernel will run faster if you say N
480 If you don't know what to do here, say N.
483 bool "Multi-core scheduler support"
486 Multi-core scheduler support improves the CPU scheduler's decision
487 making when dealing with multi-core CPU chips at a cost of slightly
488 increased overhead in some places. If unsure say N here.
491 bool "SMT scheduler support"
494 Improves the CPU scheduler's decision making when dealing with
495 MultiThreading at a cost of slightly increased overhead in some
496 places. If unsure say N here.
499 int "Maximum number of CPUs (2-4096)"
502 # These have to remain sorted largest to smallest
506 bool "Support for hot-pluggable CPUs"
509 Say Y here to experiment with turning CPUs off and on. CPUs
510 can be controlled through /sys/devices/system/cpu.
512 source kernel/Kconfig.preempt
522 config ARCH_HAS_HOLES_MEMORYMODEL
523 def_bool y if SPARSEMEM
525 config ARCH_SPARSEMEM_ENABLE
527 select SPARSEMEM_VMEMMAP_ENABLE
529 config ARCH_SPARSEMEM_DEFAULT
530 def_bool ARCH_SPARSEMEM_ENABLE
532 config ARCH_SELECT_MEMORY_MODEL
533 def_bool ARCH_SPARSEMEM_ENABLE
535 config HAVE_ARCH_PFN_VALID
536 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
538 config HW_PERF_EVENTS
539 bool "Enable hardware performance counter support for perf events"
540 depends on PERF_EVENTS
543 Enable hardware performance counter support for perf events. If
544 disabled, perf events will use software events only.
546 config SYS_SUPPORTS_HUGETLBFS
549 config ARCH_WANT_GENERAL_HUGETLB
552 config ARCH_WANT_HUGE_PMD_SHARE
553 def_bool y if !ARM64_64K_PAGES
555 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
558 config ARCH_HAS_CACHE_LINE_SIZE
564 bool "Enable seccomp to safely compute untrusted bytecode"
566 This kernel feature is useful for number crunching applications
567 that may need to compute untrusted bytecode during their
568 execution. By using pipes or other transports made available to
569 the process as file descriptors supporting the read/write
570 syscalls, it's possible to isolate those applications in
571 their own address space using seccomp. Once seccomp is
572 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
573 and the task is only allowed to execute a few safe syscalls
574 defined by each seccomp mode.
581 bool "Xen guest support on ARM64"
582 depends on ARM64 && OF
585 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
587 config FORCE_MAX_ZONEORDER
589 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
592 menuconfig ARMV8_DEPRECATED
593 bool "Emulate deprecated/obsolete ARMv8 instructions"
596 Legacy software support may require certain instructions
597 that have been deprecated or obsoleted in the architecture.
599 Enable this config to enable selective emulation of these
607 bool "Emulate SWP/SWPB instructions"
609 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
610 they are always undefined. Say Y here to enable software
611 emulation of these instructions for userspace using LDXR/STXR.
613 In some older versions of glibc [<=2.8] SWP is used during futex
614 trylock() operations with the assumption that the code will not
615 be preempted. This invalid assumption may be more likely to fail
616 with SWP emulation enabled, leading to deadlock of the user
619 NOTE: when accessing uncached shared regions, LDXR/STXR rely
620 on an external transaction monitoring block called a global
621 monitor to maintain update atomicity. If your system does not
622 implement a global monitor, this option can cause programs that
623 perform SWP operations to uncached memory to deadlock.
627 config CP15_BARRIER_EMULATION
628 bool "Emulate CP15 Barrier instructions"
630 The CP15 barrier instructions - CP15ISB, CP15DSB, and
631 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
632 strongly recommended to use the ISB, DSB, and DMB
633 instructions instead.
635 Say Y here to enable software emulation of these
636 instructions for AArch32 userspace code. When this option is
637 enabled, CP15 barrier usage is traced which can help
638 identify software that needs updating.
642 config SETEND_EMULATION
643 bool "Emulate SETEND instruction"
645 The SETEND instruction alters the data-endianness of the
646 AArch32 EL0, and is deprecated in ARMv8.
648 Say Y here to enable software emulation of the instruction
649 for AArch32 userspace code.
651 Note: All the cpus on the system must have mixed endian support at EL0
652 for this feature to be enabled. If a new CPU - which doesn't support mixed
653 endian - is hotplugged in after this feature has been enabled, there could
654 be unexpected results in the applications.
664 string "Default kernel command string"
667 Provide a set of default command-line options at build time by
668 entering them here. As a minimum, you should specify the the
669 root device (e.g. root=/dev/nfs).
672 bool "Always use the default kernel command string"
674 Always use the default kernel command string, even if the boot
675 loader passes other arguments to the kernel.
676 This is useful if you cannot or don't want to change the
677 command-line options your boot loader passes to the kernel.
683 bool "UEFI runtime support"
684 depends on OF && !CPU_BIG_ENDIAN
687 select EFI_PARAMS_FROM_FDT
688 select EFI_RUNTIME_WRAPPERS
693 This option provides support for runtime services provided
694 by UEFI firmware (such as non-volatile variables, realtime
695 clock, and platform reset). A UEFI stub is also provided to
696 allow the kernel to be booted as an EFI application. This
697 is only useful on systems that have UEFI firmware.
700 bool "Enable support for SMBIOS (DMI) tables"
704 This enables SMBIOS/DMI feature for systems.
706 This option is only useful on systems that have UEFI firmware.
707 However, even with this option, the resultant kernel should
708 continue to boot on existing non-UEFI platforms.
712 menu "Userspace binary formats"
714 source "fs/Kconfig.binfmt"
717 bool "Kernel support for 32-bit EL0"
718 depends on !ARM64_64K_PAGES || EXPERT
719 select COMPAT_BINFMT_ELF
721 select OLD_SIGSUSPEND3
722 select COMPAT_OLD_SIGACTION
724 This option enables support for a 32-bit EL0 running under a 64-bit
725 kernel at EL1. AArch32-specific components such as system calls,
726 the user helper functions, VFP support and the ptrace interface are
727 handled appropriately by the kernel.
729 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
730 will only be able to execute AArch32 binaries that were compiled with
731 64k aligned segments.
733 If you want to execute 32-bit userspace applications, say Y.
735 config SYSVIPC_COMPAT
737 depends on COMPAT && SYSVIPC
741 menu "Power management options"
743 source "kernel/power/Kconfig"
745 config ARCH_SUSPEND_POSSIBLE
750 menu "CPU Power Management"
752 source "drivers/cpuidle/Kconfig"
754 source "drivers/cpufreq/Kconfig"
760 source "drivers/Kconfig"
762 source "drivers/firmware/Kconfig"
764 source "drivers/acpi/Kconfig"
768 source "arch/arm64/kvm/Kconfig"
770 source "arch/arm64/Kconfig.debug"
772 source "security/Kconfig"
774 source "crypto/Kconfig"
776 source "arch/arm64/crypto/Kconfig"