3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HARDENED_USERCOPY
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_MMAP_RND_BITS
58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
59 select HAVE_ARCH_SECCOMP_FILTER
60 select HAVE_ARCH_TRACEHOOK
62 select HAVE_C_RECORDMCOUNT
63 select HAVE_CC_STACKPROTECTOR
64 select HAVE_CMPXCHG_DOUBLE
65 select HAVE_CMPXCHG_LOCAL
66 select HAVE_DEBUG_BUGVERBOSE
67 select HAVE_DEBUG_KMEMLEAK
68 select HAVE_DMA_API_DEBUG
70 select HAVE_DMA_CONTIGUOUS
71 select HAVE_DYNAMIC_FTRACE
72 select HAVE_EFFICIENT_UNALIGNED_ACCESS
73 select HAVE_FTRACE_MCOUNT_RECORD
74 select HAVE_FUNCTION_TRACER
75 select HAVE_FUNCTION_GRAPH_TRACER
76 select HAVE_GENERIC_DMA_COHERENT
77 select HAVE_HW_BREAKPOINT if PERF_EVENTS
78 select HAVE_IRQ_TIME_ACCOUNTING
80 select HAVE_PATA_PLATFORM
81 select HAVE_PERF_EVENTS
83 select HAVE_PERF_USER_STACK_DUMP
84 select HAVE_REGS_AND_STACK_ACCESS_API
85 select HAVE_RCU_TABLE_FREE
86 select HAVE_SYSCALL_TRACEPOINTS
88 select HAVE_KRETPROBES if HAVE_KPROBES
89 select IOMMU_DMA if IOMMU_SUPPORT
91 select IRQ_FORCED_THREADING
92 select MODULES_USE_ELF_RELA
95 select OF_EARLY_FLATTREE
96 select OF_RESERVED_MEM
97 select PERF_USE_VMALLOC
102 select SYSCTL_EXCEPTION_TRACE
103 select HAVE_CONTEXT_TRACKING
105 ARM 64-bit (AArch64) Linux support.
110 config ARCH_PHYS_ADDR_T_64BIT
116 config ARCH_MMAP_RND_BITS_MIN
117 default 14 if ARM64_64K_PAGES
118 default 16 if ARM64_16K_PAGES
121 # max bits determined by the following formula:
122 # VA_BITS - PAGE_SHIFT - 3
123 config ARCH_MMAP_RND_BITS_MAX
124 default 19 if ARM64_VA_BITS=36
125 default 24 if ARM64_VA_BITS=39
126 default 27 if ARM64_VA_BITS=42
127 default 30 if ARM64_VA_BITS=47
128 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
129 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
130 default 33 if ARM64_VA_BITS=48
131 default 14 if ARM64_64K_PAGES
132 default 16 if ARM64_16K_PAGES
135 config ARCH_MMAP_RND_COMPAT_BITS_MIN
136 default 7 if ARM64_64K_PAGES
137 default 9 if ARM64_16K_PAGES
140 config ARCH_MMAP_RND_COMPAT_BITS_MAX
146 config ILLEGAL_POINTER_VALUE
148 default 0xdead000000000000
150 config STACKTRACE_SUPPORT
153 config ILLEGAL_POINTER_VALUE
155 default 0xdead000000000000
157 config LOCKDEP_SUPPORT
160 config TRACE_IRQFLAGS_SUPPORT
163 config RWSEM_XCHGADD_ALGORITHM
170 config GENERIC_BUG_RELATIVE_POINTERS
172 depends on GENERIC_BUG
174 config GENERIC_HWEIGHT
180 config GENERIC_CALIBRATE_DELAY
186 config HAVE_GENERIC_RCU_GUP
189 config ARCH_DMA_ADDR_T_64BIT
192 config NEED_DMA_MAP_STATE
195 config NEED_SG_DMA_LENGTH
207 config KERNEL_MODE_NEON
210 config FIX_EARLYCON_MEM
213 config PGTABLE_LEVELS
215 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
216 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
217 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
218 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
219 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
220 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
222 source "init/Kconfig"
224 source "kernel/Kconfig.freezer"
226 source "arch/arm64/Kconfig.platforms"
233 This feature enables support for PCI bus system. If you say Y
234 here, the kernel will include drivers and infrastructure code
235 to support PCI bus devices.
240 config PCI_DOMAINS_GENERIC
246 source "drivers/pci/Kconfig"
247 source "drivers/pci/pcie/Kconfig"
248 source "drivers/pci/hotplug/Kconfig"
252 menu "Kernel Features"
254 menu "ARM errata workarounds via the alternatives framework"
256 config ARM64_ERRATUM_826319
257 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
260 This option adds an alternative code sequence to work around ARM
261 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
262 AXI master interface and an L2 cache.
264 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
265 and is unable to accept a certain write via this interface, it will
266 not progress on read data presented on the read data channel and the
269 The workaround promotes data cache clean instructions to
270 data cache clean-and-invalidate.
271 Please note that this does not necessarily enable the workaround,
272 as it depends on the alternative framework, which will only patch
273 the kernel if an affected CPU is detected.
277 config ARM64_ERRATUM_827319
278 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
281 This option adds an alternative code sequence to work around ARM
282 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
283 master interface and an L2 cache.
285 Under certain conditions this erratum can cause a clean line eviction
286 to occur at the same time as another transaction to the same address
287 on the AMBA 5 CHI interface, which can cause data corruption if the
288 interconnect reorders the two transactions.
290 The workaround promotes data cache clean instructions to
291 data cache clean-and-invalidate.
292 Please note that this does not necessarily enable the workaround,
293 as it depends on the alternative framework, which will only patch
294 the kernel if an affected CPU is detected.
298 config ARM64_ERRATUM_824069
299 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
302 This option adds an alternative code sequence to work around ARM
303 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
304 to a coherent interconnect.
306 If a Cortex-A53 processor is executing a store or prefetch for
307 write instruction at the same time as a processor in another
308 cluster is executing a cache maintenance operation to the same
309 address, then this erratum might cause a clean cache line to be
310 incorrectly marked as dirty.
312 The workaround promotes data cache clean instructions to
313 data cache clean-and-invalidate.
314 Please note that this option does not necessarily enable the
315 workaround, as it depends on the alternative framework, which will
316 only patch the kernel if an affected CPU is detected.
320 config ARM64_ERRATUM_819472
321 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
324 This option adds an alternative code sequence to work around ARM
325 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
326 present when it is connected to a coherent interconnect.
328 If the processor is executing a load and store exclusive sequence at
329 the same time as a processor in another cluster is executing a cache
330 maintenance operation to the same address, then this erratum might
331 cause data corruption.
333 The workaround promotes data cache clean instructions to
334 data cache clean-and-invalidate.
335 Please note that this does not necessarily enable the workaround,
336 as it depends on the alternative framework, which will only patch
337 the kernel if an affected CPU is detected.
341 config ARM64_ERRATUM_832075
342 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
345 This option adds an alternative code sequence to work around ARM
346 erratum 832075 on Cortex-A57 parts up to r1p2.
348 Affected Cortex-A57 parts might deadlock when exclusive load/store
349 instructions to Write-Back memory are mixed with Device loads.
351 The workaround is to promote device loads to use Load-Acquire
353 Please note that this does not necessarily enable the workaround,
354 as it depends on the alternative framework, which will only patch
355 the kernel if an affected CPU is detected.
359 config ARM64_ERRATUM_834220
360 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
364 This option adds an alternative code sequence to work around ARM
365 erratum 834220 on Cortex-A57 parts up to r1p2.
367 Affected Cortex-A57 parts might report a Stage 2 translation
368 fault as the result of a Stage 1 fault for load crossing a
369 page boundary when there is a permission or device memory
370 alignment fault at Stage 1 and a translation fault at Stage 2.
372 The workaround is to verify that the Stage 1 translation
373 doesn't generate a fault before handling the Stage 2 fault.
374 Please note that this does not necessarily enable the workaround,
375 as it depends on the alternative framework, which will only patch
376 the kernel if an affected CPU is detected.
380 config ARM64_ERRATUM_845719
381 bool "Cortex-A53: 845719: a load might read incorrect data"
385 This option adds an alternative code sequence to work around ARM
386 erratum 845719 on Cortex-A53 parts up to r0p4.
388 When running a compat (AArch32) userspace on an affected Cortex-A53
389 part, a load at EL0 from a virtual address that matches the bottom 32
390 bits of the virtual address used by a recent load at (AArch64) EL1
391 might return incorrect data.
393 The workaround is to write the contextidr_el1 register on exception
394 return to a 32-bit task.
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
401 config ARM64_ERRATUM_843419
402 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
405 select ARM64_MODULE_CMODEL_LARGE
407 This option builds kernel modules using the large memory model in
408 order to avoid the use of the ADRP instruction, which can cause
409 a subsequent memory access to use an incorrect address on Cortex-A53
412 Note that the kernel itself must be linked with a version of ld
413 which fixes potentially affected ADRP instructions through the
418 config CAVIUM_ERRATUM_22375
419 bool "Cavium erratum 22375, 24313"
422 Enable workaround for erratum 22375, 24313.
424 This implements two gicv3-its errata workarounds for ThunderX. Both
425 with small impact affecting only ITS table allocation.
427 erratum 22375: only alloc 8MB table size
428 erratum 24313: ignore memory access type
430 The fixes are in ITS initialization and basically ignore memory access
431 type and table size provided by the TYPER and BASER registers.
435 config CAVIUM_ERRATUM_23144
436 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
440 ITS SYNC command hang for cross node io and collections/cpu mapping.
444 config CAVIUM_ERRATUM_23154
445 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
448 The gicv3 of ThunderX requires a modified version for
449 reading the IAR status to ensure data synchronization
450 (access to icc_iar1_el1 is not sync'ed before and after).
454 config CAVIUM_ERRATUM_27456
455 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
458 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
459 instructions may cause the icache to become corrupted if it
460 contains data for a non-current ASID. The fix is to
461 invalidate the icache when changing the mm context.
470 default ARM64_4K_PAGES
472 Page size (translation granule) configuration.
474 config ARM64_4K_PAGES
477 This feature enables 4KB pages support.
479 config ARM64_16K_PAGES
482 The system will use 16KB pages support. AArch32 emulation
483 requires applications compiled with 16K (or a multiple of 16K)
486 config ARM64_64K_PAGES
489 This feature enables 64KB pages support (4KB by default)
490 allowing only two levels of page tables and faster TLB
491 look-up. AArch32 emulation requires applications compiled
492 with 64K aligned segments.
497 prompt "Virtual address space size"
498 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
499 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
500 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
502 Allows choosing one of multiple possible virtual address
503 space sizes. The level of translation table is determined by
504 a combination of page size and virtual address space size.
506 config ARM64_VA_BITS_36
507 bool "36-bit" if EXPERT
508 depends on ARM64_16K_PAGES
510 config ARM64_VA_BITS_39
512 depends on ARM64_4K_PAGES
514 config ARM64_VA_BITS_42
516 depends on ARM64_64K_PAGES
518 config ARM64_VA_BITS_47
520 depends on ARM64_16K_PAGES
522 config ARM64_VA_BITS_48
529 default 36 if ARM64_VA_BITS_36
530 default 39 if ARM64_VA_BITS_39
531 default 42 if ARM64_VA_BITS_42
532 default 47 if ARM64_VA_BITS_47
533 default 48 if ARM64_VA_BITS_48
535 config CPU_BIG_ENDIAN
536 bool "Build big-endian kernel"
538 Say Y if you plan on running a kernel in big-endian mode.
541 bool "Multi-core scheduler support"
543 Multi-core scheduler support improves the CPU scheduler's decision
544 making when dealing with multi-core CPU chips at a cost of slightly
545 increased overhead in some places. If unsure say N here.
548 bool "SMT scheduler support"
550 Improves the CPU scheduler's decision making when dealing with
551 MultiThreading at a cost of slightly increased overhead in some
552 places. If unsure say N here.
555 int "Maximum number of CPUs (2-4096)"
557 # These have to remain sorted largest to smallest
561 bool "Support for hot-pluggable CPUs"
562 select GENERIC_IRQ_MIGRATION
564 Say Y here to experiment with turning CPUs off and on. CPUs
565 can be controlled through /sys/devices/system/cpu.
567 source kernel/Kconfig.preempt
568 source kernel/Kconfig.hz
570 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
573 config ARCH_HAS_HOLES_MEMORYMODEL
574 def_bool y if SPARSEMEM
576 config ARCH_SPARSEMEM_ENABLE
578 select SPARSEMEM_VMEMMAP_ENABLE
580 config ARCH_SPARSEMEM_DEFAULT
581 def_bool ARCH_SPARSEMEM_ENABLE
583 config ARCH_SELECT_MEMORY_MODEL
584 def_bool ARCH_SPARSEMEM_ENABLE
586 config HAVE_ARCH_PFN_VALID
587 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
589 config HW_PERF_EVENTS
593 config SYS_SUPPORTS_HUGETLBFS
596 config ARCH_WANT_HUGE_PMD_SHARE
597 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
599 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
602 config ARCH_HAS_CACHE_LINE_SIZE
608 bool "Enable seccomp to safely compute untrusted bytecode"
610 This kernel feature is useful for number crunching applications
611 that may need to compute untrusted bytecode during their
612 execution. By using pipes or other transports made available to
613 the process as file descriptors supporting the read/write
614 syscalls, it's possible to isolate those applications in
615 their own address space using seccomp. Once seccomp is
616 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
617 and the task is only allowed to execute a few safe syscalls
618 defined by each seccomp mode.
625 bool "Xen guest support on ARM64"
626 depends on ARM64 && OF
629 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
631 config FORCE_MAX_ZONEORDER
633 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
634 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
637 The kernel memory allocator divides physically contiguous memory
638 blocks into "zones", where each zone is a power of two number of
639 pages. This option selects the largest power of two that the kernel
640 keeps in the memory allocator. If you need to allocate very large
641 blocks of physically contiguous memory, then you may need to
644 This config option is actually maximum order plus one. For example,
645 a value of 11 means that the largest free memory block is 2^10 pages.
647 We make sure that we can allocate upto a HugePage size for each configuration.
649 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
651 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
652 4M allocations matching the default size used by generic code.
654 menuconfig ARMV8_DEPRECATED
655 bool "Emulate deprecated/obsolete ARMv8 instructions"
658 Legacy software support may require certain instructions
659 that have been deprecated or obsoleted in the architecture.
661 Enable this config to enable selective emulation of these
669 bool "Emulate SWP/SWPB instructions"
671 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
672 they are always undefined. Say Y here to enable software
673 emulation of these instructions for userspace using LDXR/STXR.
675 In some older versions of glibc [<=2.8] SWP is used during futex
676 trylock() operations with the assumption that the code will not
677 be preempted. This invalid assumption may be more likely to fail
678 with SWP emulation enabled, leading to deadlock of the user
681 NOTE: when accessing uncached shared regions, LDXR/STXR rely
682 on an external transaction monitoring block called a global
683 monitor to maintain update atomicity. If your system does not
684 implement a global monitor, this option can cause programs that
685 perform SWP operations to uncached memory to deadlock.
689 config CP15_BARRIER_EMULATION
690 bool "Emulate CP15 Barrier instructions"
692 The CP15 barrier instructions - CP15ISB, CP15DSB, and
693 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
694 strongly recommended to use the ISB, DSB, and DMB
695 instructions instead.
697 Say Y here to enable software emulation of these
698 instructions for AArch32 userspace code. When this option is
699 enabled, CP15 barrier usage is traced which can help
700 identify software that needs updating.
704 config SETEND_EMULATION
705 bool "Emulate SETEND instruction"
707 The SETEND instruction alters the data-endianness of the
708 AArch32 EL0, and is deprecated in ARMv8.
710 Say Y here to enable software emulation of the instruction
711 for AArch32 userspace code.
713 Note: All the cpus on the system must have mixed endian support at EL0
714 for this feature to be enabled. If a new CPU - which doesn't support mixed
715 endian - is hotplugged in after this feature has been enabled, there could
716 be unexpected results in the applications.
721 config ARM64_SW_TTBR0_PAN
722 bool "Emulate Priviledged Access Never using TTBR0_EL1 switching"
724 Enabling this option prevents the kernel from accessing
725 user-space memory directly by pointing TTBR0_EL1 to a reserved
726 zeroed area and reserved ASID. The user access routines
727 restore the valid TTBR0_EL1 temporarily.
729 menu "ARMv8.1 architectural features"
731 config ARM64_HW_AFDBM
732 bool "Support for hardware updates of the Access and Dirty page flags"
735 The ARMv8.1 architecture extensions introduce support for
736 hardware updates of the access and dirty information in page
737 table entries. When enabled in TCR_EL1 (HA and HD bits) on
738 capable processors, accesses to pages with PTE_AF cleared will
739 set this bit instead of raising an access flag fault.
740 Similarly, writes to read-only pages with the DBM bit set will
741 clear the read-only bit (AP[2]) instead of raising a
744 Kernels built with this configuration option enabled continue
745 to work on pre-ARMv8.1 hardware and the performance impact is
746 minimal. If unsure, say Y.
749 bool "Enable support for Privileged Access Never (PAN)"
752 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
753 prevents the kernel or hypervisor from accessing user-space (EL0)
756 Choosing this option will cause any unprotected (not using
757 copy_to_user et al) memory access to fail with a permission fault.
759 The feature is detected at runtime, and will remain as a 'nop'
760 instruction if the cpu does not implement the feature.
762 config ARM64_LSE_ATOMICS
763 bool "Atomic instructions"
765 As part of the Large System Extensions, ARMv8.1 introduces new
766 atomic instructions that are designed specifically to scale in
769 Say Y here to make use of these instructions for the in-kernel
770 atomic routines. This incurs a small overhead on CPUs that do
771 not support these instructions and requires the kernel to be
772 built with binutils >= 2.25.
777 bool "Enable support for User Access Override (UAO)"
780 User Access Override (UAO; part of the ARMv8.2 Extensions)
781 causes the 'unprivileged' variant of the load/store instructions to
782 be overriden to be privileged.
784 This option changes get_user() and friends to use the 'unprivileged'
785 variant of the load/store instructions. This ensures that user-space
786 really did have access to the supplied memory. When addr_limit is
787 set to kernel memory the UAO bit will be set, allowing privileged
788 access to kernel memory.
790 Choosing this option will cause copy_to_user() et al to use user-space
793 The feature is detected at runtime, the kernel will use the
794 regular load/store instructions if the cpu does not implement the
797 config ARM64_MODULE_CMODEL_LARGE
800 config ARM64_MODULE_PLTS
802 select ARM64_MODULE_CMODEL_LARGE
803 select HAVE_MOD_ARCH_SPECIFIC
808 This builds the kernel as a Position Independent Executable (PIE),
809 which retains all relocation metadata required to relocate the
810 kernel binary at runtime to a different virtual address than the
811 address it was linked at.
812 Since AArch64 uses the RELA relocation format, this requires a
813 relocation pass at runtime even if the kernel is loaded at the
814 same address it was linked at.
816 config RANDOMIZE_BASE
817 bool "Randomize the address of the kernel image"
818 select ARM64_MODULE_PLTS if MODULES
821 Randomizes the virtual address at which the kernel image is
822 loaded, as a security feature that deters exploit attempts
823 relying on knowledge of the location of kernel internals.
825 It is the bootloader's job to provide entropy, by passing a
826 random u64 value in /chosen/kaslr-seed at kernel entry.
828 When booting via the UEFI stub, it will invoke the firmware's
829 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
830 to the kernel proper. In addition, it will randomise the physical
831 location of the kernel Image as well.
835 config RANDOMIZE_MODULE_REGION_FULL
836 bool "Randomize the module region independently from the core kernel"
837 depends on RANDOMIZE_BASE
840 Randomizes the location of the module region without considering the
841 location of the core kernel. This way, it is impossible for modules
842 to leak information about the location of core kernel data structures
843 but it does imply that function calls between modules and the core
844 kernel will need to be resolved via veneers in the module PLT.
846 When this option is not set, the module region will be randomized over
847 a limited range that contains the [_stext, _etext] interval of the
848 core kernel, so branch relocations are always in range.
854 config ARM64_ACPI_PARKING_PROTOCOL
855 bool "Enable support for the ARM64 ACPI parking protocol"
858 Enable support for the ARM64 ACPI parking protocol. If disabled
859 the kernel will not allow booting through the ARM64 ACPI parking
860 protocol even if the corresponding data is present in the ACPI
864 string "Default kernel command string"
867 Provide a set of default command-line options at build time by
868 entering them here. As a minimum, you should specify the the
869 root device (e.g. root=/dev/nfs).
872 prompt "Kernel command line type" if CMDLINE != ""
873 default CMDLINE_FROM_BOOTLOADER
875 config CMDLINE_FROM_BOOTLOADER
876 bool "Use bootloader kernel arguments if available"
878 Uses the command-line options passed by the boot loader. If
879 the boot loader doesn't provide any, the default kernel command
880 string provided in CMDLINE will be used.
882 config CMDLINE_EXTEND
883 bool "Extend bootloader kernel arguments"
885 The command-line arguments provided by the boot loader will be
886 appended to the default kernel command string.
889 bool "Always use the default kernel command string"
891 Always use the default kernel command string, even if the boot
892 loader passes other arguments to the kernel.
893 This is useful if you cannot or don't want to change the
894 command-line options your boot loader passes to the kernel.
901 bool "UEFI runtime support"
902 depends on OF && !CPU_BIG_ENDIAN
905 select EFI_PARAMS_FROM_FDT
906 select EFI_RUNTIME_WRAPPERS
911 This option provides support for runtime services provided
912 by UEFI firmware (such as non-volatile variables, realtime
913 clock, and platform reset). A UEFI stub is also provided to
914 allow the kernel to be booted as an EFI application. This
915 is only useful on systems that have UEFI firmware.
918 bool "Enable support for SMBIOS (DMI) tables"
922 This enables SMBIOS/DMI feature for systems.
924 This option is only useful on systems that have UEFI firmware.
925 However, even with this option, the resultant kernel should
926 continue to boot on existing non-UEFI platforms.
928 config BUILD_ARM64_APPENDED_DTB_IMAGE
929 bool "Build a concatenated Image.gz/dtb by default"
932 Enabling this option will cause a concatenated Image.gz and list of
933 DTBs to be built by default (instead of a standalone Image.gz.)
934 The image will built in arch/arm64/boot/Image.gz-dtb
936 config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
937 string "Default dtb names"
938 depends on BUILD_ARM64_APPENDED_DTB_IMAGE
940 Space separated list of names of dtbs to append when
941 building a concatenated Image.gz-dtb.
945 menu "Userspace binary formats"
947 source "fs/Kconfig.binfmt"
950 bool "Kernel support for 32-bit EL0"
951 depends on ARM64_4K_PAGES || EXPERT
952 select COMPAT_BINFMT_ELF
954 select OLD_SIGSUSPEND3
955 select COMPAT_OLD_SIGACTION
957 This option enables support for a 32-bit EL0 running under a 64-bit
958 kernel at EL1. AArch32-specific components such as system calls,
959 the user helper functions, VFP support and the ptrace interface are
960 handled appropriately by the kernel.
962 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
963 that you will only be able to execute AArch32 binaries that were compiled
964 with page size aligned segments.
966 If you want to execute 32-bit userspace applications, say Y.
968 config SYSVIPC_COMPAT
970 depends on COMPAT && SYSVIPC
974 menu "Power management options"
976 source "kernel/power/Kconfig"
978 config ARCH_SUSPEND_POSSIBLE
983 menu "CPU Power Management"
985 source "drivers/cpuidle/Kconfig"
987 source "drivers/cpufreq/Kconfig"
993 source "drivers/Kconfig"
995 source "drivers/firmware/Kconfig"
997 source "drivers/acpi/Kconfig"
1001 source "arch/arm64/kvm/Kconfig"
1003 source "arch/arm64/Kconfig.debug"
1005 source "security/Kconfig"
1007 source "crypto/Kconfig"
1009 source "arch/arm64/crypto/Kconfig"
1012 source "lib/Kconfig"