3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
23 select BUILDTIME_EXTABLE_SORT
24 select CLONE_BACKWARDS
26 select CPU_PM if (SUSPEND || CPU_IDLE)
27 select DCACHE_WORD_ACCESS
29 select GENERIC_ALLOCATOR
30 select GENERIC_CLOCKEVENTS
31 select GENERIC_CLOCKEVENTS_BROADCAST
32 select GENERIC_CPU_AUTOPROBE
33 select GENERIC_EARLY_IOREMAP
34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
36 select GENERIC_IRQ_SHOW_LEVEL
37 select GENERIC_PCI_IOMAP
38 select GENERIC_SCHED_CLOCK
39 select GENERIC_SMP_IDLE_THREAD
40 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
42 select GENERIC_TIME_VSYSCALL
43 select HANDLE_DOMAIN_IRQ
44 select HARDIRQS_SW_RESEND
45 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
46 select HAVE_ARCH_AUDITSYSCALL
47 select HAVE_ARCH_BITREVERSE
48 select HAVE_ARCH_JUMP_LABEL
50 select HAVE_ARCH_SECCOMP_FILTER
51 select HAVE_ARCH_TRACEHOOK
53 select HAVE_C_RECORDMCOUNT
54 select HAVE_CC_STACKPROTECTOR
55 select HAVE_CMPXCHG_DOUBLE
56 select HAVE_DEBUG_BUGVERBOSE
57 select HAVE_DEBUG_KMEMLEAK
58 select HAVE_DMA_API_DEBUG
60 select HAVE_DMA_CONTIGUOUS
61 select HAVE_DYNAMIC_FTRACE
62 select HAVE_EFFICIENT_UNALIGNED_ACCESS
63 select HAVE_FTRACE_MCOUNT_RECORD
64 select HAVE_FUNCTION_TRACER
65 select HAVE_FUNCTION_GRAPH_TRACER
66 select HAVE_GENERIC_DMA_COHERENT
67 select HAVE_HW_BREAKPOINT if PERF_EVENTS
69 select HAVE_PATA_PLATFORM
70 select HAVE_PERF_EVENTS
72 select HAVE_PERF_USER_STACK_DUMP
73 select HAVE_RCU_TABLE_FREE
74 select HAVE_SYSCALL_TRACEPOINTS
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_RELA
80 select OF_EARLY_FLATTREE
81 select OF_RESERVED_MEM
82 select PERF_USE_VMALLOC
87 select SYSCTL_EXCEPTION_TRACE
88 select HAVE_CONTEXT_TRACKING
90 ARM 64-bit (AArch64) Linux support.
95 config ARCH_PHYS_ADDR_T_64BIT
104 config STACKTRACE_SUPPORT
107 config LOCKDEP_SUPPORT
110 config TRACE_IRQFLAGS_SUPPORT
113 config RWSEM_XCHGADD_ALGORITHM
116 config GENERIC_HWEIGHT
122 config GENERIC_CALIBRATE_DELAY
128 config HAVE_GENERIC_RCU_GUP
131 config ARCH_DMA_ADDR_T_64BIT
134 config NEED_DMA_MAP_STATE
137 config NEED_SG_DMA_LENGTH
149 config KERNEL_MODE_NEON
152 config FIX_EARLYCON_MEM
155 config PGTABLE_LEVELS
157 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
158 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
159 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
160 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
162 source "init/Kconfig"
164 source "kernel/Kconfig.freezer"
166 menu "Platform selection"
171 This enables support for Samsung Exynos SoC family
174 bool "ARMv8 based Samsung Exynos7"
176 select COMMON_CLK_SAMSUNG
177 select HAVE_S3C2410_WATCHDOG if WATCHDOG
178 select HAVE_S3C_RTC if RTC_CLASS
180 select PINCTRL_EXYNOS
183 This enables support for Samsung Exynos7 SoC family
185 config ARCH_FSL_LS2085A
186 bool "Freescale LS2085A SOC"
188 This enables support for Freescale LS2085A SOC.
191 bool "Hisilicon SoC Family"
193 This enables support for Hisilicon ARMv8 SoC family
196 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
200 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
203 bool "Qualcomm Platforms"
206 This enables support for the ARMv8 based Qualcomm chipsets.
209 bool "AMD Seattle SoC Family"
211 This enables support for AMD Seattle SOC Family
214 bool "NVIDIA Tegra SoC Family"
215 select ARCH_HAS_RESET_CONTROLLER
216 select ARCH_REQUIRE_GPIOLIB
220 select GENERIC_CLOCKEVENTS
223 select RESET_CONTROLLER
225 This enables support for the NVIDIA Tegra SoC family.
227 config ARCH_TEGRA_132_SOC
228 bool "NVIDIA Tegra132 SoC"
229 depends on ARCH_TEGRA
230 select PINCTRL_TEGRA124
231 select USB_ULPI if USB_PHY
232 select USB_ULPI_VIEWPORT if USB_PHY
234 Enable support for NVIDIA Tegra132 SoC, based on the Denver
235 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
236 but contains an NVIDIA Denver CPU complex in place of
237 Tegra124's "4+1" Cortex-A15 CPU complex.
240 bool "Spreadtrum SoC platform"
242 Support for Spreadtrum ARM based SoCs
245 bool "Cavium Inc. Thunder SoC Family"
247 This enables support for Cavium's Thunder Family of SoCs.
250 bool "ARMv8 software model (Versatile Express)"
251 select ARCH_REQUIRE_GPIOLIB
252 select COMMON_CLK_VERSATILE
253 select POWER_RESET_VEXPRESS
254 select VEXPRESS_CONFIG
256 This enables support for the ARMv8 software model (Versatile
260 bool "AppliedMicro X-Gene SOC Family"
262 This enables support for AppliedMicro X-Gene SOC Family
265 bool "Xilinx ZynqMP Family"
267 This enables support for Xilinx ZynqMP Family
276 This feature enables support for PCI bus system. If you say Y
277 here, the kernel will include drivers and infrastructure code
278 to support PCI bus devices.
283 config PCI_DOMAINS_GENERIC
289 source "drivers/pci/Kconfig"
290 source "drivers/pci/pcie/Kconfig"
291 source "drivers/pci/hotplug/Kconfig"
295 menu "Kernel Features"
297 menu "ARM errata workarounds via the alternatives framework"
299 config ARM64_ERRATUM_826319
300 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
303 This option adds an alternative code sequence to work around ARM
304 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
305 AXI master interface and an L2 cache.
307 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
308 and is unable to accept a certain write via this interface, it will
309 not progress on read data presented on the read data channel and the
312 The workaround promotes data cache clean instructions to
313 data cache clean-and-invalidate.
314 Please note that this does not necessarily enable the workaround,
315 as it depends on the alternative framework, which will only patch
316 the kernel if an affected CPU is detected.
320 config ARM64_ERRATUM_827319
321 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
324 This option adds an alternative code sequence to work around ARM
325 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
326 master interface and an L2 cache.
328 Under certain conditions this erratum can cause a clean line eviction
329 to occur at the same time as another transaction to the same address
330 on the AMBA 5 CHI interface, which can cause data corruption if the
331 interconnect reorders the two transactions.
333 The workaround promotes data cache clean instructions to
334 data cache clean-and-invalidate.
335 Please note that this does not necessarily enable the workaround,
336 as it depends on the alternative framework, which will only patch
337 the kernel if an affected CPU is detected.
341 config ARM64_ERRATUM_824069
342 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
345 This option adds an alternative code sequence to work around ARM
346 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
347 to a coherent interconnect.
349 If a Cortex-A53 processor is executing a store or prefetch for
350 write instruction at the same time as a processor in another
351 cluster is executing a cache maintenance operation to the same
352 address, then this erratum might cause a clean cache line to be
353 incorrectly marked as dirty.
355 The workaround promotes data cache clean instructions to
356 data cache clean-and-invalidate.
357 Please note that this option does not necessarily enable the
358 workaround, as it depends on the alternative framework, which will
359 only patch the kernel if an affected CPU is detected.
363 config ARM64_ERRATUM_819472
364 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
367 This option adds an alternative code sequence to work around ARM
368 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
369 present when it is connected to a coherent interconnect.
371 If the processor is executing a load and store exclusive sequence at
372 the same time as a processor in another cluster is executing a cache
373 maintenance operation to the same address, then this erratum might
374 cause data corruption.
376 The workaround promotes data cache clean instructions to
377 data cache clean-and-invalidate.
378 Please note that this does not necessarily enable the workaround,
379 as it depends on the alternative framework, which will only patch
380 the kernel if an affected CPU is detected.
384 config ARM64_ERRATUM_832075
385 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
388 This option adds an alternative code sequence to work around ARM
389 erratum 832075 on Cortex-A57 parts up to r1p2.
391 Affected Cortex-A57 parts might deadlock when exclusive load/store
392 instructions to Write-Back memory are mixed with Device loads.
394 The workaround is to promote device loads to use Load-Acquire
396 Please note that this does not necessarily enable the workaround,
397 as it depends on the alternative framework, which will only patch
398 the kernel if an affected CPU is detected.
402 config ARM64_ERRATUM_845719
403 bool "Cortex-A53: 845719: a load might read incorrect data"
407 This option adds an alternative code sequence to work around ARM
408 erratum 845719 on Cortex-A53 parts up to r0p4.
410 When running a compat (AArch32) userspace on an affected Cortex-A53
411 part, a load at EL0 from a virtual address that matches the bottom 32
412 bits of the virtual address used by a recent load at (AArch64) EL1
413 might return incorrect data.
415 The workaround is to write the contextidr_el1 register on exception
416 return to a 32-bit task.
417 Please note that this does not necessarily enable the workaround,
418 as it depends on the alternative framework, which will only patch
419 the kernel if an affected CPU is detected.
428 default ARM64_4K_PAGES
430 Page size (translation granule) configuration.
432 config ARM64_4K_PAGES
435 This feature enables 4KB pages support.
437 config ARM64_64K_PAGES
440 This feature enables 64KB pages support (4KB by default)
441 allowing only two levels of page tables and faster TLB
442 look-up. AArch32 emulation is not available when this feature
448 prompt "Virtual address space size"
449 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
450 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
452 Allows choosing one of multiple possible virtual address
453 space sizes. The level of translation table is determined by
454 a combination of page size and virtual address space size.
456 config ARM64_VA_BITS_39
458 depends on ARM64_4K_PAGES
460 config ARM64_VA_BITS_42
462 depends on ARM64_64K_PAGES
464 config ARM64_VA_BITS_48
471 default 39 if ARM64_VA_BITS_39
472 default 42 if ARM64_VA_BITS_42
473 default 48 if ARM64_VA_BITS_48
475 config ARM64_HW_AFDBM
476 bool "Support for hardware updates of the Access and Dirty page flags"
479 The ARMv8.1 architecture extensions introduce support for
480 hardware updates of the access and dirty information in page
481 table entries. When enabled in TCR_EL1 (HA and HD bits) on
482 capable processors, accesses to pages with PTE_AF cleared will
483 set this bit instead of raising an access flag fault.
484 Similarly, writes to read-only pages with the DBM bit set will
485 clear the read-only bit (AP[2]) instead of raising a
488 Kernels built with this configuration option enabled continue
489 to work on pre-ARMv8.1 hardware and the performance impact is
490 minimal. If unsure, say Y.
492 config CPU_BIG_ENDIAN
493 bool "Build big-endian kernel"
495 Say Y if you plan on running a kernel in big-endian mode.
498 bool "Multi-core scheduler support"
500 Multi-core scheduler support improves the CPU scheduler's decision
501 making when dealing with multi-core CPU chips at a cost of slightly
502 increased overhead in some places. If unsure say N here.
505 bool "SMT scheduler support"
507 Improves the CPU scheduler's decision making when dealing with
508 MultiThreading at a cost of slightly increased overhead in some
509 places. If unsure say N here.
512 int "Maximum number of CPUs (2-4096)"
514 # These have to remain sorted largest to smallest
518 bool "Support for hot-pluggable CPUs"
520 Say Y here to experiment with turning CPUs off and on. CPUs
521 can be controlled through /sys/devices/system/cpu.
523 source kernel/Kconfig.preempt
529 config ARCH_HAS_HOLES_MEMORYMODEL
530 def_bool y if SPARSEMEM
532 config ARCH_SPARSEMEM_ENABLE
534 select SPARSEMEM_VMEMMAP_ENABLE
536 config ARCH_SPARSEMEM_DEFAULT
537 def_bool ARCH_SPARSEMEM_ENABLE
539 config ARCH_SELECT_MEMORY_MODEL
540 def_bool ARCH_SPARSEMEM_ENABLE
542 config HAVE_ARCH_PFN_VALID
543 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
545 config HW_PERF_EVENTS
546 bool "Enable hardware performance counter support for perf events"
547 depends on PERF_EVENTS
550 Enable hardware performance counter support for perf events. If
551 disabled, perf events will use software events only.
553 config SYS_SUPPORTS_HUGETLBFS
556 config ARCH_WANT_GENERAL_HUGETLB
559 config ARCH_WANT_HUGE_PMD_SHARE
560 def_bool y if !ARM64_64K_PAGES
562 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
565 config ARCH_HAS_CACHE_LINE_SIZE
571 bool "Enable seccomp to safely compute untrusted bytecode"
573 This kernel feature is useful for number crunching applications
574 that may need to compute untrusted bytecode during their
575 execution. By using pipes or other transports made available to
576 the process as file descriptors supporting the read/write
577 syscalls, it's possible to isolate those applications in
578 their own address space using seccomp. Once seccomp is
579 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
580 and the task is only allowed to execute a few safe syscalls
581 defined by each seccomp mode.
588 bool "Xen guest support on ARM64"
589 depends on ARM64 && OF
592 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
594 config FORCE_MAX_ZONEORDER
596 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
599 menuconfig ARMV8_DEPRECATED
600 bool "Emulate deprecated/obsolete ARMv8 instructions"
603 Legacy software support may require certain instructions
604 that have been deprecated or obsoleted in the architecture.
606 Enable this config to enable selective emulation of these
614 bool "Emulate SWP/SWPB instructions"
616 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
617 they are always undefined. Say Y here to enable software
618 emulation of these instructions for userspace using LDXR/STXR.
620 In some older versions of glibc [<=2.8] SWP is used during futex
621 trylock() operations with the assumption that the code will not
622 be preempted. This invalid assumption may be more likely to fail
623 with SWP emulation enabled, leading to deadlock of the user
626 NOTE: when accessing uncached shared regions, LDXR/STXR rely
627 on an external transaction monitoring block called a global
628 monitor to maintain update atomicity. If your system does not
629 implement a global monitor, this option can cause programs that
630 perform SWP operations to uncached memory to deadlock.
634 config CP15_BARRIER_EMULATION
635 bool "Emulate CP15 Barrier instructions"
637 The CP15 barrier instructions - CP15ISB, CP15DSB, and
638 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
639 strongly recommended to use the ISB, DSB, and DMB
640 instructions instead.
642 Say Y here to enable software emulation of these
643 instructions for AArch32 userspace code. When this option is
644 enabled, CP15 barrier usage is traced which can help
645 identify software that needs updating.
649 config SETEND_EMULATION
650 bool "Emulate SETEND instruction"
652 The SETEND instruction alters the data-endianness of the
653 AArch32 EL0, and is deprecated in ARMv8.
655 Say Y here to enable software emulation of the instruction
656 for AArch32 userspace code.
658 Note: All the cpus on the system must have mixed endian support at EL0
659 for this feature to be enabled. If a new CPU - which doesn't support mixed
660 endian - is hotplugged in after this feature has been enabled, there could
661 be unexpected results in the applications.
671 string "Default kernel command string"
674 Provide a set of default command-line options at build time by
675 entering them here. As a minimum, you should specify the the
676 root device (e.g. root=/dev/nfs).
679 bool "Always use the default kernel command string"
681 Always use the default kernel command string, even if the boot
682 loader passes other arguments to the kernel.
683 This is useful if you cannot or don't want to change the
684 command-line options your boot loader passes to the kernel.
690 bool "UEFI runtime support"
691 depends on OF && !CPU_BIG_ENDIAN
694 select EFI_PARAMS_FROM_FDT
695 select EFI_RUNTIME_WRAPPERS
700 This option provides support for runtime services provided
701 by UEFI firmware (such as non-volatile variables, realtime
702 clock, and platform reset). A UEFI stub is also provided to
703 allow the kernel to be booted as an EFI application. This
704 is only useful on systems that have UEFI firmware.
707 bool "Enable support for SMBIOS (DMI) tables"
711 This enables SMBIOS/DMI feature for systems.
713 This option is only useful on systems that have UEFI firmware.
714 However, even with this option, the resultant kernel should
715 continue to boot on existing non-UEFI platforms.
719 menu "Userspace binary formats"
721 source "fs/Kconfig.binfmt"
724 bool "Kernel support for 32-bit EL0"
725 depends on !ARM64_64K_PAGES || EXPERT
726 select COMPAT_BINFMT_ELF
728 select OLD_SIGSUSPEND3
729 select COMPAT_OLD_SIGACTION
731 This option enables support for a 32-bit EL0 running under a 64-bit
732 kernel at EL1. AArch32-specific components such as system calls,
733 the user helper functions, VFP support and the ptrace interface are
734 handled appropriately by the kernel.
736 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
737 will only be able to execute AArch32 binaries that were compiled with
738 64k aligned segments.
740 If you want to execute 32-bit userspace applications, say Y.
742 config SYSVIPC_COMPAT
744 depends on COMPAT && SYSVIPC
748 menu "Power management options"
750 source "kernel/power/Kconfig"
752 config ARCH_SUSPEND_POSSIBLE
757 menu "CPU Power Management"
759 source "drivers/cpuidle/Kconfig"
761 source "drivers/cpufreq/Kconfig"
767 source "drivers/Kconfig"
769 source "drivers/firmware/Kconfig"
771 source "drivers/acpi/Kconfig"
775 source "arch/arm64/kvm/Kconfig"
777 source "arch/arm64/Kconfig.debug"
779 source "security/Kconfig"
781 source "crypto/Kconfig"
783 source "arch/arm64/crypto/Kconfig"