3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HARDENED_USERCOPY
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_MMAP_RND_BITS
58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
59 select HAVE_ARCH_SECCOMP_FILTER
60 select HAVE_ARCH_TRACEHOOK
62 select HAVE_C_RECORDMCOUNT
63 select HAVE_CC_STACKPROTECTOR
64 select HAVE_CMPXCHG_DOUBLE
65 select HAVE_CMPXCHG_LOCAL
66 select HAVE_DEBUG_BUGVERBOSE
67 select HAVE_DEBUG_KMEMLEAK
68 select HAVE_DMA_API_DEBUG
70 select HAVE_DMA_CONTIGUOUS
71 select HAVE_DYNAMIC_FTRACE
72 select HAVE_EFFICIENT_UNALIGNED_ACCESS
73 select HAVE_FTRACE_MCOUNT_RECORD
74 select HAVE_FUNCTION_TRACER
75 select HAVE_FUNCTION_GRAPH_TRACER
76 select HAVE_GENERIC_DMA_COHERENT
77 select HAVE_HW_BREAKPOINT if PERF_EVENTS
78 select HAVE_IRQ_TIME_ACCOUNTING
80 select HAVE_PATA_PLATFORM
81 select HAVE_PERF_EVENTS
83 select HAVE_PERF_USER_STACK_DUMP
84 select HAVE_REGS_AND_STACK_ACCESS_API
85 select HAVE_RCU_TABLE_FREE
86 select HAVE_SYSCALL_TRACEPOINTS
88 select HAVE_KRETPROBES if HAVE_KPROBES
89 select IOMMU_DMA if IOMMU_SUPPORT
91 select IRQ_FORCED_THREADING
92 select MODULES_USE_ELF_RELA
95 select OF_EARLY_FLATTREE
96 select OF_RESERVED_MEM
97 select PERF_USE_VMALLOC
102 select SYSCTL_EXCEPTION_TRACE
103 select HAVE_CONTEXT_TRACKING
104 select HAVE_ARM_SMCCC
106 ARM 64-bit (AArch64) Linux support.
111 config ARCH_PHYS_ADDR_T_64BIT
117 config ARCH_MMAP_RND_BITS_MIN
118 default 14 if ARM64_64K_PAGES
119 default 16 if ARM64_16K_PAGES
122 # max bits determined by the following formula:
123 # VA_BITS - PAGE_SHIFT - 3
124 config ARCH_MMAP_RND_BITS_MAX
125 default 19 if ARM64_VA_BITS=36
126 default 24 if ARM64_VA_BITS=39
127 default 27 if ARM64_VA_BITS=42
128 default 30 if ARM64_VA_BITS=47
129 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
130 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
131 default 33 if ARM64_VA_BITS=48
132 default 14 if ARM64_64K_PAGES
133 default 16 if ARM64_16K_PAGES
136 config ARCH_MMAP_RND_COMPAT_BITS_MIN
137 default 7 if ARM64_64K_PAGES
138 default 9 if ARM64_16K_PAGES
141 config ARCH_MMAP_RND_COMPAT_BITS_MAX
147 config ILLEGAL_POINTER_VALUE
149 default 0xdead000000000000
151 config STACKTRACE_SUPPORT
154 config ILLEGAL_POINTER_VALUE
156 default 0xdead000000000000
158 config LOCKDEP_SUPPORT
161 config TRACE_IRQFLAGS_SUPPORT
164 config RWSEM_XCHGADD_ALGORITHM
171 config GENERIC_BUG_RELATIVE_POINTERS
173 depends on GENERIC_BUG
175 config GENERIC_HWEIGHT
181 config GENERIC_CALIBRATE_DELAY
187 config HAVE_GENERIC_RCU_GUP
190 config ARCH_DMA_ADDR_T_64BIT
193 config NEED_DMA_MAP_STATE
196 config NEED_SG_DMA_LENGTH
208 config KERNEL_MODE_NEON
211 config FIX_EARLYCON_MEM
214 config PGTABLE_LEVELS
216 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
217 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
218 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
219 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
220 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
221 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
223 source "init/Kconfig"
225 source "kernel/Kconfig.freezer"
227 source "arch/arm64/Kconfig.platforms"
234 This feature enables support for PCI bus system. If you say Y
235 here, the kernel will include drivers and infrastructure code
236 to support PCI bus devices.
241 config PCI_DOMAINS_GENERIC
247 source "drivers/pci/Kconfig"
248 source "drivers/pci/pcie/Kconfig"
249 source "drivers/pci/hotplug/Kconfig"
253 menu "Kernel Features"
255 menu "ARM errata workarounds via the alternatives framework"
257 config ARM64_ERRATUM_826319
258 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
261 This option adds an alternative code sequence to work around ARM
262 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
263 AXI master interface and an L2 cache.
265 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
266 and is unable to accept a certain write via this interface, it will
267 not progress on read data presented on the read data channel and the
270 The workaround promotes data cache clean instructions to
271 data cache clean-and-invalidate.
272 Please note that this does not necessarily enable the workaround,
273 as it depends on the alternative framework, which will only patch
274 the kernel if an affected CPU is detected.
278 config ARM64_ERRATUM_827319
279 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
282 This option adds an alternative code sequence to work around ARM
283 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
284 master interface and an L2 cache.
286 Under certain conditions this erratum can cause a clean line eviction
287 to occur at the same time as another transaction to the same address
288 on the AMBA 5 CHI interface, which can cause data corruption if the
289 interconnect reorders the two transactions.
291 The workaround promotes data cache clean instructions to
292 data cache clean-and-invalidate.
293 Please note that this does not necessarily enable the workaround,
294 as it depends on the alternative framework, which will only patch
295 the kernel if an affected CPU is detected.
299 config ARM64_ERRATUM_824069
300 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
303 This option adds an alternative code sequence to work around ARM
304 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
305 to a coherent interconnect.
307 If a Cortex-A53 processor is executing a store or prefetch for
308 write instruction at the same time as a processor in another
309 cluster is executing a cache maintenance operation to the same
310 address, then this erratum might cause a clean cache line to be
311 incorrectly marked as dirty.
313 The workaround promotes data cache clean instructions to
314 data cache clean-and-invalidate.
315 Please note that this option does not necessarily enable the
316 workaround, as it depends on the alternative framework, which will
317 only patch the kernel if an affected CPU is detected.
321 config ARM64_ERRATUM_819472
322 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
325 This option adds an alternative code sequence to work around ARM
326 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
327 present when it is connected to a coherent interconnect.
329 If the processor is executing a load and store exclusive sequence at
330 the same time as a processor in another cluster is executing a cache
331 maintenance operation to the same address, then this erratum might
332 cause data corruption.
334 The workaround promotes data cache clean instructions to
335 data cache clean-and-invalidate.
336 Please note that this does not necessarily enable the workaround,
337 as it depends on the alternative framework, which will only patch
338 the kernel if an affected CPU is detected.
342 config ARM64_ERRATUM_832075
343 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
346 This option adds an alternative code sequence to work around ARM
347 erratum 832075 on Cortex-A57 parts up to r1p2.
349 Affected Cortex-A57 parts might deadlock when exclusive load/store
350 instructions to Write-Back memory are mixed with Device loads.
352 The workaround is to promote device loads to use Load-Acquire
354 Please note that this does not necessarily enable the workaround,
355 as it depends on the alternative framework, which will only patch
356 the kernel if an affected CPU is detected.
360 config ARM64_ERRATUM_834220
361 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
365 This option adds an alternative code sequence to work around ARM
366 erratum 834220 on Cortex-A57 parts up to r1p2.
368 Affected Cortex-A57 parts might report a Stage 2 translation
369 fault as the result of a Stage 1 fault for load crossing a
370 page boundary when there is a permission or device memory
371 alignment fault at Stage 1 and a translation fault at Stage 2.
373 The workaround is to verify that the Stage 1 translation
374 doesn't generate a fault before handling the Stage 2 fault.
375 Please note that this does not necessarily enable the workaround,
376 as it depends on the alternative framework, which will only patch
377 the kernel if an affected CPU is detected.
381 config ARM64_ERRATUM_845719
382 bool "Cortex-A53: 845719: a load might read incorrect data"
386 This option adds an alternative code sequence to work around ARM
387 erratum 845719 on Cortex-A53 parts up to r0p4.
389 When running a compat (AArch32) userspace on an affected Cortex-A53
390 part, a load at EL0 from a virtual address that matches the bottom 32
391 bits of the virtual address used by a recent load at (AArch64) EL1
392 might return incorrect data.
394 The workaround is to write the contextidr_el1 register on exception
395 return to a 32-bit task.
396 Please note that this does not necessarily enable the workaround,
397 as it depends on the alternative framework, which will only patch
398 the kernel if an affected CPU is detected.
402 config ARM64_ERRATUM_843419
403 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
406 select ARM64_MODULE_CMODEL_LARGE
408 This option builds kernel modules using the large memory model in
409 order to avoid the use of the ADRP instruction, which can cause
410 a subsequent memory access to use an incorrect address on Cortex-A53
413 Note that the kernel itself must be linked with a version of ld
414 which fixes potentially affected ADRP instructions through the
419 config CAVIUM_ERRATUM_22375
420 bool "Cavium erratum 22375, 24313"
423 Enable workaround for erratum 22375, 24313.
425 This implements two gicv3-its errata workarounds for ThunderX. Both
426 with small impact affecting only ITS table allocation.
428 erratum 22375: only alloc 8MB table size
429 erratum 24313: ignore memory access type
431 The fixes are in ITS initialization and basically ignore memory access
432 type and table size provided by the TYPER and BASER registers.
436 config CAVIUM_ERRATUM_23144
437 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
441 ITS SYNC command hang for cross node io and collections/cpu mapping.
445 config CAVIUM_ERRATUM_23154
446 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
449 The gicv3 of ThunderX requires a modified version for
450 reading the IAR status to ensure data synchronization
451 (access to icc_iar1_el1 is not sync'ed before and after).
455 config CAVIUM_ERRATUM_27456
456 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
459 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
460 instructions may cause the icache to become corrupted if it
461 contains data for a non-current ASID. The fix is to
462 invalidate the icache when changing the mm context.
471 default ARM64_4K_PAGES
473 Page size (translation granule) configuration.
475 config ARM64_4K_PAGES
478 This feature enables 4KB pages support.
480 config ARM64_16K_PAGES
483 The system will use 16KB pages support. AArch32 emulation
484 requires applications compiled with 16K (or a multiple of 16K)
487 config ARM64_64K_PAGES
490 This feature enables 64KB pages support (4KB by default)
491 allowing only two levels of page tables and faster TLB
492 look-up. AArch32 emulation requires applications compiled
493 with 64K aligned segments.
498 prompt "Virtual address space size"
499 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
500 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
501 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
503 Allows choosing one of multiple possible virtual address
504 space sizes. The level of translation table is determined by
505 a combination of page size and virtual address space size.
507 config ARM64_VA_BITS_36
508 bool "36-bit" if EXPERT
509 depends on ARM64_16K_PAGES
511 config ARM64_VA_BITS_39
513 depends on ARM64_4K_PAGES
515 config ARM64_VA_BITS_42
517 depends on ARM64_64K_PAGES
519 config ARM64_VA_BITS_47
521 depends on ARM64_16K_PAGES
523 config ARM64_VA_BITS_48
530 default 36 if ARM64_VA_BITS_36
531 default 39 if ARM64_VA_BITS_39
532 default 42 if ARM64_VA_BITS_42
533 default 47 if ARM64_VA_BITS_47
534 default 48 if ARM64_VA_BITS_48
536 config CPU_BIG_ENDIAN
537 bool "Build big-endian kernel"
539 Say Y if you plan on running a kernel in big-endian mode.
542 bool "Multi-core scheduler support"
544 Multi-core scheduler support improves the CPU scheduler's decision
545 making when dealing with multi-core CPU chips at a cost of slightly
546 increased overhead in some places. If unsure say N here.
549 bool "SMT scheduler support"
551 Improves the CPU scheduler's decision making when dealing with
552 MultiThreading at a cost of slightly increased overhead in some
553 places. If unsure say N here.
556 int "Maximum number of CPUs (2-4096)"
558 # These have to remain sorted largest to smallest
562 bool "Support for hot-pluggable CPUs"
563 select GENERIC_IRQ_MIGRATION
565 Say Y here to experiment with turning CPUs off and on. CPUs
566 can be controlled through /sys/devices/system/cpu.
568 source kernel/Kconfig.preempt
569 source kernel/Kconfig.hz
571 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
574 config ARCH_HAS_HOLES_MEMORYMODEL
575 def_bool y if SPARSEMEM
577 config ARCH_SPARSEMEM_ENABLE
579 select SPARSEMEM_VMEMMAP_ENABLE
581 config ARCH_SPARSEMEM_DEFAULT
582 def_bool ARCH_SPARSEMEM_ENABLE
584 config ARCH_SELECT_MEMORY_MODEL
585 def_bool ARCH_SPARSEMEM_ENABLE
587 config HAVE_ARCH_PFN_VALID
588 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
590 config HW_PERF_EVENTS
594 config SYS_SUPPORTS_HUGETLBFS
597 config ARCH_WANT_HUGE_PMD_SHARE
598 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
600 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
603 config ARCH_HAS_CACHE_LINE_SIZE
609 bool "Enable seccomp to safely compute untrusted bytecode"
611 This kernel feature is useful for number crunching applications
612 that may need to compute untrusted bytecode during their
613 execution. By using pipes or other transports made available to
614 the process as file descriptors supporting the read/write
615 syscalls, it's possible to isolate those applications in
616 their own address space using seccomp. Once seccomp is
617 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
618 and the task is only allowed to execute a few safe syscalls
619 defined by each seccomp mode.
626 bool "Xen guest support on ARM64"
627 depends on ARM64 && OF
630 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
632 config FORCE_MAX_ZONEORDER
634 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
635 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
638 The kernel memory allocator divides physically contiguous memory
639 blocks into "zones", where each zone is a power of two number of
640 pages. This option selects the largest power of two that the kernel
641 keeps in the memory allocator. If you need to allocate very large
642 blocks of physically contiguous memory, then you may need to
645 This config option is actually maximum order plus one. For example,
646 a value of 11 means that the largest free memory block is 2^10 pages.
648 We make sure that we can allocate upto a HugePage size for each configuration.
650 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
652 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
653 4M allocations matching the default size used by generic code.
655 menuconfig ARMV8_DEPRECATED
656 bool "Emulate deprecated/obsolete ARMv8 instructions"
659 Legacy software support may require certain instructions
660 that have been deprecated or obsoleted in the architecture.
662 Enable this config to enable selective emulation of these
670 bool "Emulate SWP/SWPB instructions"
672 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
673 they are always undefined. Say Y here to enable software
674 emulation of these instructions for userspace using LDXR/STXR.
676 In some older versions of glibc [<=2.8] SWP is used during futex
677 trylock() operations with the assumption that the code will not
678 be preempted. This invalid assumption may be more likely to fail
679 with SWP emulation enabled, leading to deadlock of the user
682 NOTE: when accessing uncached shared regions, LDXR/STXR rely
683 on an external transaction monitoring block called a global
684 monitor to maintain update atomicity. If your system does not
685 implement a global monitor, this option can cause programs that
686 perform SWP operations to uncached memory to deadlock.
690 config CP15_BARRIER_EMULATION
691 bool "Emulate CP15 Barrier instructions"
693 The CP15 barrier instructions - CP15ISB, CP15DSB, and
694 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
695 strongly recommended to use the ISB, DSB, and DMB
696 instructions instead.
698 Say Y here to enable software emulation of these
699 instructions for AArch32 userspace code. When this option is
700 enabled, CP15 barrier usage is traced which can help
701 identify software that needs updating.
705 config SETEND_EMULATION
706 bool "Emulate SETEND instruction"
708 The SETEND instruction alters the data-endianness of the
709 AArch32 EL0, and is deprecated in ARMv8.
711 Say Y here to enable software emulation of the instruction
712 for AArch32 userspace code.
714 Note: All the cpus on the system must have mixed endian support at EL0
715 for this feature to be enabled. If a new CPU - which doesn't support mixed
716 endian - is hotplugged in after this feature has been enabled, there could
717 be unexpected results in the applications.
722 config ARM64_SW_TTBR0_PAN
723 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
725 Enabling this option prevents the kernel from accessing
726 user-space memory directly by pointing TTBR0_EL1 to a reserved
727 zeroed area and reserved ASID. The user access routines
728 restore the valid TTBR0_EL1 temporarily.
730 menu "ARMv8.1 architectural features"
732 config ARM64_HW_AFDBM
733 bool "Support for hardware updates of the Access and Dirty page flags"
736 The ARMv8.1 architecture extensions introduce support for
737 hardware updates of the access and dirty information in page
738 table entries. When enabled in TCR_EL1 (HA and HD bits) on
739 capable processors, accesses to pages with PTE_AF cleared will
740 set this bit instead of raising an access flag fault.
741 Similarly, writes to read-only pages with the DBM bit set will
742 clear the read-only bit (AP[2]) instead of raising a
745 Kernels built with this configuration option enabled continue
746 to work on pre-ARMv8.1 hardware and the performance impact is
747 minimal. If unsure, say Y.
750 bool "Enable support for Privileged Access Never (PAN)"
753 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
754 prevents the kernel or hypervisor from accessing user-space (EL0)
757 Choosing this option will cause any unprotected (not using
758 copy_to_user et al) memory access to fail with a permission fault.
760 The feature is detected at runtime, and will remain as a 'nop'
761 instruction if the cpu does not implement the feature.
763 config ARM64_LSE_ATOMICS
764 bool "Atomic instructions"
766 As part of the Large System Extensions, ARMv8.1 introduces new
767 atomic instructions that are designed specifically to scale in
770 Say Y here to make use of these instructions for the in-kernel
771 atomic routines. This incurs a small overhead on CPUs that do
772 not support these instructions and requires the kernel to be
773 built with binutils >= 2.25.
778 bool "Enable support for User Access Override (UAO)"
781 User Access Override (UAO; part of the ARMv8.2 Extensions)
782 causes the 'unprivileged' variant of the load/store instructions to
783 be overriden to be privileged.
785 This option changes get_user() and friends to use the 'unprivileged'
786 variant of the load/store instructions. This ensures that user-space
787 really did have access to the supplied memory. When addr_limit is
788 set to kernel memory the UAO bit will be set, allowing privileged
789 access to kernel memory.
791 Choosing this option will cause copy_to_user() et al to use user-space
794 The feature is detected at runtime, the kernel will use the
795 regular load/store instructions if the cpu does not implement the
798 config ARM64_MODULE_CMODEL_LARGE
801 config ARM64_MODULE_PLTS
803 select ARM64_MODULE_CMODEL_LARGE
804 select HAVE_MOD_ARCH_SPECIFIC
809 This builds the kernel as a Position Independent Executable (PIE),
810 which retains all relocation metadata required to relocate the
811 kernel binary at runtime to a different virtual address than the
812 address it was linked at.
813 Since AArch64 uses the RELA relocation format, this requires a
814 relocation pass at runtime even if the kernel is loaded at the
815 same address it was linked at.
817 config RANDOMIZE_BASE
818 bool "Randomize the address of the kernel image"
819 select ARM64_MODULE_PLTS if MODULES
822 Randomizes the virtual address at which the kernel image is
823 loaded, as a security feature that deters exploit attempts
824 relying on knowledge of the location of kernel internals.
826 It is the bootloader's job to provide entropy, by passing a
827 random u64 value in /chosen/kaslr-seed at kernel entry.
829 When booting via the UEFI stub, it will invoke the firmware's
830 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
831 to the kernel proper. In addition, it will randomise the physical
832 location of the kernel Image as well.
836 config RANDOMIZE_MODULE_REGION_FULL
837 bool "Randomize the module region independently from the core kernel"
838 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
841 Randomizes the location of the module region without considering the
842 location of the core kernel. This way, it is impossible for modules
843 to leak information about the location of core kernel data structures
844 but it does imply that function calls between modules and the core
845 kernel will need to be resolved via veneers in the module PLT.
847 When this option is not set, the module region will be randomized over
848 a limited range that contains the [_stext, _etext] interval of the
849 core kernel, so branch relocations are always in range.
855 config ARM64_ACPI_PARKING_PROTOCOL
856 bool "Enable support for the ARM64 ACPI parking protocol"
859 Enable support for the ARM64 ACPI parking protocol. If disabled
860 the kernel will not allow booting through the ARM64 ACPI parking
861 protocol even if the corresponding data is present in the ACPI
865 string "Default kernel command string"
868 Provide a set of default command-line options at build time by
869 entering them here. As a minimum, you should specify the the
870 root device (e.g. root=/dev/nfs).
873 prompt "Kernel command line type" if CMDLINE != ""
874 default CMDLINE_FROM_BOOTLOADER
876 config CMDLINE_FROM_BOOTLOADER
877 bool "Use bootloader kernel arguments if available"
879 Uses the command-line options passed by the boot loader. If
880 the boot loader doesn't provide any, the default kernel command
881 string provided in CMDLINE will be used.
883 config CMDLINE_EXTEND
884 bool "Extend bootloader kernel arguments"
886 The command-line arguments provided by the boot loader will be
887 appended to the default kernel command string.
890 bool "Always use the default kernel command string"
892 Always use the default kernel command string, even if the boot
893 loader passes other arguments to the kernel.
894 This is useful if you cannot or don't want to change the
895 command-line options your boot loader passes to the kernel.
902 bool "UEFI runtime support"
903 depends on OF && !CPU_BIG_ENDIAN
906 select EFI_PARAMS_FROM_FDT
907 select EFI_RUNTIME_WRAPPERS
912 This option provides support for runtime services provided
913 by UEFI firmware (such as non-volatile variables, realtime
914 clock, and platform reset). A UEFI stub is also provided to
915 allow the kernel to be booted as an EFI application. This
916 is only useful on systems that have UEFI firmware.
919 bool "Enable support for SMBIOS (DMI) tables"
923 This enables SMBIOS/DMI feature for systems.
925 This option is only useful on systems that have UEFI firmware.
926 However, even with this option, the resultant kernel should
927 continue to boot on existing non-UEFI platforms.
929 config BUILD_ARM64_APPENDED_DTB_IMAGE
930 bool "Build a concatenated Image.gz/dtb by default"
933 Enabling this option will cause a concatenated Image.gz and list of
934 DTBs to be built by default (instead of a standalone Image.gz.)
935 The image will built in arch/arm64/boot/Image.gz-dtb
938 prompt "Appended DTB Kernel Image name"
939 depends on BUILD_ARM64_APPENDED_DTB_IMAGE
941 Enabling this option will cause a specific kernel image Image or
942 Image.gz to be used for final image creation.
943 The image will built in arch/arm64/boot/IMAGE-NAME-dtb
951 config BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME
953 depends on BUILD_ARM64_APPENDED_DTB_IMAGE
954 default "Image.gz-dtb" if IMG_GZ_DTB
955 default "Image-dtb" if IMG_DTB
957 config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
958 string "Default dtb names"
959 depends on BUILD_ARM64_APPENDED_DTB_IMAGE
961 Space separated list of names of dtbs to append when
962 building a concatenated Image.gz-dtb.
966 menu "Userspace binary formats"
968 source "fs/Kconfig.binfmt"
971 bool "Kernel support for 32-bit EL0"
972 depends on ARM64_4K_PAGES || EXPERT
973 select COMPAT_BINFMT_ELF
975 select OLD_SIGSUSPEND3
976 select COMPAT_OLD_SIGACTION
978 This option enables support for a 32-bit EL0 running under a 64-bit
979 kernel at EL1. AArch32-specific components such as system calls,
980 the user helper functions, VFP support and the ptrace interface are
981 handled appropriately by the kernel.
983 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
984 that you will only be able to execute AArch32 binaries that were compiled
985 with page size aligned segments.
987 If you want to execute 32-bit userspace applications, say Y.
989 config SYSVIPC_COMPAT
991 depends on COMPAT && SYSVIPC
995 menu "Power management options"
997 source "kernel/power/Kconfig"
999 config ARCH_HIBERNATION_POSSIBLE
1003 config ARCH_HIBERNATION_HEADER
1005 depends on HIBERNATION
1007 config ARCH_SUSPEND_POSSIBLE
1012 menu "CPU Power Management"
1014 source "drivers/cpuidle/Kconfig"
1016 source "drivers/cpufreq/Kconfig"
1020 source "net/Kconfig"
1022 source "drivers/Kconfig"
1024 source "drivers/firmware/Kconfig"
1026 source "drivers/acpi/Kconfig"
1030 source "arch/arm64/kvm/Kconfig"
1032 source "arch/arm64/Kconfig.debug"
1034 source "security/Kconfig"
1036 source "crypto/Kconfig"
1038 source "arch/arm64/crypto/Kconfig"
1041 source "lib/Kconfig"