3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_BITREVERSE
43 select HAVE_ARCH_JUMP_LABEL
45 select HAVE_ARCH_SECCOMP_FILTER
46 select HAVE_ARCH_TRACEHOOK
48 select HAVE_C_RECORDMCOUNT
49 select HAVE_CC_STACKPROTECTOR
50 select HAVE_CMPXCHG_DOUBLE
51 select HAVE_DEBUG_BUGVERBOSE
52 select HAVE_DEBUG_KMEMLEAK
53 select HAVE_DMA_API_DEBUG
55 select HAVE_DMA_CONTIGUOUS
56 select HAVE_DYNAMIC_FTRACE
57 select HAVE_EFFICIENT_UNALIGNED_ACCESS
58 select HAVE_FTRACE_MCOUNT_RECORD
59 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
61 select HAVE_GENERIC_DMA_COHERENT
62 select HAVE_HW_BREAKPOINT if PERF_EVENTS
64 select HAVE_PATA_PLATFORM
65 select HAVE_PERF_EVENTS
67 select HAVE_PERF_USER_STACK_DUMP
68 select HAVE_RCU_TABLE_FREE
69 select HAVE_SYSCALL_TRACEPOINTS
71 select MODULES_USE_ELF_RELA
74 select OF_EARLY_FLATTREE
75 select OF_RESERVED_MEM
76 select PERF_USE_VMALLOC
81 select SYSCTL_EXCEPTION_TRACE
82 select HAVE_CONTEXT_TRACKING
84 ARM 64-bit (AArch64) Linux support.
89 config ARCH_PHYS_ADDR_T_64BIT
98 config STACKTRACE_SUPPORT
101 config LOCKDEP_SUPPORT
104 config TRACE_IRQFLAGS_SUPPORT
107 config RWSEM_XCHGADD_ALGORITHM
110 config GENERIC_HWEIGHT
116 config GENERIC_CALIBRATE_DELAY
122 config HAVE_GENERIC_RCU_GUP
125 config ARCH_DMA_ADDR_T_64BIT
128 config NEED_DMA_MAP_STATE
131 config NEED_SG_DMA_LENGTH
140 config KERNEL_MODE_NEON
143 config FIX_EARLYCON_MEM
146 source "init/Kconfig"
148 source "kernel/Kconfig.freezer"
150 menu "Platform selection"
155 This enables support for Samsung Exynos SoC family
158 bool "ARMv8 based Samsung Exynos7"
160 select COMMON_CLK_SAMSUNG
161 select HAVE_S3C2410_WATCHDOG if WATCHDOG
162 select HAVE_S3C_RTC if RTC_CLASS
164 select PINCTRL_EXYNOS
167 This enables support for Samsung Exynos7 SoC family
169 config ARCH_FSL_LS2085A
170 bool "Freescale LS2085A SOC"
172 This enables support for Freescale LS2085A SOC.
175 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
178 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
181 bool "AMD Seattle SoC Family"
183 This enables support for AMD Seattle SOC Family
186 bool "NVIDIA Tegra SoC Family"
187 select ARCH_HAS_RESET_CONTROLLER
188 select ARCH_REQUIRE_GPIOLIB
192 select GENERIC_CLOCKEVENTS
195 select RESET_CONTROLLER
197 This enables support for the NVIDIA Tegra SoC family.
199 config ARCH_TEGRA_132_SOC
200 bool "NVIDIA Tegra132 SoC"
201 depends on ARCH_TEGRA
202 select PINCTRL_TEGRA124
203 select USB_ULPI if USB_PHY
204 select USB_ULPI_VIEWPORT if USB_PHY
206 Enable support for NVIDIA Tegra132 SoC, based on the Denver
207 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
208 but contains an NVIDIA Denver CPU complex in place of
209 Tegra124's "4+1" Cortex-A15 CPU complex.
212 bool "Cavium Inc. Thunder SoC Family"
214 This enables support for Cavium's Thunder Family of SoCs.
217 bool "ARMv8 software model (Versatile Express)"
218 select ARCH_REQUIRE_GPIOLIB
219 select COMMON_CLK_VERSATILE
220 select POWER_RESET_VEXPRESS
221 select VEXPRESS_CONFIG
223 This enables support for the ARMv8 software model (Versatile
227 bool "AppliedMicro X-Gene SOC Family"
229 This enables support for AppliedMicro X-Gene SOC Family
238 This feature enables support for PCI bus system. If you say Y
239 here, the kernel will include drivers and infrastructure code
240 to support PCI bus devices.
245 config PCI_DOMAINS_GENERIC
251 source "drivers/pci/Kconfig"
252 source "drivers/pci/pcie/Kconfig"
253 source "drivers/pci/hotplug/Kconfig"
257 menu "Kernel Features"
259 menu "ARM errata workarounds via the alternatives framework"
261 config ARM64_ERRATUM_826319
262 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
265 This option adds an alternative code sequence to work around ARM
266 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
267 AXI master interface and an L2 cache.
269 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
270 and is unable to accept a certain write via this interface, it will
271 not progress on read data presented on the read data channel and the
274 The workaround promotes data cache clean instructions to
275 data cache clean-and-invalidate.
276 Please note that this does not necessarily enable the workaround,
277 as it depends on the alternative framework, which will only patch
278 the kernel if an affected CPU is detected.
282 config ARM64_ERRATUM_827319
283 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
286 This option adds an alternative code sequence to work around ARM
287 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
288 master interface and an L2 cache.
290 Under certain conditions this erratum can cause a clean line eviction
291 to occur at the same time as another transaction to the same address
292 on the AMBA 5 CHI interface, which can cause data corruption if the
293 interconnect reorders the two transactions.
295 The workaround promotes data cache clean instructions to
296 data cache clean-and-invalidate.
297 Please note that this does not necessarily enable the workaround,
298 as it depends on the alternative framework, which will only patch
299 the kernel if an affected CPU is detected.
303 config ARM64_ERRATUM_824069
304 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
307 This option adds an alternative code sequence to work around ARM
308 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
309 to a coherent interconnect.
311 If a Cortex-A53 processor is executing a store or prefetch for
312 write instruction at the same time as a processor in another
313 cluster is executing a cache maintenance operation to the same
314 address, then this erratum might cause a clean cache line to be
315 incorrectly marked as dirty.
317 The workaround promotes data cache clean instructions to
318 data cache clean-and-invalidate.
319 Please note that this option does not necessarily enable the
320 workaround, as it depends on the alternative framework, which will
321 only patch the kernel if an affected CPU is detected.
325 config ARM64_ERRATUM_819472
326 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
329 This option adds an alternative code sequence to work around ARM
330 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
331 present when it is connected to a coherent interconnect.
333 If the processor is executing a load and store exclusive sequence at
334 the same time as a processor in another cluster is executing a cache
335 maintenance operation to the same address, then this erratum might
336 cause data corruption.
338 The workaround promotes data cache clean instructions to
339 data cache clean-and-invalidate.
340 Please note that this does not necessarily enable the workaround,
341 as it depends on the alternative framework, which will only patch
342 the kernel if an affected CPU is detected.
346 config ARM64_ERRATUM_832075
347 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
350 This option adds an alternative code sequence to work around ARM
351 erratum 832075 on Cortex-A57 parts up to r1p2.
353 Affected Cortex-A57 parts might deadlock when exclusive load/store
354 instructions to Write-Back memory are mixed with Device loads.
356 The workaround is to promote device loads to use Load-Acquire
358 Please note that this does not necessarily enable the workaround,
359 as it depends on the alternative framework, which will only patch
360 the kernel if an affected CPU is detected.
369 default ARM64_4K_PAGES
371 Page size (translation granule) configuration.
373 config ARM64_4K_PAGES
376 This feature enables 4KB pages support.
378 config ARM64_64K_PAGES
381 This feature enables 64KB pages support (4KB by default)
382 allowing only two levels of page tables and faster TLB
383 look-up. AArch32 emulation is not available when this feature
389 prompt "Virtual address space size"
390 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
391 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
393 Allows choosing one of multiple possible virtual address
394 space sizes. The level of translation table is determined by
395 a combination of page size and virtual address space size.
397 config ARM64_VA_BITS_39
399 depends on ARM64_4K_PAGES
401 config ARM64_VA_BITS_42
403 depends on ARM64_64K_PAGES
405 config ARM64_VA_BITS_48
412 default 39 if ARM64_VA_BITS_39
413 default 42 if ARM64_VA_BITS_42
414 default 48 if ARM64_VA_BITS_48
416 config ARM64_PGTABLE_LEVELS
418 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
419 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
420 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
421 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
423 config CPU_BIG_ENDIAN
424 bool "Build big-endian kernel"
426 Say Y if you plan on running a kernel in big-endian mode.
429 bool "Symmetric Multi-Processing"
431 This enables support for systems with more than one CPU. If
432 you say N here, the kernel will run on single and
433 multiprocessor machines, but will use only one CPU of a
434 multiprocessor machine. If you say Y here, the kernel will run
435 on many, but not all, single processor machines. On a single
436 processor machine, the kernel will run faster if you say N
439 If you don't know what to do here, say N.
442 bool "Multi-core scheduler support"
445 Multi-core scheduler support improves the CPU scheduler's decision
446 making when dealing with multi-core CPU chips at a cost of slightly
447 increased overhead in some places. If unsure say N here.
450 bool "SMT scheduler support"
453 Improves the CPU scheduler's decision making when dealing with
454 MultiThreading at a cost of slightly increased overhead in some
455 places. If unsure say N here.
458 int "Maximum number of CPUs (2-4096)"
461 # These have to remain sorted largest to smallest
465 bool "Support for hot-pluggable CPUs"
468 Say Y here to experiment with turning CPUs off and on. CPUs
469 can be controlled through /sys/devices/system/cpu.
471 source kernel/Kconfig.preempt
481 config ARCH_HAS_HOLES_MEMORYMODEL
482 def_bool y if SPARSEMEM
484 config ARCH_SPARSEMEM_ENABLE
486 select SPARSEMEM_VMEMMAP_ENABLE
488 config ARCH_SPARSEMEM_DEFAULT
489 def_bool ARCH_SPARSEMEM_ENABLE
491 config ARCH_SELECT_MEMORY_MODEL
492 def_bool ARCH_SPARSEMEM_ENABLE
494 config HAVE_ARCH_PFN_VALID
495 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
497 config HW_PERF_EVENTS
498 bool "Enable hardware performance counter support for perf events"
499 depends on PERF_EVENTS
502 Enable hardware performance counter support for perf events. If
503 disabled, perf events will use software events only.
505 config SYS_SUPPORTS_HUGETLBFS
508 config ARCH_WANT_GENERAL_HUGETLB
511 config ARCH_WANT_HUGE_PMD_SHARE
512 def_bool y if !ARM64_64K_PAGES
514 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
517 config ARCH_HAS_CACHE_LINE_SIZE
523 bool "Enable seccomp to safely compute untrusted bytecode"
525 This kernel feature is useful for number crunching applications
526 that may need to compute untrusted bytecode during their
527 execution. By using pipes or other transports made available to
528 the process as file descriptors supporting the read/write
529 syscalls, it's possible to isolate those applications in
530 their own address space using seccomp. Once seccomp is
531 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
532 and the task is only allowed to execute a few safe syscalls
533 defined by each seccomp mode.
540 bool "Xen guest support on ARM64"
541 depends on ARM64 && OF
544 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
546 config FORCE_MAX_ZONEORDER
548 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
551 menuconfig ARMV8_DEPRECATED
552 bool "Emulate deprecated/obsolete ARMv8 instructions"
555 Legacy software support may require certain instructions
556 that have been deprecated or obsoleted in the architecture.
558 Enable this config to enable selective emulation of these
566 bool "Emulate SWP/SWPB instructions"
568 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
569 they are always undefined. Say Y here to enable software
570 emulation of these instructions for userspace using LDXR/STXR.
572 In some older versions of glibc [<=2.8] SWP is used during futex
573 trylock() operations with the assumption that the code will not
574 be preempted. This invalid assumption may be more likely to fail
575 with SWP emulation enabled, leading to deadlock of the user
578 NOTE: when accessing uncached shared regions, LDXR/STXR rely
579 on an external transaction monitoring block called a global
580 monitor to maintain update atomicity. If your system does not
581 implement a global monitor, this option can cause programs that
582 perform SWP operations to uncached memory to deadlock.
586 config CP15_BARRIER_EMULATION
587 bool "Emulate CP15 Barrier instructions"
589 The CP15 barrier instructions - CP15ISB, CP15DSB, and
590 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
591 strongly recommended to use the ISB, DSB, and DMB
592 instructions instead.
594 Say Y here to enable software emulation of these
595 instructions for AArch32 userspace code. When this option is
596 enabled, CP15 barrier usage is traced which can help
597 identify software that needs updating.
601 config SETEND_EMULATION
602 bool "Emulate SETEND instruction"
604 The SETEND instruction alters the data-endianness of the
605 AArch32 EL0, and is deprecated in ARMv8.
607 Say Y here to enable software emulation of the instruction
608 for AArch32 userspace code.
610 Note: All the cpus on the system must have mixed endian support at EL0
611 for this feature to be enabled. If a new CPU - which doesn't support mixed
612 endian - is hotplugged in after this feature has been enabled, there could
613 be unexpected results in the applications.
623 string "Default kernel command string"
626 Provide a set of default command-line options at build time by
627 entering them here. As a minimum, you should specify the the
628 root device (e.g. root=/dev/nfs).
631 bool "Always use the default kernel command string"
633 Always use the default kernel command string, even if the boot
634 loader passes other arguments to the kernel.
635 This is useful if you cannot or don't want to change the
636 command-line options your boot loader passes to the kernel.
642 bool "UEFI runtime support"
643 depends on OF && !CPU_BIG_ENDIAN
646 select EFI_PARAMS_FROM_FDT
647 select EFI_RUNTIME_WRAPPERS
652 This option provides support for runtime services provided
653 by UEFI firmware (such as non-volatile variables, realtime
654 clock, and platform reset). A UEFI stub is also provided to
655 allow the kernel to be booted as an EFI application. This
656 is only useful on systems that have UEFI firmware.
659 bool "Enable support for SMBIOS (DMI) tables"
663 This enables SMBIOS/DMI feature for systems.
665 This option is only useful on systems that have UEFI firmware.
666 However, even with this option, the resultant kernel should
667 continue to boot on existing non-UEFI platforms.
671 menu "Userspace binary formats"
673 source "fs/Kconfig.binfmt"
676 bool "Kernel support for 32-bit EL0"
677 depends on !ARM64_64K_PAGES || EXPERT
678 select COMPAT_BINFMT_ELF
680 select OLD_SIGSUSPEND3
681 select COMPAT_OLD_SIGACTION
683 This option enables support for a 32-bit EL0 running under a 64-bit
684 kernel at EL1. AArch32-specific components such as system calls,
685 the user helper functions, VFP support and the ptrace interface are
686 handled appropriately by the kernel.
688 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
689 will only be able to execute AArch32 binaries that were compiled with
690 64k aligned segments.
692 If you want to execute 32-bit userspace applications, say Y.
694 config SYSVIPC_COMPAT
696 depends on COMPAT && SYSVIPC
700 menu "Power management options"
702 source "kernel/power/Kconfig"
704 config ARCH_SUSPEND_POSSIBLE
709 menu "CPU Power Management"
711 source "drivers/cpuidle/Kconfig"
713 source "drivers/cpufreq/Kconfig"
719 source "drivers/Kconfig"
721 source "drivers/firmware/Kconfig"
725 source "arch/arm64/kvm/Kconfig"
727 source "arch/arm64/Kconfig.debug"
729 source "security/Kconfig"
731 source "crypto/Kconfig"
733 source "arch/arm64/crypto/Kconfig"