3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HARDENED_USERCOPY
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_SECCOMP_FILTER
58 select HAVE_ARCH_TRACEHOOK
60 select HAVE_C_RECORDMCOUNT
61 select HAVE_CC_STACKPROTECTOR
62 select HAVE_CMPXCHG_DOUBLE
63 select HAVE_CMPXCHG_LOCAL
64 select HAVE_DEBUG_BUGVERBOSE
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DMA_API_DEBUG
68 select HAVE_DMA_CONTIGUOUS
69 select HAVE_DYNAMIC_FTRACE
70 select HAVE_EFFICIENT_UNALIGNED_ACCESS
71 select HAVE_FTRACE_MCOUNT_RECORD
72 select HAVE_FUNCTION_TRACER
73 select HAVE_FUNCTION_GRAPH_TRACER
74 select HAVE_GENERIC_DMA_COHERENT
75 select HAVE_HW_BREAKPOINT if PERF_EVENTS
76 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_PATA_PLATFORM
79 select HAVE_PERF_EVENTS
81 select HAVE_PERF_USER_STACK_DUMP
82 select HAVE_REGS_AND_STACK_ACCESS_API
83 select HAVE_RCU_TABLE_FREE
84 select HAVE_SYSCALL_TRACEPOINTS
86 select HAVE_KRETPROBES if HAVE_KPROBES
87 select IOMMU_DMA if IOMMU_SUPPORT
89 select IRQ_FORCED_THREADING
90 select MODULES_USE_ELF_RELA
93 select OF_EARLY_FLATTREE
94 select OF_RESERVED_MEM
95 select PERF_USE_VMALLOC
100 select SYSCTL_EXCEPTION_TRACE
101 select HAVE_CONTEXT_TRACKING
102 select HAVE_ARM_SMCCC
104 ARM 64-bit (AArch64) Linux support.
109 config ARCH_PHYS_ADDR_T_64BIT
115 config ARM64_PAGE_SHIFT
117 default 16 if ARM64_64K_PAGES
118 default 14 if ARM64_16K_PAGES
121 config ARM64_CONT_SHIFT
123 default 5 if ARM64_64K_PAGES
124 default 7 if ARM64_16K_PAGES
130 config STACKTRACE_SUPPORT
133 config ILLEGAL_POINTER_VALUE
135 default 0xdead000000000000
137 config LOCKDEP_SUPPORT
140 config TRACE_IRQFLAGS_SUPPORT
143 config RWSEM_XCHGADD_ALGORITHM
150 config GENERIC_BUG_RELATIVE_POINTERS
152 depends on GENERIC_BUG
154 config GENERIC_HWEIGHT
160 config GENERIC_CALIBRATE_DELAY
166 config HAVE_GENERIC_RCU_GUP
169 config ARCH_DMA_ADDR_T_64BIT
172 config NEED_DMA_MAP_STATE
175 config NEED_SG_DMA_LENGTH
187 config KERNEL_MODE_NEON
190 config FIX_EARLYCON_MEM
193 config PGTABLE_LEVELS
195 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
196 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
197 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
198 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
199 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
200 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
202 source "init/Kconfig"
204 source "kernel/Kconfig.freezer"
206 source "arch/arm64/Kconfig.platforms"
213 This feature enables support for PCI bus system. If you say Y
214 here, the kernel will include drivers and infrastructure code
215 to support PCI bus devices.
220 config PCI_DOMAINS_GENERIC
226 source "drivers/pci/Kconfig"
227 source "drivers/pci/pcie/Kconfig"
228 source "drivers/pci/hotplug/Kconfig"
232 menu "Kernel Features"
234 menu "ARM errata workarounds via the alternatives framework"
236 config ARM64_ERRATUM_826319
237 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
240 This option adds an alternative code sequence to work around ARM
241 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
242 AXI master interface and an L2 cache.
244 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
245 and is unable to accept a certain write via this interface, it will
246 not progress on read data presented on the read data channel and the
249 The workaround promotes data cache clean instructions to
250 data cache clean-and-invalidate.
251 Please note that this does not necessarily enable the workaround,
252 as it depends on the alternative framework, which will only patch
253 the kernel if an affected CPU is detected.
257 config ARM64_ERRATUM_827319
258 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
261 This option adds an alternative code sequence to work around ARM
262 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
263 master interface and an L2 cache.
265 Under certain conditions this erratum can cause a clean line eviction
266 to occur at the same time as another transaction to the same address
267 on the AMBA 5 CHI interface, which can cause data corruption if the
268 interconnect reorders the two transactions.
270 The workaround promotes data cache clean instructions to
271 data cache clean-and-invalidate.
272 Please note that this does not necessarily enable the workaround,
273 as it depends on the alternative framework, which will only patch
274 the kernel if an affected CPU is detected.
278 config ARM64_ERRATUM_824069
279 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
282 This option adds an alternative code sequence to work around ARM
283 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
284 to a coherent interconnect.
286 If a Cortex-A53 processor is executing a store or prefetch for
287 write instruction at the same time as a processor in another
288 cluster is executing a cache maintenance operation to the same
289 address, then this erratum might cause a clean cache line to be
290 incorrectly marked as dirty.
292 The workaround promotes data cache clean instructions to
293 data cache clean-and-invalidate.
294 Please note that this option does not necessarily enable the
295 workaround, as it depends on the alternative framework, which will
296 only patch the kernel if an affected CPU is detected.
300 config ARM64_ERRATUM_819472
301 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
304 This option adds an alternative code sequence to work around ARM
305 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
306 present when it is connected to a coherent interconnect.
308 If the processor is executing a load and store exclusive sequence at
309 the same time as a processor in another cluster is executing a cache
310 maintenance operation to the same address, then this erratum might
311 cause data corruption.
313 The workaround promotes data cache clean instructions to
314 data cache clean-and-invalidate.
315 Please note that this does not necessarily enable the workaround,
316 as it depends on the alternative framework, which will only patch
317 the kernel if an affected CPU is detected.
321 config ARM64_ERRATUM_832075
322 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
325 This option adds an alternative code sequence to work around ARM
326 erratum 832075 on Cortex-A57 parts up to r1p2.
328 Affected Cortex-A57 parts might deadlock when exclusive load/store
329 instructions to Write-Back memory are mixed with Device loads.
331 The workaround is to promote device loads to use Load-Acquire
333 Please note that this does not necessarily enable the workaround,
334 as it depends on the alternative framework, which will only patch
335 the kernel if an affected CPU is detected.
339 config ARM64_ERRATUM_834220
340 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
344 This option adds an alternative code sequence to work around ARM
345 erratum 834220 on Cortex-A57 parts up to r1p2.
347 Affected Cortex-A57 parts might report a Stage 2 translation
348 fault as the result of a Stage 1 fault for load crossing a
349 page boundary when there is a permission or device memory
350 alignment fault at Stage 1 and a translation fault at Stage 2.
352 The workaround is to verify that the Stage 1 translation
353 doesn't generate a fault before handling the Stage 2 fault.
354 Please note that this does not necessarily enable the workaround,
355 as it depends on the alternative framework, which will only patch
356 the kernel if an affected CPU is detected.
360 config ARM64_ERRATUM_845719
361 bool "Cortex-A53: 845719: a load might read incorrect data"
365 This option adds an alternative code sequence to work around ARM
366 erratum 845719 on Cortex-A53 parts up to r0p4.
368 When running a compat (AArch32) userspace on an affected Cortex-A53
369 part, a load at EL0 from a virtual address that matches the bottom 32
370 bits of the virtual address used by a recent load at (AArch64) EL1
371 might return incorrect data.
373 The workaround is to write the contextidr_el1 register on exception
374 return to a 32-bit task.
375 Please note that this does not necessarily enable the workaround,
376 as it depends on the alternative framework, which will only patch
377 the kernel if an affected CPU is detected.
381 config ARM64_ERRATUM_843419
382 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
385 select ARM64_MODULE_CMODEL_LARGE
387 This option builds kernel modules using the large memory model in
388 order to avoid the use of the ADRP instruction, which can cause
389 a subsequent memory access to use an incorrect address on Cortex-A53
392 Note that the kernel itself must be linked with a version of ld
393 which fixes potentially affected ADRP instructions through the
398 config CAVIUM_ERRATUM_22375
399 bool "Cavium erratum 22375, 24313"
402 Enable workaround for erratum 22375, 24313.
404 This implements two gicv3-its errata workarounds for ThunderX. Both
405 with small impact affecting only ITS table allocation.
407 erratum 22375: only alloc 8MB table size
408 erratum 24313: ignore memory access type
410 The fixes are in ITS initialization and basically ignore memory access
411 type and table size provided by the TYPER and BASER registers.
415 config CAVIUM_ERRATUM_23144
416 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
420 ITS SYNC command hang for cross node io and collections/cpu mapping.
424 config CAVIUM_ERRATUM_23154
425 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
428 The gicv3 of ThunderX requires a modified version for
429 reading the IAR status to ensure data synchronization
430 (access to icc_iar1_el1 is not sync'ed before and after).
434 config CAVIUM_ERRATUM_27456
435 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
438 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
439 instructions may cause the icache to become corrupted if it
440 contains data for a non-current ASID. The fix is to
441 invalidate the icache when changing the mm context.
450 default ARM64_4K_PAGES
452 Page size (translation granule) configuration.
454 config ARM64_4K_PAGES
457 This feature enables 4KB pages support.
459 config ARM64_16K_PAGES
462 The system will use 16KB pages support. AArch32 emulation
463 requires applications compiled with 16K (or a multiple of 16K)
466 config ARM64_64K_PAGES
469 This feature enables 64KB pages support (4KB by default)
470 allowing only two levels of page tables and faster TLB
471 look-up. AArch32 emulation requires applications compiled
472 with 64K aligned segments.
477 prompt "Virtual address space size"
478 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
479 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
480 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
482 Allows choosing one of multiple possible virtual address
483 space sizes. The level of translation table is determined by
484 a combination of page size and virtual address space size.
486 config ARM64_VA_BITS_36
487 bool "36-bit" if EXPERT
488 depends on ARM64_16K_PAGES
490 config ARM64_VA_BITS_39
492 depends on ARM64_4K_PAGES
494 config ARM64_VA_BITS_42
496 depends on ARM64_64K_PAGES
498 config ARM64_VA_BITS_47
500 depends on ARM64_16K_PAGES
502 config ARM64_VA_BITS_48
509 default 36 if ARM64_VA_BITS_36
510 default 39 if ARM64_VA_BITS_39
511 default 42 if ARM64_VA_BITS_42
512 default 47 if ARM64_VA_BITS_47
513 default 48 if ARM64_VA_BITS_48
515 config CPU_BIG_ENDIAN
516 bool "Build big-endian kernel"
518 Say Y if you plan on running a kernel in big-endian mode.
521 bool "Multi-core scheduler support"
523 Multi-core scheduler support improves the CPU scheduler's decision
524 making when dealing with multi-core CPU chips at a cost of slightly
525 increased overhead in some places. If unsure say N here.
528 bool "SMT scheduler support"
530 Improves the CPU scheduler's decision making when dealing with
531 MultiThreading at a cost of slightly increased overhead in some
532 places. If unsure say N here.
535 int "Maximum number of CPUs (2-4096)"
537 # These have to remain sorted largest to smallest
541 bool "Support for hot-pluggable CPUs"
542 select GENERIC_IRQ_MIGRATION
544 Say Y here to experiment with turning CPUs off and on. CPUs
545 can be controlled through /sys/devices/system/cpu.
547 source kernel/Kconfig.preempt
548 source kernel/Kconfig.hz
550 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
553 config ARCH_HAS_HOLES_MEMORYMODEL
554 def_bool y if SPARSEMEM
556 config ARCH_SPARSEMEM_ENABLE
558 select SPARSEMEM_VMEMMAP_ENABLE
560 config ARCH_SPARSEMEM_DEFAULT
561 def_bool ARCH_SPARSEMEM_ENABLE
563 config ARCH_SELECT_MEMORY_MODEL
564 def_bool ARCH_SPARSEMEM_ENABLE
566 config HAVE_ARCH_PFN_VALID
567 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
569 config HW_PERF_EVENTS
573 config SYS_SUPPORTS_HUGETLBFS
576 config ARCH_WANT_HUGE_PMD_SHARE
577 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
579 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
582 config ARCH_HAS_CACHE_LINE_SIZE
588 bool "Enable seccomp to safely compute untrusted bytecode"
590 This kernel feature is useful for number crunching applications
591 that may need to compute untrusted bytecode during their
592 execution. By using pipes or other transports made available to
593 the process as file descriptors supporting the read/write
594 syscalls, it's possible to isolate those applications in
595 their own address space using seccomp. Once seccomp is
596 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
597 and the task is only allowed to execute a few safe syscalls
598 defined by each seccomp mode.
605 bool "Xen guest support on ARM64"
606 depends on ARM64 && OF
609 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
611 config FORCE_MAX_ZONEORDER
613 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
614 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
617 The kernel memory allocator divides physically contiguous memory
618 blocks into "zones", where each zone is a power of two number of
619 pages. This option selects the largest power of two that the kernel
620 keeps in the memory allocator. If you need to allocate very large
621 blocks of physically contiguous memory, then you may need to
624 This config option is actually maximum order plus one. For example,
625 a value of 11 means that the largest free memory block is 2^10 pages.
627 We make sure that we can allocate upto a HugePage size for each configuration.
629 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
631 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
632 4M allocations matching the default size used by generic code.
634 menuconfig ARMV8_DEPRECATED
635 bool "Emulate deprecated/obsolete ARMv8 instructions"
638 Legacy software support may require certain instructions
639 that have been deprecated or obsoleted in the architecture.
641 Enable this config to enable selective emulation of these
649 bool "Emulate SWP/SWPB instructions"
651 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
652 they are always undefined. Say Y here to enable software
653 emulation of these instructions for userspace using LDXR/STXR.
655 In some older versions of glibc [<=2.8] SWP is used during futex
656 trylock() operations with the assumption that the code will not
657 be preempted. This invalid assumption may be more likely to fail
658 with SWP emulation enabled, leading to deadlock of the user
661 NOTE: when accessing uncached shared regions, LDXR/STXR rely
662 on an external transaction monitoring block called a global
663 monitor to maintain update atomicity. If your system does not
664 implement a global monitor, this option can cause programs that
665 perform SWP operations to uncached memory to deadlock.
669 config CP15_BARRIER_EMULATION
670 bool "Emulate CP15 Barrier instructions"
672 The CP15 barrier instructions - CP15ISB, CP15DSB, and
673 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
674 strongly recommended to use the ISB, DSB, and DMB
675 instructions instead.
677 Say Y here to enable software emulation of these
678 instructions for AArch32 userspace code. When this option is
679 enabled, CP15 barrier usage is traced which can help
680 identify software that needs updating.
684 config SETEND_EMULATION
685 bool "Emulate SETEND instruction"
687 The SETEND instruction alters the data-endianness of the
688 AArch32 EL0, and is deprecated in ARMv8.
690 Say Y here to enable software emulation of the instruction
691 for AArch32 userspace code.
693 Note: All the cpus on the system must have mixed endian support at EL0
694 for this feature to be enabled. If a new CPU - which doesn't support mixed
695 endian - is hotplugged in after this feature has been enabled, there could
696 be unexpected results in the applications.
701 menu "ARMv8.1 architectural features"
703 config ARM64_HW_AFDBM
704 bool "Support for hardware updates of the Access and Dirty page flags"
707 The ARMv8.1 architecture extensions introduce support for
708 hardware updates of the access and dirty information in page
709 table entries. When enabled in TCR_EL1 (HA and HD bits) on
710 capable processors, accesses to pages with PTE_AF cleared will
711 set this bit instead of raising an access flag fault.
712 Similarly, writes to read-only pages with the DBM bit set will
713 clear the read-only bit (AP[2]) instead of raising a
716 Kernels built with this configuration option enabled continue
717 to work on pre-ARMv8.1 hardware and the performance impact is
718 minimal. If unsure, say Y.
721 bool "Enable support for Privileged Access Never (PAN)"
724 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
725 prevents the kernel or hypervisor from accessing user-space (EL0)
728 Choosing this option will cause any unprotected (not using
729 copy_to_user et al) memory access to fail with a permission fault.
731 The feature is detected at runtime, and will remain as a 'nop'
732 instruction if the cpu does not implement the feature.
734 config ARM64_LSE_ATOMICS
735 bool "Atomic instructions"
737 As part of the Large System Extensions, ARMv8.1 introduces new
738 atomic instructions that are designed specifically to scale in
741 Say Y here to make use of these instructions for the in-kernel
742 atomic routines. This incurs a small overhead on CPUs that do
743 not support these instructions and requires the kernel to be
744 built with binutils >= 2.25.
749 bool "Enable support for User Access Override (UAO)"
752 User Access Override (UAO; part of the ARMv8.2 Extensions)
753 causes the 'unprivileged' variant of the load/store instructions to
754 be overriden to be privileged.
756 This option changes get_user() and friends to use the 'unprivileged'
757 variant of the load/store instructions. This ensures that user-space
758 really did have access to the supplied memory. When addr_limit is
759 set to kernel memory the UAO bit will be set, allowing privileged
760 access to kernel memory.
762 Choosing this option will cause copy_to_user() et al to use user-space
765 The feature is detected at runtime, the kernel will use the
766 regular load/store instructions if the cpu does not implement the
769 config ARM64_MODULE_CMODEL_LARGE
772 config ARM64_MODULE_PLTS
774 select ARM64_MODULE_CMODEL_LARGE
775 select HAVE_MOD_ARCH_SPECIFIC
780 This builds the kernel as a Position Independent Executable (PIE),
781 which retains all relocation metadata required to relocate the
782 kernel binary at runtime to a different virtual address than the
783 address it was linked at.
784 Since AArch64 uses the RELA relocation format, this requires a
785 relocation pass at runtime even if the kernel is loaded at the
786 same address it was linked at.
788 config RANDOMIZE_BASE
789 bool "Randomize the address of the kernel image"
790 select ARM64_MODULE_PLTS if MODULES
793 Randomizes the virtual address at which the kernel image is
794 loaded, as a security feature that deters exploit attempts
795 relying on knowledge of the location of kernel internals.
797 It is the bootloader's job to provide entropy, by passing a
798 random u64 value in /chosen/kaslr-seed at kernel entry.
800 When booting via the UEFI stub, it will invoke the firmware's
801 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
802 to the kernel proper. In addition, it will randomise the physical
803 location of the kernel Image as well.
807 config RANDOMIZE_MODULE_REGION_FULL
808 bool "Randomize the module region independently from the core kernel"
809 depends on RANDOMIZE_BASE
812 Randomizes the location of the module region without considering the
813 location of the core kernel. This way, it is impossible for modules
814 to leak information about the location of core kernel data structures
815 but it does imply that function calls between modules and the core
816 kernel will need to be resolved via veneers in the module PLT.
818 When this option is not set, the module region will be randomized over
819 a limited range that contains the [_stext, _etext] interval of the
820 core kernel, so branch relocations are always in range.
826 config ARM64_ACPI_PARKING_PROTOCOL
827 bool "Enable support for the ARM64 ACPI parking protocol"
830 Enable support for the ARM64 ACPI parking protocol. If disabled
831 the kernel will not allow booting through the ARM64 ACPI parking
832 protocol even if the corresponding data is present in the ACPI
836 string "Default kernel command string"
839 Provide a set of default command-line options at build time by
840 entering them here. As a minimum, you should specify the the
841 root device (e.g. root=/dev/nfs).
844 bool "Always use the default kernel command string"
846 Always use the default kernel command string, even if the boot
847 loader passes other arguments to the kernel.
848 This is useful if you cannot or don't want to change the
849 command-line options your boot loader passes to the kernel.
855 bool "UEFI runtime support"
856 depends on OF && !CPU_BIG_ENDIAN
859 select EFI_PARAMS_FROM_FDT
860 select EFI_RUNTIME_WRAPPERS
865 This option provides support for runtime services provided
866 by UEFI firmware (such as non-volatile variables, realtime
867 clock, and platform reset). A UEFI stub is also provided to
868 allow the kernel to be booted as an EFI application. This
869 is only useful on systems that have UEFI firmware.
872 bool "Enable support for SMBIOS (DMI) tables"
876 This enables SMBIOS/DMI feature for systems.
878 This option is only useful on systems that have UEFI firmware.
879 However, even with this option, the resultant kernel should
880 continue to boot on existing non-UEFI platforms.
884 menu "Userspace binary formats"
886 source "fs/Kconfig.binfmt"
889 bool "Kernel support for 32-bit EL0"
890 depends on ARM64_4K_PAGES || EXPERT
891 select COMPAT_BINFMT_ELF
893 select OLD_SIGSUSPEND3
894 select COMPAT_OLD_SIGACTION
896 This option enables support for a 32-bit EL0 running under a 64-bit
897 kernel at EL1. AArch32-specific components such as system calls,
898 the user helper functions, VFP support and the ptrace interface are
899 handled appropriately by the kernel.
901 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
902 that you will only be able to execute AArch32 binaries that were compiled
903 with page size aligned segments.
905 If you want to execute 32-bit userspace applications, say Y.
907 config SYSVIPC_COMPAT
909 depends on COMPAT && SYSVIPC
913 menu "Power management options"
915 source "kernel/power/Kconfig"
917 config ARCH_HIBERNATION_POSSIBLE
921 config ARCH_HIBERNATION_HEADER
923 depends on HIBERNATION
925 config ARCH_SUSPEND_POSSIBLE
930 menu "CPU Power Management"
932 source "drivers/cpuidle/Kconfig"
934 source "drivers/cpufreq/Kconfig"
940 source "drivers/Kconfig"
942 source "drivers/firmware/Kconfig"
944 source "drivers/acpi/Kconfig"
948 source "arch/arm64/kvm/Kconfig"
950 source "arch/arm64/Kconfig.debug"
952 source "security/Kconfig"
954 source "crypto/Kconfig"
956 source "arch/arm64/crypto/Kconfig"