3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
31 select GENERIC_ALLOCATOR
32 select GENERIC_CLOCKEVENTS
33 select GENERIC_CLOCKEVENTS_BROADCAST
34 select GENERIC_CPU_AUTOPROBE
35 select GENERIC_EARLY_IOREMAP
36 select GENERIC_IDLE_POLL_SETUP
37 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
39 select GENERIC_IRQ_SHOW_LEVEL
40 select GENERIC_PCI_IOMAP
41 select GENERIC_SCHED_CLOCK
42 select GENERIC_SMP_IDLE_THREAD
43 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
45 select GENERIC_TIME_VSYSCALL
46 select HANDLE_DOMAIN_IRQ
47 select HARDIRQS_SW_RESEND
48 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
49 select HAVE_ARCH_AUDITSYSCALL
50 select HAVE_ARCH_BITREVERSE
51 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
54 select HAVE_ARCH_SECCOMP_FILTER
55 select HAVE_ARCH_TRACEHOOK
57 select HAVE_C_RECORDMCOUNT
58 select HAVE_CC_STACKPROTECTOR
59 select HAVE_CMPXCHG_DOUBLE
60 select HAVE_CMPXCHG_LOCAL
61 select HAVE_DEBUG_BUGVERBOSE
62 select HAVE_DEBUG_KMEMLEAK
63 select HAVE_DMA_API_DEBUG
65 select HAVE_DMA_CONTIGUOUS
66 select HAVE_DYNAMIC_FTRACE
67 select HAVE_EFFICIENT_UNALIGNED_ACCESS
68 select HAVE_FTRACE_MCOUNT_RECORD
69 select HAVE_FUNCTION_TRACER
70 select HAVE_FUNCTION_GRAPH_TRACER
71 select HAVE_GENERIC_DMA_COHERENT
72 select HAVE_HW_BREAKPOINT if PERF_EVENTS
74 select HAVE_PATA_PLATFORM
75 select HAVE_PERF_EVENTS
77 select HAVE_PERF_USER_STACK_DUMP
78 select HAVE_REGS_AND_STACK_ACCESS_API
79 select HAVE_RCU_TABLE_FREE
80 select HAVE_SYSCALL_TRACEPOINTS
82 select HAVE_KRETPROBES if HAVE_KPROBES
83 select IOMMU_DMA if IOMMU_SUPPORT
85 select IRQ_FORCED_THREADING
86 select MODULES_USE_ELF_RELA
89 select OF_EARLY_FLATTREE
90 select OF_RESERVED_MEM
91 select PERF_USE_VMALLOC
96 select SYSCTL_EXCEPTION_TRACE
97 select HAVE_CONTEXT_TRACKING
99 ARM 64-bit (AArch64) Linux support.
104 config ARCH_PHYS_ADDR_T_64BIT
113 config STACKTRACE_SUPPORT
116 config ILLEGAL_POINTER_VALUE
118 default 0xdead000000000000
120 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
126 config RWSEM_XCHGADD_ALGORITHM
133 config GENERIC_BUG_RELATIVE_POINTERS
135 depends on GENERIC_BUG
137 config GENERIC_HWEIGHT
143 config GENERIC_CALIBRATE_DELAY
149 config HAVE_GENERIC_RCU_GUP
152 config ARCH_DMA_ADDR_T_64BIT
155 config NEED_DMA_MAP_STATE
158 config NEED_SG_DMA_LENGTH
170 config KERNEL_MODE_NEON
173 config FIX_EARLYCON_MEM
176 config PGTABLE_LEVELS
178 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
179 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
180 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
181 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
182 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
183 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
185 source "init/Kconfig"
187 source "kernel/Kconfig.freezer"
189 source "arch/arm64/Kconfig.platforms"
196 This feature enables support for PCI bus system. If you say Y
197 here, the kernel will include drivers and infrastructure code
198 to support PCI bus devices.
203 config PCI_DOMAINS_GENERIC
209 source "drivers/pci/Kconfig"
210 source "drivers/pci/pcie/Kconfig"
211 source "drivers/pci/hotplug/Kconfig"
215 menu "Kernel Features"
217 menu "ARM errata workarounds via the alternatives framework"
219 config ARM64_ERRATUM_826319
220 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
223 This option adds an alternative code sequence to work around ARM
224 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
225 AXI master interface and an L2 cache.
227 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
228 and is unable to accept a certain write via this interface, it will
229 not progress on read data presented on the read data channel and the
232 The workaround promotes data cache clean instructions to
233 data cache clean-and-invalidate.
234 Please note that this does not necessarily enable the workaround,
235 as it depends on the alternative framework, which will only patch
236 the kernel if an affected CPU is detected.
240 config ARM64_ERRATUM_827319
241 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
244 This option adds an alternative code sequence to work around ARM
245 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
246 master interface and an L2 cache.
248 Under certain conditions this erratum can cause a clean line eviction
249 to occur at the same time as another transaction to the same address
250 on the AMBA 5 CHI interface, which can cause data corruption if the
251 interconnect reorders the two transactions.
253 The workaround promotes data cache clean instructions to
254 data cache clean-and-invalidate.
255 Please note that this does not necessarily enable the workaround,
256 as it depends on the alternative framework, which will only patch
257 the kernel if an affected CPU is detected.
261 config ARM64_ERRATUM_824069
262 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
265 This option adds an alternative code sequence to work around ARM
266 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
267 to a coherent interconnect.
269 If a Cortex-A53 processor is executing a store or prefetch for
270 write instruction at the same time as a processor in another
271 cluster is executing a cache maintenance operation to the same
272 address, then this erratum might cause a clean cache line to be
273 incorrectly marked as dirty.
275 The workaround promotes data cache clean instructions to
276 data cache clean-and-invalidate.
277 Please note that this option does not necessarily enable the
278 workaround, as it depends on the alternative framework, which will
279 only patch the kernel if an affected CPU is detected.
283 config ARM64_ERRATUM_819472
284 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
287 This option adds an alternative code sequence to work around ARM
288 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
289 present when it is connected to a coherent interconnect.
291 If the processor is executing a load and store exclusive sequence at
292 the same time as a processor in another cluster is executing a cache
293 maintenance operation to the same address, then this erratum might
294 cause data corruption.
296 The workaround promotes data cache clean instructions to
297 data cache clean-and-invalidate.
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
304 config ARM64_ERRATUM_832075
305 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
308 This option adds an alternative code sequence to work around ARM
309 erratum 832075 on Cortex-A57 parts up to r1p2.
311 Affected Cortex-A57 parts might deadlock when exclusive load/store
312 instructions to Write-Back memory are mixed with Device loads.
314 The workaround is to promote device loads to use Load-Acquire
316 Please note that this does not necessarily enable the workaround,
317 as it depends on the alternative framework, which will only patch
318 the kernel if an affected CPU is detected.
322 config ARM64_ERRATUM_834220
323 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
327 This option adds an alternative code sequence to work around ARM
328 erratum 834220 on Cortex-A57 parts up to r1p2.
330 Affected Cortex-A57 parts might report a Stage 2 translation
331 fault as the result of a Stage 1 fault for load crossing a
332 page boundary when there is a permission or device memory
333 alignment fault at Stage 1 and a translation fault at Stage 2.
335 The workaround is to verify that the Stage 1 translation
336 doesn't generate a fault before handling the Stage 2 fault.
337 Please note that this does not necessarily enable the workaround,
338 as it depends on the alternative framework, which will only patch
339 the kernel if an affected CPU is detected.
343 config ARM64_ERRATUM_845719
344 bool "Cortex-A53: 845719: a load might read incorrect data"
348 This option adds an alternative code sequence to work around ARM
349 erratum 845719 on Cortex-A53 parts up to r0p4.
351 When running a compat (AArch32) userspace on an affected Cortex-A53
352 part, a load at EL0 from a virtual address that matches the bottom 32
353 bits of the virtual address used by a recent load at (AArch64) EL1
354 might return incorrect data.
356 The workaround is to write the contextidr_el1 register on exception
357 return to a 32-bit task.
358 Please note that this does not necessarily enable the workaround,
359 as it depends on the alternative framework, which will only patch
360 the kernel if an affected CPU is detected.
364 config ARM64_ERRATUM_843419
365 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
369 This option builds kernel modules using the large memory model in
370 order to avoid the use of the ADRP instruction, which can cause
371 a subsequent memory access to use an incorrect address on Cortex-A53
374 Note that the kernel itself must be linked with a version of ld
375 which fixes potentially affected ADRP instructions through the
380 config CAVIUM_ERRATUM_22375
381 bool "Cavium erratum 22375, 24313"
384 Enable workaround for erratum 22375, 24313.
386 This implements two gicv3-its errata workarounds for ThunderX. Both
387 with small impact affecting only ITS table allocation.
389 erratum 22375: only alloc 8MB table size
390 erratum 24313: ignore memory access type
392 The fixes are in ITS initialization and basically ignore memory access
393 type and table size provided by the TYPER and BASER registers.
397 config CAVIUM_ERRATUM_23144
398 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
402 ITS SYNC command hang for cross node io and collections/cpu mapping.
406 config CAVIUM_ERRATUM_23154
407 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
410 The gicv3 of ThunderX requires a modified version for
411 reading the IAR status to ensure data synchronization
412 (access to icc_iar1_el1 is not sync'ed before and after).
416 config CAVIUM_ERRATUM_27456
417 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
420 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
421 instructions may cause the icache to become corrupted if it
422 contains data for a non-current ASID. The fix is to
423 invalidate the icache when changing the mm context.
432 default ARM64_4K_PAGES
434 Page size (translation granule) configuration.
436 config ARM64_4K_PAGES
439 This feature enables 4KB pages support.
441 config ARM64_16K_PAGES
444 The system will use 16KB pages support. AArch32 emulation
445 requires applications compiled with 16K (or a multiple of 16K)
448 config ARM64_64K_PAGES
451 This feature enables 64KB pages support (4KB by default)
452 allowing only two levels of page tables and faster TLB
453 look-up. AArch32 emulation requires applications compiled
454 with 64K aligned segments.
459 prompt "Virtual address space size"
460 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
461 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
462 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
464 Allows choosing one of multiple possible virtual address
465 space sizes. The level of translation table is determined by
466 a combination of page size and virtual address space size.
468 config ARM64_VA_BITS_36
469 bool "36-bit" if EXPERT
470 depends on ARM64_16K_PAGES
472 config ARM64_VA_BITS_39
474 depends on ARM64_4K_PAGES
476 config ARM64_VA_BITS_42
478 depends on ARM64_64K_PAGES
480 config ARM64_VA_BITS_47
482 depends on ARM64_16K_PAGES
484 config ARM64_VA_BITS_48
491 default 36 if ARM64_VA_BITS_36
492 default 39 if ARM64_VA_BITS_39
493 default 42 if ARM64_VA_BITS_42
494 default 47 if ARM64_VA_BITS_47
495 default 48 if ARM64_VA_BITS_48
497 config CPU_BIG_ENDIAN
498 bool "Build big-endian kernel"
500 Say Y if you plan on running a kernel in big-endian mode.
503 bool "Multi-core scheduler support"
505 Multi-core scheduler support improves the CPU scheduler's decision
506 making when dealing with multi-core CPU chips at a cost of slightly
507 increased overhead in some places. If unsure say N here.
510 bool "SMT scheduler support"
512 Improves the CPU scheduler's decision making when dealing with
513 MultiThreading at a cost of slightly increased overhead in some
514 places. If unsure say N here.
517 int "Maximum number of CPUs (2-4096)"
519 # These have to remain sorted largest to smallest
523 bool "Support for hot-pluggable CPUs"
524 select GENERIC_IRQ_MIGRATION
526 Say Y here to experiment with turning CPUs off and on. CPUs
527 can be controlled through /sys/devices/system/cpu.
529 source kernel/Kconfig.preempt
530 source kernel/Kconfig.hz
532 config ARCH_HAS_HOLES_MEMORYMODEL
533 def_bool y if SPARSEMEM
535 config ARCH_SPARSEMEM_ENABLE
537 select SPARSEMEM_VMEMMAP_ENABLE
539 config ARCH_SPARSEMEM_DEFAULT
540 def_bool ARCH_SPARSEMEM_ENABLE
542 config ARCH_SELECT_MEMORY_MODEL
543 def_bool ARCH_SPARSEMEM_ENABLE
545 config HAVE_ARCH_PFN_VALID
546 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
548 config HW_PERF_EVENTS
552 config SYS_SUPPORTS_HUGETLBFS
555 config ARCH_WANT_GENERAL_HUGETLB
558 config ARCH_WANT_HUGE_PMD_SHARE
559 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
561 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
564 config ARCH_HAS_CACHE_LINE_SIZE
570 bool "Enable seccomp to safely compute untrusted bytecode"
572 This kernel feature is useful for number crunching applications
573 that may need to compute untrusted bytecode during their
574 execution. By using pipes or other transports made available to
575 the process as file descriptors supporting the read/write
576 syscalls, it's possible to isolate those applications in
577 their own address space using seccomp. Once seccomp is
578 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
579 and the task is only allowed to execute a few safe syscalls
580 defined by each seccomp mode.
587 bool "Xen guest support on ARM64"
588 depends on ARM64 && OF
591 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
593 config FORCE_MAX_ZONEORDER
595 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
596 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
599 The kernel memory allocator divides physically contiguous memory
600 blocks into "zones", where each zone is a power of two number of
601 pages. This option selects the largest power of two that the kernel
602 keeps in the memory allocator. If you need to allocate very large
603 blocks of physically contiguous memory, then you may need to
606 This config option is actually maximum order plus one. For example,
607 a value of 11 means that the largest free memory block is 2^10 pages.
609 We make sure that we can allocate upto a HugePage size for each configuration.
611 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
613 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
614 4M allocations matching the default size used by generic code.
616 menuconfig ARMV8_DEPRECATED
617 bool "Emulate deprecated/obsolete ARMv8 instructions"
620 Legacy software support may require certain instructions
621 that have been deprecated or obsoleted in the architecture.
623 Enable this config to enable selective emulation of these
631 bool "Emulate SWP/SWPB instructions"
633 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
634 they are always undefined. Say Y here to enable software
635 emulation of these instructions for userspace using LDXR/STXR.
637 In some older versions of glibc [<=2.8] SWP is used during futex
638 trylock() operations with the assumption that the code will not
639 be preempted. This invalid assumption may be more likely to fail
640 with SWP emulation enabled, leading to deadlock of the user
643 NOTE: when accessing uncached shared regions, LDXR/STXR rely
644 on an external transaction monitoring block called a global
645 monitor to maintain update atomicity. If your system does not
646 implement a global monitor, this option can cause programs that
647 perform SWP operations to uncached memory to deadlock.
651 config CP15_BARRIER_EMULATION
652 bool "Emulate CP15 Barrier instructions"
654 The CP15 barrier instructions - CP15ISB, CP15DSB, and
655 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
656 strongly recommended to use the ISB, DSB, and DMB
657 instructions instead.
659 Say Y here to enable software emulation of these
660 instructions for AArch32 userspace code. When this option is
661 enabled, CP15 barrier usage is traced which can help
662 identify software that needs updating.
666 config SETEND_EMULATION
667 bool "Emulate SETEND instruction"
669 The SETEND instruction alters the data-endianness of the
670 AArch32 EL0, and is deprecated in ARMv8.
672 Say Y here to enable software emulation of the instruction
673 for AArch32 userspace code.
675 Note: All the cpus on the system must have mixed endian support at EL0
676 for this feature to be enabled. If a new CPU - which doesn't support mixed
677 endian - is hotplugged in after this feature has been enabled, there could
678 be unexpected results in the applications.
683 menu "ARMv8.1 architectural features"
685 config ARM64_HW_AFDBM
686 bool "Support for hardware updates of the Access and Dirty page flags"
689 The ARMv8.1 architecture extensions introduce support for
690 hardware updates of the access and dirty information in page
691 table entries. When enabled in TCR_EL1 (HA and HD bits) on
692 capable processors, accesses to pages with PTE_AF cleared will
693 set this bit instead of raising an access flag fault.
694 Similarly, writes to read-only pages with the DBM bit set will
695 clear the read-only bit (AP[2]) instead of raising a
698 Kernels built with this configuration option enabled continue
699 to work on pre-ARMv8.1 hardware and the performance impact is
700 minimal. If unsure, say Y.
703 bool "Enable support for Privileged Access Never (PAN)"
706 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
707 prevents the kernel or hypervisor from accessing user-space (EL0)
710 Choosing this option will cause any unprotected (not using
711 copy_to_user et al) memory access to fail with a permission fault.
713 The feature is detected at runtime, and will remain as a 'nop'
714 instruction if the cpu does not implement the feature.
716 config ARM64_LSE_ATOMICS
717 bool "Atomic instructions"
719 As part of the Large System Extensions, ARMv8.1 introduces new
720 atomic instructions that are designed specifically to scale in
723 Say Y here to make use of these instructions for the in-kernel
724 atomic routines. This incurs a small overhead on CPUs that do
725 not support these instructions and requires the kernel to be
726 built with binutils >= 2.25.
735 string "Default kernel command string"
738 Provide a set of default command-line options at build time by
739 entering them here. As a minimum, you should specify the the
740 root device (e.g. root=/dev/nfs).
743 bool "Always use the default kernel command string"
745 Always use the default kernel command string, even if the boot
746 loader passes other arguments to the kernel.
747 This is useful if you cannot or don't want to change the
748 command-line options your boot loader passes to the kernel.
754 bool "UEFI runtime support"
755 depends on OF && !CPU_BIG_ENDIAN
758 select EFI_PARAMS_FROM_FDT
759 select EFI_RUNTIME_WRAPPERS
764 This option provides support for runtime services provided
765 by UEFI firmware (such as non-volatile variables, realtime
766 clock, and platform reset). A UEFI stub is also provided to
767 allow the kernel to be booted as an EFI application. This
768 is only useful on systems that have UEFI firmware.
771 bool "Enable support for SMBIOS (DMI) tables"
775 This enables SMBIOS/DMI feature for systems.
777 This option is only useful on systems that have UEFI firmware.
778 However, even with this option, the resultant kernel should
779 continue to boot on existing non-UEFI platforms.
783 menu "Userspace binary formats"
785 source "fs/Kconfig.binfmt"
788 bool "Kernel support for 32-bit EL0"
789 depends on ARM64_4K_PAGES || EXPERT
790 select COMPAT_BINFMT_ELF
792 select OLD_SIGSUSPEND3
793 select COMPAT_OLD_SIGACTION
795 This option enables support for a 32-bit EL0 running under a 64-bit
796 kernel at EL1. AArch32-specific components such as system calls,
797 the user helper functions, VFP support and the ptrace interface are
798 handled appropriately by the kernel.
800 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
801 that you will only be able to execute AArch32 binaries that were compiled
802 with page size aligned segments.
804 If you want to execute 32-bit userspace applications, say Y.
806 config SYSVIPC_COMPAT
808 depends on COMPAT && SYSVIPC
812 menu "Power management options"
814 source "kernel/power/Kconfig"
816 config ARCH_SUSPEND_POSSIBLE
821 menu "CPU Power Management"
823 source "drivers/cpuidle/Kconfig"
825 source "drivers/cpufreq/Kconfig"
831 source "drivers/Kconfig"
833 source "drivers/firmware/Kconfig"
835 source "drivers/acpi/Kconfig"
839 source "arch/arm64/kvm/Kconfig"
841 source "arch/arm64/Kconfig.debug"
843 source "security/Kconfig"
845 source "crypto/Kconfig"
847 source "arch/arm64/crypto/Kconfig"