3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HARDENED_USERCOPY
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_SECCOMP_FILTER
58 select HAVE_ARCH_TRACEHOOK
60 select HAVE_C_RECORDMCOUNT
61 select HAVE_CC_STACKPROTECTOR
62 select HAVE_CMPXCHG_DOUBLE
63 select HAVE_CMPXCHG_LOCAL
64 select HAVE_DEBUG_BUGVERBOSE
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DMA_API_DEBUG
68 select HAVE_DMA_CONTIGUOUS
69 select HAVE_DYNAMIC_FTRACE
70 select HAVE_EFFICIENT_UNALIGNED_ACCESS
71 select HAVE_FTRACE_MCOUNT_RECORD
72 select HAVE_FUNCTION_TRACER
73 select HAVE_FUNCTION_GRAPH_TRACER
74 select HAVE_GENERIC_DMA_COHERENT
75 select HAVE_HW_BREAKPOINT if PERF_EVENTS
76 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_PATA_PLATFORM
79 select HAVE_PERF_EVENTS
81 select HAVE_PERF_USER_STACK_DUMP
82 select HAVE_REGS_AND_STACK_ACCESS_API
83 select HAVE_RCU_TABLE_FREE
84 select HAVE_SYSCALL_TRACEPOINTS
86 select HAVE_KRETPROBES if HAVE_KPROBES
87 select IOMMU_DMA if IOMMU_SUPPORT
89 select IRQ_FORCED_THREADING
90 select MODULES_USE_ELF_RELA
93 select OF_EARLY_FLATTREE
94 select OF_RESERVED_MEM
95 select PERF_USE_VMALLOC
100 select SYSCTL_EXCEPTION_TRACE
101 select HAVE_CONTEXT_TRACKING
102 select HAVE_ARM_SMCCC
104 ARM 64-bit (AArch64) Linux support.
109 config ARCH_PHYS_ADDR_T_64BIT
118 config STACKTRACE_SUPPORT
121 config ILLEGAL_POINTER_VALUE
123 default 0xdead000000000000
125 config LOCKDEP_SUPPORT
128 config TRACE_IRQFLAGS_SUPPORT
131 config RWSEM_XCHGADD_ALGORITHM
138 config GENERIC_BUG_RELATIVE_POINTERS
140 depends on GENERIC_BUG
142 config GENERIC_HWEIGHT
148 config GENERIC_CALIBRATE_DELAY
154 config HAVE_GENERIC_RCU_GUP
157 config ARCH_DMA_ADDR_T_64BIT
160 config NEED_DMA_MAP_STATE
163 config NEED_SG_DMA_LENGTH
175 config KERNEL_MODE_NEON
178 config FIX_EARLYCON_MEM
181 config PGTABLE_LEVELS
183 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
184 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
185 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
186 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
187 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
188 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
190 source "init/Kconfig"
192 source "kernel/Kconfig.freezer"
194 source "arch/arm64/Kconfig.platforms"
201 This feature enables support for PCI bus system. If you say Y
202 here, the kernel will include drivers and infrastructure code
203 to support PCI bus devices.
208 config PCI_DOMAINS_GENERIC
214 source "drivers/pci/Kconfig"
215 source "drivers/pci/pcie/Kconfig"
216 source "drivers/pci/hotplug/Kconfig"
220 menu "Kernel Features"
222 menu "ARM errata workarounds via the alternatives framework"
224 config ARM64_ERRATUM_826319
225 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
228 This option adds an alternative code sequence to work around ARM
229 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
230 AXI master interface and an L2 cache.
232 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
233 and is unable to accept a certain write via this interface, it will
234 not progress on read data presented on the read data channel and the
237 The workaround promotes data cache clean instructions to
238 data cache clean-and-invalidate.
239 Please note that this does not necessarily enable the workaround,
240 as it depends on the alternative framework, which will only patch
241 the kernel if an affected CPU is detected.
245 config ARM64_ERRATUM_827319
246 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
249 This option adds an alternative code sequence to work around ARM
250 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
251 master interface and an L2 cache.
253 Under certain conditions this erratum can cause a clean line eviction
254 to occur at the same time as another transaction to the same address
255 on the AMBA 5 CHI interface, which can cause data corruption if the
256 interconnect reorders the two transactions.
258 The workaround promotes data cache clean instructions to
259 data cache clean-and-invalidate.
260 Please note that this does not necessarily enable the workaround,
261 as it depends on the alternative framework, which will only patch
262 the kernel if an affected CPU is detected.
266 config ARM64_ERRATUM_824069
267 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
270 This option adds an alternative code sequence to work around ARM
271 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
272 to a coherent interconnect.
274 If a Cortex-A53 processor is executing a store or prefetch for
275 write instruction at the same time as a processor in another
276 cluster is executing a cache maintenance operation to the same
277 address, then this erratum might cause a clean cache line to be
278 incorrectly marked as dirty.
280 The workaround promotes data cache clean instructions to
281 data cache clean-and-invalidate.
282 Please note that this option does not necessarily enable the
283 workaround, as it depends on the alternative framework, which will
284 only patch the kernel if an affected CPU is detected.
288 config ARM64_ERRATUM_819472
289 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
292 This option adds an alternative code sequence to work around ARM
293 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
294 present when it is connected to a coherent interconnect.
296 If the processor is executing a load and store exclusive sequence at
297 the same time as a processor in another cluster is executing a cache
298 maintenance operation to the same address, then this erratum might
299 cause data corruption.
301 The workaround promotes data cache clean instructions to
302 data cache clean-and-invalidate.
303 Please note that this does not necessarily enable the workaround,
304 as it depends on the alternative framework, which will only patch
305 the kernel if an affected CPU is detected.
309 config ARM64_ERRATUM_832075
310 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
313 This option adds an alternative code sequence to work around ARM
314 erratum 832075 on Cortex-A57 parts up to r1p2.
316 Affected Cortex-A57 parts might deadlock when exclusive load/store
317 instructions to Write-Back memory are mixed with Device loads.
319 The workaround is to promote device loads to use Load-Acquire
321 Please note that this does not necessarily enable the workaround,
322 as it depends on the alternative framework, which will only patch
323 the kernel if an affected CPU is detected.
327 config ARM64_ERRATUM_834220
328 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
332 This option adds an alternative code sequence to work around ARM
333 erratum 834220 on Cortex-A57 parts up to r1p2.
335 Affected Cortex-A57 parts might report a Stage 2 translation
336 fault as the result of a Stage 1 fault for load crossing a
337 page boundary when there is a permission or device memory
338 alignment fault at Stage 1 and a translation fault at Stage 2.
340 The workaround is to verify that the Stage 1 translation
341 doesn't generate a fault before handling the Stage 2 fault.
342 Please note that this does not necessarily enable the workaround,
343 as it depends on the alternative framework, which will only patch
344 the kernel if an affected CPU is detected.
348 config ARM64_ERRATUM_845719
349 bool "Cortex-A53: 845719: a load might read incorrect data"
353 This option adds an alternative code sequence to work around ARM
354 erratum 845719 on Cortex-A53 parts up to r0p4.
356 When running a compat (AArch32) userspace on an affected Cortex-A53
357 part, a load at EL0 from a virtual address that matches the bottom 32
358 bits of the virtual address used by a recent load at (AArch64) EL1
359 might return incorrect data.
361 The workaround is to write the contextidr_el1 register on exception
362 return to a 32-bit task.
363 Please note that this does not necessarily enable the workaround,
364 as it depends on the alternative framework, which will only patch
365 the kernel if an affected CPU is detected.
369 config ARM64_ERRATUM_843419
370 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
373 select ARM64_MODULE_CMODEL_LARGE
375 This option builds kernel modules using the large memory model in
376 order to avoid the use of the ADRP instruction, which can cause
377 a subsequent memory access to use an incorrect address on Cortex-A53
380 Note that the kernel itself must be linked with a version of ld
381 which fixes potentially affected ADRP instructions through the
386 config CAVIUM_ERRATUM_22375
387 bool "Cavium erratum 22375, 24313"
390 Enable workaround for erratum 22375, 24313.
392 This implements two gicv3-its errata workarounds for ThunderX. Both
393 with small impact affecting only ITS table allocation.
395 erratum 22375: only alloc 8MB table size
396 erratum 24313: ignore memory access type
398 The fixes are in ITS initialization and basically ignore memory access
399 type and table size provided by the TYPER and BASER registers.
403 config CAVIUM_ERRATUM_23144
404 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
408 ITS SYNC command hang for cross node io and collections/cpu mapping.
412 config CAVIUM_ERRATUM_23154
413 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
416 The gicv3 of ThunderX requires a modified version for
417 reading the IAR status to ensure data synchronization
418 (access to icc_iar1_el1 is not sync'ed before and after).
422 config CAVIUM_ERRATUM_27456
423 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
426 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
427 instructions may cause the icache to become corrupted if it
428 contains data for a non-current ASID. The fix is to
429 invalidate the icache when changing the mm context.
438 default ARM64_4K_PAGES
440 Page size (translation granule) configuration.
442 config ARM64_4K_PAGES
445 This feature enables 4KB pages support.
447 config ARM64_16K_PAGES
450 The system will use 16KB pages support. AArch32 emulation
451 requires applications compiled with 16K (or a multiple of 16K)
454 config ARM64_64K_PAGES
457 This feature enables 64KB pages support (4KB by default)
458 allowing only two levels of page tables and faster TLB
459 look-up. AArch32 emulation requires applications compiled
460 with 64K aligned segments.
465 prompt "Virtual address space size"
466 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
467 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
468 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
470 Allows choosing one of multiple possible virtual address
471 space sizes. The level of translation table is determined by
472 a combination of page size and virtual address space size.
474 config ARM64_VA_BITS_36
475 bool "36-bit" if EXPERT
476 depends on ARM64_16K_PAGES
478 config ARM64_VA_BITS_39
480 depends on ARM64_4K_PAGES
482 config ARM64_VA_BITS_42
484 depends on ARM64_64K_PAGES
486 config ARM64_VA_BITS_47
488 depends on ARM64_16K_PAGES
490 config ARM64_VA_BITS_48
497 default 36 if ARM64_VA_BITS_36
498 default 39 if ARM64_VA_BITS_39
499 default 42 if ARM64_VA_BITS_42
500 default 47 if ARM64_VA_BITS_47
501 default 48 if ARM64_VA_BITS_48
503 config CPU_BIG_ENDIAN
504 bool "Build big-endian kernel"
506 Say Y if you plan on running a kernel in big-endian mode.
509 bool "Multi-core scheduler support"
511 Multi-core scheduler support improves the CPU scheduler's decision
512 making when dealing with multi-core CPU chips at a cost of slightly
513 increased overhead in some places. If unsure say N here.
516 bool "SMT scheduler support"
518 Improves the CPU scheduler's decision making when dealing with
519 MultiThreading at a cost of slightly increased overhead in some
520 places. If unsure say N here.
523 int "Maximum number of CPUs (2-4096)"
525 # These have to remain sorted largest to smallest
529 bool "Support for hot-pluggable CPUs"
530 select GENERIC_IRQ_MIGRATION
532 Say Y here to experiment with turning CPUs off and on. CPUs
533 can be controlled through /sys/devices/system/cpu.
535 source kernel/Kconfig.preempt
536 source kernel/Kconfig.hz
538 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
541 config ARCH_HAS_HOLES_MEMORYMODEL
542 def_bool y if SPARSEMEM
544 config ARCH_SPARSEMEM_ENABLE
546 select SPARSEMEM_VMEMMAP_ENABLE
548 config ARCH_SPARSEMEM_DEFAULT
549 def_bool ARCH_SPARSEMEM_ENABLE
551 config ARCH_SELECT_MEMORY_MODEL
552 def_bool ARCH_SPARSEMEM_ENABLE
554 config HAVE_ARCH_PFN_VALID
555 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
557 config HW_PERF_EVENTS
561 config SYS_SUPPORTS_HUGETLBFS
564 config ARCH_WANT_HUGE_PMD_SHARE
565 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
567 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
570 config ARCH_HAS_CACHE_LINE_SIZE
576 bool "Enable seccomp to safely compute untrusted bytecode"
578 This kernel feature is useful for number crunching applications
579 that may need to compute untrusted bytecode during their
580 execution. By using pipes or other transports made available to
581 the process as file descriptors supporting the read/write
582 syscalls, it's possible to isolate those applications in
583 their own address space using seccomp. Once seccomp is
584 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
585 and the task is only allowed to execute a few safe syscalls
586 defined by each seccomp mode.
593 bool "Xen guest support on ARM64"
594 depends on ARM64 && OF
597 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
599 config FORCE_MAX_ZONEORDER
601 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
602 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
605 The kernel memory allocator divides physically contiguous memory
606 blocks into "zones", where each zone is a power of two number of
607 pages. This option selects the largest power of two that the kernel
608 keeps in the memory allocator. If you need to allocate very large
609 blocks of physically contiguous memory, then you may need to
612 This config option is actually maximum order plus one. For example,
613 a value of 11 means that the largest free memory block is 2^10 pages.
615 We make sure that we can allocate upto a HugePage size for each configuration.
617 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
619 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
620 4M allocations matching the default size used by generic code.
622 menuconfig ARMV8_DEPRECATED
623 bool "Emulate deprecated/obsolete ARMv8 instructions"
626 Legacy software support may require certain instructions
627 that have been deprecated or obsoleted in the architecture.
629 Enable this config to enable selective emulation of these
637 bool "Emulate SWP/SWPB instructions"
639 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
640 they are always undefined. Say Y here to enable software
641 emulation of these instructions for userspace using LDXR/STXR.
643 In some older versions of glibc [<=2.8] SWP is used during futex
644 trylock() operations with the assumption that the code will not
645 be preempted. This invalid assumption may be more likely to fail
646 with SWP emulation enabled, leading to deadlock of the user
649 NOTE: when accessing uncached shared regions, LDXR/STXR rely
650 on an external transaction monitoring block called a global
651 monitor to maintain update atomicity. If your system does not
652 implement a global monitor, this option can cause programs that
653 perform SWP operations to uncached memory to deadlock.
657 config CP15_BARRIER_EMULATION
658 bool "Emulate CP15 Barrier instructions"
660 The CP15 barrier instructions - CP15ISB, CP15DSB, and
661 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
662 strongly recommended to use the ISB, DSB, and DMB
663 instructions instead.
665 Say Y here to enable software emulation of these
666 instructions for AArch32 userspace code. When this option is
667 enabled, CP15 barrier usage is traced which can help
668 identify software that needs updating.
672 config SETEND_EMULATION
673 bool "Emulate SETEND instruction"
675 The SETEND instruction alters the data-endianness of the
676 AArch32 EL0, and is deprecated in ARMv8.
678 Say Y here to enable software emulation of the instruction
679 for AArch32 userspace code.
681 Note: All the cpus on the system must have mixed endian support at EL0
682 for this feature to be enabled. If a new CPU - which doesn't support mixed
683 endian - is hotplugged in after this feature has been enabled, there could
684 be unexpected results in the applications.
689 menu "ARMv8.1 architectural features"
691 config ARM64_HW_AFDBM
692 bool "Support for hardware updates of the Access and Dirty page flags"
695 The ARMv8.1 architecture extensions introduce support for
696 hardware updates of the access and dirty information in page
697 table entries. When enabled in TCR_EL1 (HA and HD bits) on
698 capable processors, accesses to pages with PTE_AF cleared will
699 set this bit instead of raising an access flag fault.
700 Similarly, writes to read-only pages with the DBM bit set will
701 clear the read-only bit (AP[2]) instead of raising a
704 Kernels built with this configuration option enabled continue
705 to work on pre-ARMv8.1 hardware and the performance impact is
706 minimal. If unsure, say Y.
709 bool "Enable support for Privileged Access Never (PAN)"
712 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
713 prevents the kernel or hypervisor from accessing user-space (EL0)
716 Choosing this option will cause any unprotected (not using
717 copy_to_user et al) memory access to fail with a permission fault.
719 The feature is detected at runtime, and will remain as a 'nop'
720 instruction if the cpu does not implement the feature.
722 config ARM64_LSE_ATOMICS
723 bool "Atomic instructions"
725 As part of the Large System Extensions, ARMv8.1 introduces new
726 atomic instructions that are designed specifically to scale in
729 Say Y here to make use of these instructions for the in-kernel
730 atomic routines. This incurs a small overhead on CPUs that do
731 not support these instructions and requires the kernel to be
732 built with binutils >= 2.25.
737 bool "Enable support for User Access Override (UAO)"
740 User Access Override (UAO; part of the ARMv8.2 Extensions)
741 causes the 'unprivileged' variant of the load/store instructions to
742 be overriden to be privileged.
744 This option changes get_user() and friends to use the 'unprivileged'
745 variant of the load/store instructions. This ensures that user-space
746 really did have access to the supplied memory. When addr_limit is
747 set to kernel memory the UAO bit will be set, allowing privileged
748 access to kernel memory.
750 Choosing this option will cause copy_to_user() et al to use user-space
753 The feature is detected at runtime, the kernel will use the
754 regular load/store instructions if the cpu does not implement the
757 config ARM64_MODULE_CMODEL_LARGE
760 config ARM64_MODULE_PLTS
762 select ARM64_MODULE_CMODEL_LARGE
763 select HAVE_MOD_ARCH_SPECIFIC
768 This builds the kernel as a Position Independent Executable (PIE),
769 which retains all relocation metadata required to relocate the
770 kernel binary at runtime to a different virtual address than the
771 address it was linked at.
772 Since AArch64 uses the RELA relocation format, this requires a
773 relocation pass at runtime even if the kernel is loaded at the
774 same address it was linked at.
776 config RANDOMIZE_BASE
777 bool "Randomize the address of the kernel image"
778 select ARM64_MODULE_PLTS if MODULES
781 Randomizes the virtual address at which the kernel image is
782 loaded, as a security feature that deters exploit attempts
783 relying on knowledge of the location of kernel internals.
785 It is the bootloader's job to provide entropy, by passing a
786 random u64 value in /chosen/kaslr-seed at kernel entry.
788 When booting via the UEFI stub, it will invoke the firmware's
789 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
790 to the kernel proper. In addition, it will randomise the physical
791 location of the kernel Image as well.
795 config RANDOMIZE_MODULE_REGION_FULL
796 bool "Randomize the module region independently from the core kernel"
797 depends on RANDOMIZE_BASE
800 Randomizes the location of the module region without considering the
801 location of the core kernel. This way, it is impossible for modules
802 to leak information about the location of core kernel data structures
803 but it does imply that function calls between modules and the core
804 kernel will need to be resolved via veneers in the module PLT.
806 When this option is not set, the module region will be randomized over
807 a limited range that contains the [_stext, _etext] interval of the
808 core kernel, so branch relocations are always in range.
814 config ARM64_ACPI_PARKING_PROTOCOL
815 bool "Enable support for the ARM64 ACPI parking protocol"
818 Enable support for the ARM64 ACPI parking protocol. If disabled
819 the kernel will not allow booting through the ARM64 ACPI parking
820 protocol even if the corresponding data is present in the ACPI
824 string "Default kernel command string"
827 Provide a set of default command-line options at build time by
828 entering them here. As a minimum, you should specify the the
829 root device (e.g. root=/dev/nfs).
832 bool "Always use the default kernel command string"
834 Always use the default kernel command string, even if the boot
835 loader passes other arguments to the kernel.
836 This is useful if you cannot or don't want to change the
837 command-line options your boot loader passes to the kernel.
843 bool "UEFI runtime support"
844 depends on OF && !CPU_BIG_ENDIAN
847 select EFI_PARAMS_FROM_FDT
848 select EFI_RUNTIME_WRAPPERS
853 This option provides support for runtime services provided
854 by UEFI firmware (such as non-volatile variables, realtime
855 clock, and platform reset). A UEFI stub is also provided to
856 allow the kernel to be booted as an EFI application. This
857 is only useful on systems that have UEFI firmware.
860 bool "Enable support for SMBIOS (DMI) tables"
864 This enables SMBIOS/DMI feature for systems.
866 This option is only useful on systems that have UEFI firmware.
867 However, even with this option, the resultant kernel should
868 continue to boot on existing non-UEFI platforms.
872 menu "Userspace binary formats"
874 source "fs/Kconfig.binfmt"
877 bool "Kernel support for 32-bit EL0"
878 depends on ARM64_4K_PAGES || EXPERT
879 select COMPAT_BINFMT_ELF
881 select OLD_SIGSUSPEND3
882 select COMPAT_OLD_SIGACTION
884 This option enables support for a 32-bit EL0 running under a 64-bit
885 kernel at EL1. AArch32-specific components such as system calls,
886 the user helper functions, VFP support and the ptrace interface are
887 handled appropriately by the kernel.
889 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
890 that you will only be able to execute AArch32 binaries that were compiled
891 with page size aligned segments.
893 If you want to execute 32-bit userspace applications, say Y.
895 config SYSVIPC_COMPAT
897 depends on COMPAT && SYSVIPC
901 menu "Power management options"
903 source "kernel/power/Kconfig"
905 config ARCH_HIBERNATION_POSSIBLE
909 config ARCH_HIBERNATION_HEADER
911 depends on HIBERNATION
913 config ARCH_SUSPEND_POSSIBLE
918 menu "CPU Power Management"
920 source "drivers/cpuidle/Kconfig"
922 source "drivers/cpufreq/Kconfig"
928 source "drivers/Kconfig"
930 source "drivers/firmware/Kconfig"
932 source "drivers/acpi/Kconfig"
936 source "arch/arm64/kvm/Kconfig"
938 source "arch/arm64/Kconfig.debug"
940 source "security/Kconfig"
942 source "crypto/Kconfig"
944 source "arch/arm64/crypto/Kconfig"