3 select ACPI_GENERIC_GSI if ACPI
4 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_GCOV_PROFILE_ALL
8 select ARCH_HAS_SG_CHAIN
9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_WANT_OPTIONAL_GPIOLIB
13 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
14 select ARCH_WANT_FRAME_POINTERS
18 select AUDIT_ARCH_COMPAT_GENERIC
19 select ARM_GIC_V2M if PCI_MSI
21 select ARM_GIC_V3_ITS if PCI_MSI
22 select BUILDTIME_EXTABLE_SORT
23 select CLONE_BACKWARDS
25 select CPU_PM if (SUSPEND || CPU_IDLE)
26 select DCACHE_WORD_ACCESS
27 select GENERIC_ALLOCATOR
28 select GENERIC_CLOCKEVENTS
29 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
30 select GENERIC_CPU_AUTOPROBE
31 select GENERIC_EARLY_IOREMAP
32 select GENERIC_IRQ_PROBE
33 select GENERIC_IRQ_SHOW
34 select GENERIC_IRQ_SHOW_LEVEL
35 select GENERIC_PCI_IOMAP
36 select GENERIC_SCHED_CLOCK
37 select GENERIC_SMP_IDLE_THREAD
38 select GENERIC_STRNCPY_FROM_USER
39 select GENERIC_STRNLEN_USER
40 select GENERIC_TIME_VSYSCALL
41 select HANDLE_DOMAIN_IRQ
42 select HARDIRQS_SW_RESEND
43 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
44 select HAVE_ARCH_AUDITSYSCALL
45 select HAVE_ARCH_BITREVERSE
46 select HAVE_ARCH_JUMP_LABEL
48 select HAVE_ARCH_SECCOMP_FILTER
49 select HAVE_ARCH_TRACEHOOK
51 select HAVE_C_RECORDMCOUNT
52 select HAVE_CC_STACKPROTECTOR
53 select HAVE_CMPXCHG_DOUBLE
54 select HAVE_DEBUG_BUGVERBOSE
55 select HAVE_DEBUG_KMEMLEAK
56 select HAVE_DMA_API_DEBUG
58 select HAVE_DMA_CONTIGUOUS
59 select HAVE_DYNAMIC_FTRACE
60 select HAVE_EFFICIENT_UNALIGNED_ACCESS
61 select HAVE_FTRACE_MCOUNT_RECORD
62 select HAVE_FUNCTION_TRACER
63 select HAVE_FUNCTION_GRAPH_TRACER
64 select HAVE_GENERIC_DMA_COHERENT
65 select HAVE_HW_BREAKPOINT if PERF_EVENTS
67 select HAVE_PATA_PLATFORM
68 select HAVE_PERF_EVENTS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE
72 select HAVE_SYSCALL_TRACEPOINTS
74 select IRQ_FORCED_THREADING
75 select MODULES_USE_ELF_RELA
78 select OF_EARLY_FLATTREE
79 select OF_RESERVED_MEM
80 select PERF_USE_VMALLOC
85 select SYSCTL_EXCEPTION_TRACE
86 select HAVE_CONTEXT_TRACKING
88 ARM 64-bit (AArch64) Linux support.
93 config ARCH_PHYS_ADDR_T_64BIT
102 config STACKTRACE_SUPPORT
105 config LOCKDEP_SUPPORT
108 config TRACE_IRQFLAGS_SUPPORT
111 config RWSEM_XCHGADD_ALGORITHM
114 config GENERIC_HWEIGHT
120 config GENERIC_CALIBRATE_DELAY
126 config HAVE_GENERIC_RCU_GUP
129 config ARCH_DMA_ADDR_T_64BIT
132 config NEED_DMA_MAP_STATE
135 config NEED_SG_DMA_LENGTH
144 config KERNEL_MODE_NEON
147 config FIX_EARLYCON_MEM
150 config PGTABLE_LEVELS
152 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
153 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
154 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
155 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
157 source "init/Kconfig"
159 source "kernel/Kconfig.freezer"
161 menu "Platform selection"
166 This enables support for Samsung Exynos SoC family
169 bool "ARMv8 based Samsung Exynos7"
171 select COMMON_CLK_SAMSUNG
172 select HAVE_S3C2410_WATCHDOG if WATCHDOG
173 select HAVE_S3C_RTC if RTC_CLASS
175 select PINCTRL_EXYNOS
178 This enables support for Samsung Exynos7 SoC family
180 config ARCH_FSL_LS2085A
181 bool "Freescale LS2085A SOC"
183 This enables support for Freescale LS2085A SOC.
186 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
190 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
193 bool "Qualcomm Platforms"
196 This enables support for the ARMv8 based Qualcomm chipsets.
199 bool "AMD Seattle SoC Family"
201 This enables support for AMD Seattle SOC Family
204 bool "NVIDIA Tegra SoC Family"
205 select ARCH_HAS_RESET_CONTROLLER
206 select ARCH_REQUIRE_GPIOLIB
210 select GENERIC_CLOCKEVENTS
213 select RESET_CONTROLLER
215 This enables support for the NVIDIA Tegra SoC family.
217 config ARCH_TEGRA_132_SOC
218 bool "NVIDIA Tegra132 SoC"
219 depends on ARCH_TEGRA
220 select PINCTRL_TEGRA124
221 select USB_ULPI if USB_PHY
222 select USB_ULPI_VIEWPORT if USB_PHY
224 Enable support for NVIDIA Tegra132 SoC, based on the Denver
225 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
226 but contains an NVIDIA Denver CPU complex in place of
227 Tegra124's "4+1" Cortex-A15 CPU complex.
230 bool "Spreadtrum SoC platform"
232 Support for Spreadtrum ARM based SoCs
235 bool "Cavium Inc. Thunder SoC Family"
237 This enables support for Cavium's Thunder Family of SoCs.
240 bool "ARMv8 software model (Versatile Express)"
241 select ARCH_REQUIRE_GPIOLIB
242 select COMMON_CLK_VERSATILE
243 select POWER_RESET_VEXPRESS
244 select VEXPRESS_CONFIG
246 This enables support for the ARMv8 software model (Versatile
250 bool "AppliedMicro X-Gene SOC Family"
252 This enables support for AppliedMicro X-Gene SOC Family
255 bool "Xilinx ZynqMP Family"
257 This enables support for Xilinx ZynqMP Family
266 This feature enables support for PCI bus system. If you say Y
267 here, the kernel will include drivers and infrastructure code
268 to support PCI bus devices.
273 config PCI_DOMAINS_GENERIC
279 source "drivers/pci/Kconfig"
280 source "drivers/pci/pcie/Kconfig"
281 source "drivers/pci/hotplug/Kconfig"
285 menu "Kernel Features"
287 menu "ARM errata workarounds via the alternatives framework"
289 config ARM64_ERRATUM_826319
290 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
293 This option adds an alternative code sequence to work around ARM
294 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
295 AXI master interface and an L2 cache.
297 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
298 and is unable to accept a certain write via this interface, it will
299 not progress on read data presented on the read data channel and the
302 The workaround promotes data cache clean instructions to
303 data cache clean-and-invalidate.
304 Please note that this does not necessarily enable the workaround,
305 as it depends on the alternative framework, which will only patch
306 the kernel if an affected CPU is detected.
310 config ARM64_ERRATUM_827319
311 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
314 This option adds an alternative code sequence to work around ARM
315 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
316 master interface and an L2 cache.
318 Under certain conditions this erratum can cause a clean line eviction
319 to occur at the same time as another transaction to the same address
320 on the AMBA 5 CHI interface, which can cause data corruption if the
321 interconnect reorders the two transactions.
323 The workaround promotes data cache clean instructions to
324 data cache clean-and-invalidate.
325 Please note that this does not necessarily enable the workaround,
326 as it depends on the alternative framework, which will only patch
327 the kernel if an affected CPU is detected.
331 config ARM64_ERRATUM_824069
332 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
335 This option adds an alternative code sequence to work around ARM
336 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
337 to a coherent interconnect.
339 If a Cortex-A53 processor is executing a store or prefetch for
340 write instruction at the same time as a processor in another
341 cluster is executing a cache maintenance operation to the same
342 address, then this erratum might cause a clean cache line to be
343 incorrectly marked as dirty.
345 The workaround promotes data cache clean instructions to
346 data cache clean-and-invalidate.
347 Please note that this option does not necessarily enable the
348 workaround, as it depends on the alternative framework, which will
349 only patch the kernel if an affected CPU is detected.
353 config ARM64_ERRATUM_819472
354 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
357 This option adds an alternative code sequence to work around ARM
358 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
359 present when it is connected to a coherent interconnect.
361 If the processor is executing a load and store exclusive sequence at
362 the same time as a processor in another cluster is executing a cache
363 maintenance operation to the same address, then this erratum might
364 cause data corruption.
366 The workaround promotes data cache clean instructions to
367 data cache clean-and-invalidate.
368 Please note that this does not necessarily enable the workaround,
369 as it depends on the alternative framework, which will only patch
370 the kernel if an affected CPU is detected.
374 config ARM64_ERRATUM_832075
375 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
378 This option adds an alternative code sequence to work around ARM
379 erratum 832075 on Cortex-A57 parts up to r1p2.
381 Affected Cortex-A57 parts might deadlock when exclusive load/store
382 instructions to Write-Back memory are mixed with Device loads.
384 The workaround is to promote device loads to use Load-Acquire
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_845719
393 bool "Cortex-A53: 845719: a load might read incorrect data"
397 This option adds an alternative code sequence to work around ARM
398 erratum 845719 on Cortex-A53 parts up to r0p4.
400 When running a compat (AArch32) userspace on an affected Cortex-A53
401 part, a load at EL0 from a virtual address that matches the bottom 32
402 bits of the virtual address used by a recent load at (AArch64) EL1
403 might return incorrect data.
405 The workaround is to write the contextidr_el1 register on exception
406 return to a 32-bit task.
407 Please note that this does not necessarily enable the workaround,
408 as it depends on the alternative framework, which will only patch
409 the kernel if an affected CPU is detected.
418 default ARM64_4K_PAGES
420 Page size (translation granule) configuration.
422 config ARM64_4K_PAGES
425 This feature enables 4KB pages support.
427 config ARM64_64K_PAGES
430 This feature enables 64KB pages support (4KB by default)
431 allowing only two levels of page tables and faster TLB
432 look-up. AArch32 emulation is not available when this feature
438 prompt "Virtual address space size"
439 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
440 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
442 Allows choosing one of multiple possible virtual address
443 space sizes. The level of translation table is determined by
444 a combination of page size and virtual address space size.
446 config ARM64_VA_BITS_39
448 depends on ARM64_4K_PAGES
450 config ARM64_VA_BITS_42
452 depends on ARM64_64K_PAGES
454 config ARM64_VA_BITS_48
461 default 39 if ARM64_VA_BITS_39
462 default 42 if ARM64_VA_BITS_42
463 default 48 if ARM64_VA_BITS_48
465 config CPU_BIG_ENDIAN
466 bool "Build big-endian kernel"
468 Say Y if you plan on running a kernel in big-endian mode.
471 bool "Symmetric Multi-Processing"
473 This enables support for systems with more than one CPU. If
474 you say N here, the kernel will run on single and
475 multiprocessor machines, but will use only one CPU of a
476 multiprocessor machine. If you say Y here, the kernel will run
477 on many, but not all, single processor machines. On a single
478 processor machine, the kernel will run faster if you say N
481 If you don't know what to do here, say N.
484 bool "Multi-core scheduler support"
487 Multi-core scheduler support improves the CPU scheduler's decision
488 making when dealing with multi-core CPU chips at a cost of slightly
489 increased overhead in some places. If unsure say N here.
492 bool "SMT scheduler support"
495 Improves the CPU scheduler's decision making when dealing with
496 MultiThreading at a cost of slightly increased overhead in some
497 places. If unsure say N here.
500 int "Maximum number of CPUs (2-4096)"
503 # These have to remain sorted largest to smallest
507 bool "Support for hot-pluggable CPUs"
510 Say Y here to experiment with turning CPUs off and on. CPUs
511 can be controlled through /sys/devices/system/cpu.
513 source kernel/Kconfig.preempt
523 config ARCH_HAS_HOLES_MEMORYMODEL
524 def_bool y if SPARSEMEM
526 config ARCH_SPARSEMEM_ENABLE
528 select SPARSEMEM_VMEMMAP_ENABLE
530 config ARCH_SPARSEMEM_DEFAULT
531 def_bool ARCH_SPARSEMEM_ENABLE
533 config ARCH_SELECT_MEMORY_MODEL
534 def_bool ARCH_SPARSEMEM_ENABLE
536 config HAVE_ARCH_PFN_VALID
537 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
539 config HW_PERF_EVENTS
540 bool "Enable hardware performance counter support for perf events"
541 depends on PERF_EVENTS
544 Enable hardware performance counter support for perf events. If
545 disabled, perf events will use software events only.
547 config SYS_SUPPORTS_HUGETLBFS
550 config ARCH_WANT_GENERAL_HUGETLB
553 config ARCH_WANT_HUGE_PMD_SHARE
554 def_bool y if !ARM64_64K_PAGES
556 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
559 config ARCH_HAS_CACHE_LINE_SIZE
565 bool "Enable seccomp to safely compute untrusted bytecode"
567 This kernel feature is useful for number crunching applications
568 that may need to compute untrusted bytecode during their
569 execution. By using pipes or other transports made available to
570 the process as file descriptors supporting the read/write
571 syscalls, it's possible to isolate those applications in
572 their own address space using seccomp. Once seccomp is
573 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
574 and the task is only allowed to execute a few safe syscalls
575 defined by each seccomp mode.
582 bool "Xen guest support on ARM64"
583 depends on ARM64 && OF
586 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
588 config FORCE_MAX_ZONEORDER
590 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
593 menuconfig ARMV8_DEPRECATED
594 bool "Emulate deprecated/obsolete ARMv8 instructions"
597 Legacy software support may require certain instructions
598 that have been deprecated or obsoleted in the architecture.
600 Enable this config to enable selective emulation of these
608 bool "Emulate SWP/SWPB instructions"
610 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
611 they are always undefined. Say Y here to enable software
612 emulation of these instructions for userspace using LDXR/STXR.
614 In some older versions of glibc [<=2.8] SWP is used during futex
615 trylock() operations with the assumption that the code will not
616 be preempted. This invalid assumption may be more likely to fail
617 with SWP emulation enabled, leading to deadlock of the user
620 NOTE: when accessing uncached shared regions, LDXR/STXR rely
621 on an external transaction monitoring block called a global
622 monitor to maintain update atomicity. If your system does not
623 implement a global monitor, this option can cause programs that
624 perform SWP operations to uncached memory to deadlock.
628 config CP15_BARRIER_EMULATION
629 bool "Emulate CP15 Barrier instructions"
631 The CP15 barrier instructions - CP15ISB, CP15DSB, and
632 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
633 strongly recommended to use the ISB, DSB, and DMB
634 instructions instead.
636 Say Y here to enable software emulation of these
637 instructions for AArch32 userspace code. When this option is
638 enabled, CP15 barrier usage is traced which can help
639 identify software that needs updating.
643 config SETEND_EMULATION
644 bool "Emulate SETEND instruction"
646 The SETEND instruction alters the data-endianness of the
647 AArch32 EL0, and is deprecated in ARMv8.
649 Say Y here to enable software emulation of the instruction
650 for AArch32 userspace code.
652 Note: All the cpus on the system must have mixed endian support at EL0
653 for this feature to be enabled. If a new CPU - which doesn't support mixed
654 endian - is hotplugged in after this feature has been enabled, there could
655 be unexpected results in the applications.
665 string "Default kernel command string"
668 Provide a set of default command-line options at build time by
669 entering them here. As a minimum, you should specify the the
670 root device (e.g. root=/dev/nfs).
673 bool "Always use the default kernel command string"
675 Always use the default kernel command string, even if the boot
676 loader passes other arguments to the kernel.
677 This is useful if you cannot or don't want to change the
678 command-line options your boot loader passes to the kernel.
684 bool "UEFI runtime support"
685 depends on OF && !CPU_BIG_ENDIAN
688 select EFI_PARAMS_FROM_FDT
689 select EFI_RUNTIME_WRAPPERS
694 This option provides support for runtime services provided
695 by UEFI firmware (such as non-volatile variables, realtime
696 clock, and platform reset). A UEFI stub is also provided to
697 allow the kernel to be booted as an EFI application. This
698 is only useful on systems that have UEFI firmware.
701 bool "Enable support for SMBIOS (DMI) tables"
705 This enables SMBIOS/DMI feature for systems.
707 This option is only useful on systems that have UEFI firmware.
708 However, even with this option, the resultant kernel should
709 continue to boot on existing non-UEFI platforms.
713 menu "Userspace binary formats"
715 source "fs/Kconfig.binfmt"
718 bool "Kernel support for 32-bit EL0"
719 depends on !ARM64_64K_PAGES || EXPERT
720 select COMPAT_BINFMT_ELF
722 select OLD_SIGSUSPEND3
723 select COMPAT_OLD_SIGACTION
725 This option enables support for a 32-bit EL0 running under a 64-bit
726 kernel at EL1. AArch32-specific components such as system calls,
727 the user helper functions, VFP support and the ptrace interface are
728 handled appropriately by the kernel.
730 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
731 will only be able to execute AArch32 binaries that were compiled with
732 64k aligned segments.
734 If you want to execute 32-bit userspace applications, say Y.
736 config SYSVIPC_COMPAT
738 depends on COMPAT && SYSVIPC
742 menu "Power management options"
744 source "kernel/power/Kconfig"
746 config ARCH_SUSPEND_POSSIBLE
751 menu "CPU Power Management"
753 source "drivers/cpuidle/Kconfig"
755 source "drivers/cpufreq/Kconfig"
761 source "drivers/Kconfig"
763 source "drivers/firmware/Kconfig"
765 source "drivers/acpi/Kconfig"
769 source "arch/arm64/kvm/Kconfig"
771 source "arch/arm64/Kconfig.debug"
773 source "security/Kconfig"
775 source "crypto/Kconfig"
777 source "arch/arm64/crypto/Kconfig"