arch/arm64/boot/dts/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                 };
  29                 cpu@001 {
  30                         device_type = "cpu";
  31                         compatible = "apm,potenza", "arm,armv8";
  32                         reg = <0x0 0x001>;
  33                         enable-method = "spin-table";
  34                         cpu-release-addr = <0x1 0x0000fff8>;
  35                 };
  36                 cpu@100 {
  37                         device_type = "cpu";
  38                         compatible = "apm,potenza", "arm,armv8";
  39                         reg = <0x0 0x100>;
  40                         enable-method = "spin-table";
  41                         cpu-release-addr = <0x1 0x0000fff8>;
  42                 };
  43                 cpu@101 {
  44                         device_type = "cpu";
  45                         compatible = "apm,potenza", "arm,armv8";
  46                         reg = <0x0 0x101>;
  47                         enable-method = "spin-table";
  48                         cpu-release-addr = <0x1 0x0000fff8>;
  49                 };
  50                 cpu@200 {
  51                         device_type = "cpu";
  52                         compatible = "apm,potenza", "arm,armv8";
  53                         reg = <0x0 0x200>;
  54                         enable-method = "spin-table";
  55                         cpu-release-addr = <0x1 0x0000fff8>;
  56                 };
  57                 cpu@201 {
  58                         device_type = "cpu";
  59                         compatible = "apm,potenza", "arm,armv8";
  60                         reg = <0x0 0x201>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0x1 0x0000fff8>;
  63                 };
  64                 cpu@300 {
  65                         device_type = "cpu";
  66                         compatible = "apm,potenza", "arm,armv8";
  67                         reg = <0x0 0x300>;
  68                         enable-method = "spin-table";
  69                         cpu-release-addr = <0x1 0x0000fff8>;
  70                 };
  71                 cpu@301 {
  72                         device_type = "cpu";
  73                         compatible = "apm,potenza", "arm,armv8";
  74                         reg = <0x0 0x301>;
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0x1 0x0000fff8>;
  77                 };
  78         };
  79
  80         gic: interrupt-controller@78010000 {
  81                 compatible = "arm,cortex-a15-gic";
  82                 #interrupt-cells = <3>;
  83                 interrupt-controller;
  84                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
  85                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
  86                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
  87                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
  88                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
  94                              <1 13 0xff01>,     /* Non-secure Phys IRQ */
  95                              <1 14 0xff01>,     /* Virt IRQ */
  96                              <1 15 0xff01>;     /* Hyp IRQ */
  97                 clock-frequency = <50000000>;
  98         };
  99
 100         soc {
 101                 compatible = "simple-bus";
 102                 #address-cells = <2>;
 103                 #size-cells = <2>;
 104                 ranges;
 105
 106                 clocks {
 107                         #address-cells = <2>;
 108                         #size-cells = <2>;
 109                         ranges;
 110                         refclk: refclk {
 111                                 compatible = "fixed-clock";
 112                                 #clock-cells = <1>;
 113                                 clock-frequency = <100000000>;
 114                                 clock-output-names = "refclk";
 115                         };
 116
 117                         pcppll: pcppll@17000100 {
 118                                 compatible = "apm,xgene-pcppll-clock";
 119                                 #clock-cells = <1>;
 120                                 clocks = <&refclk 0>;
 121                                 clock-names = "pcppll";
 122                                 reg = <0x0 0x17000100 0x0 0x1000>;
 123                                 clock-output-names = "pcppll";
 124                                 type = <0>;
 125                         };
 126
 127                         socpll: socpll@17000120 {
 128                                 compatible = "apm,xgene-socpll-clock";
 129                                 #clock-cells = <1>;
 130                                 clocks = <&refclk 0>;
 131                                 clock-names = "socpll";
 132                                 reg = <0x0 0x17000120 0x0 0x1000>;
 133                                 clock-output-names = "socpll";
 134                                 type = <1>;
 135                         };
 136
 137                         socplldiv2: socplldiv2  {
 138                                 compatible = "fixed-factor-clock";
 139                                 #clock-cells = <1>;
 140                                 clocks = <&socpll 0>;
 141                                 clock-names = "socplldiv2";
 142                                 clock-mult = <1>;
 143                                 clock-div = <2>;
 144                                 clock-output-names = "socplldiv2";
 145                         };
 146
 147                         qmlclk: qmlclk {
 148                                 compatible = "apm,xgene-device-clock";
 149                                 #clock-cells = <1>;
 150                                 clocks = <&socplldiv2 0>;
 151                                 clock-names = "qmlclk";
 152                                 reg = <0x0 0x1703C000 0x0 0x1000>;
 153                                 reg-names = "csr-reg";
 154                                 clock-output-names = "qmlclk";
 155                         };
 156
 157                         ethclk: ethclk {
 158                                 compatible = "apm,xgene-device-clock";
 159                                 #clock-cells = <1>;
 160                                 clocks = <&socplldiv2 0>;
 161                                 clock-names = "ethclk";
 162                                 reg = <0x0 0x17000000 0x0 0x1000>;
 163                                 reg-names = "div-reg";
 164                                 divider-offset = <0x238>;
 165                                 divider-width = <0x9>;
 166                                 divider-shift = <0x0>;
 167                                 clock-output-names = "ethclk";
 168                         };
 169
 170                         menetclk: menetclk {
 171                                 compatible = "apm,xgene-device-clock";
 172                                 #clock-cells = <1>;
 173                                 clocks = <&ethclk 0>;
 174                                 reg = <0x0 0x1702C000 0x0 0x1000>;
 175                                 reg-names = "csr-reg";
 176                                 clock-output-names = "menetclk";
 177                         };
 178
 179                         sge0clk: sge0clk@1f21c000 {
 180                                 compatible = "apm,xgene-device-clock";
 181                                 #clock-cells = <1>;
 182                                 clocks = <&socplldiv2 0>;
 183                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 184                                 reg-names = "csr-reg";
 185                                 csr-mask = <0x3>;
 186                                 clock-output-names = "sge0clk";
 187                         };
 188
 189                         xge0clk: xge0clk@1f61c000 {
 190                                 compatible = "apm,xgene-device-clock";
 191                                 #clock-cells = <1>;
 192                                 clocks = <&socplldiv2 0>;
 193                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 194                                 reg-names = "csr-reg";
 195                                 csr-mask = <0x3>;
 196                                 clock-output-names = "xge0clk";
 197                         };
 198
 199                         sataphy1clk: sataphy1clk@1f21c000 {
 200                                 compatible = "apm,xgene-device-clock";
 201                                 #clock-cells = <1>;
 202                                 clocks = <&socplldiv2 0>;
 203                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 204                                 reg-names = "csr-reg";
 205                                 clock-output-names = "sataphy1clk";
 206                                 status = "disabled";
 207                                 csr-offset = <0x4>;
 208                                 csr-mask = <0x00>;
 209                                 enable-offset = <0x0>;
 210                                 enable-mask = <0x06>;
 211                         };
 212
 213                         sataphy2clk: sataphy1clk@1f22c000 {
 214                                 compatible = "apm,xgene-device-clock";
 215                                 #clock-cells = <1>;
 216                                 clocks = <&socplldiv2 0>;
 217                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 218                                 reg-names = "csr-reg";
 219                                 clock-output-names = "sataphy2clk";
 220                                 status = "ok";
 221                                 csr-offset = <0x4>;
 222                                 csr-mask = <0x3a>;
 223                                 enable-offset = <0x0>;
 224                                 enable-mask = <0x06>;
 225                         };
 226
 227                         sataphy3clk: sataphy1clk@1f23c000 {
 228                                 compatible = "apm,xgene-device-clock";
 229                                 #clock-cells = <1>;
 230                                 clocks = <&socplldiv2 0>;
 231                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 232                                 reg-names = "csr-reg";
 233                                 clock-output-names = "sataphy3clk";
 234                                 status = "ok";
 235                                 csr-offset = <0x4>;
 236                                 csr-mask = <0x3a>;
 237                                 enable-offset = <0x0>;
 238                                 enable-mask = <0x06>;
 239                         };
 240
 241                         sata01clk: sata01clk@1f21c000 {
 242                                 compatible = "apm,xgene-device-clock";
 243                                 #clock-cells = <1>;
 244                                 clocks = <&socplldiv2 0>;
 245                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 246                                 reg-names = "csr-reg";
 247                                 clock-output-names = "sata01clk";
 248                                 csr-offset = <0x4>;
 249                                 csr-mask = <0x05>;
 250                                 enable-offset = <0x0>;
 251                                 enable-mask = <0x39>;
 252                         };
 253
 254                         sata23clk: sata23clk@1f22c000 {
 255                                 compatible = "apm,xgene-device-clock";
 256                                 #clock-cells = <1>;
 257                                 clocks = <&socplldiv2 0>;
 258                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 259                                 reg-names = "csr-reg";
 260                                 clock-output-names = "sata23clk";
 261                                 csr-offset = <0x4>;
 262                                 csr-mask = <0x05>;
 263                                 enable-offset = <0x0>;
 264                                 enable-mask = <0x39>;
 265                         };
 266
 267                         sata45clk: sata45clk@1f23c000 {
 268                                 compatible = "apm,xgene-device-clock";
 269                                 #clock-cells = <1>;
 270                                 clocks = <&socplldiv2 0>;
 271                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 272                                 reg-names = "csr-reg";
 273                                 clock-output-names = "sata45clk";
 274                                 csr-offset = <0x4>;
 275                                 csr-mask = <0x05>;
 276                                 enable-offset = <0x0>;
 277                                 enable-mask = <0x39>;
 278                         };
 279
 280                         rtcclk: rtcclk@17000000 {
 281                                 compatible = "apm,xgene-device-clock";
 282                                 #clock-cells = <1>;
 283                                 clocks = <&socplldiv2 0>;
 284                                 reg = <0x0 0x17000000 0x0 0x2000>;
 285                                 reg-names = "csr-reg";
 286                                 csr-offset = <0xc>;
 287                                 csr-mask = <0x2>;
 288                                 enable-offset = <0x10>;
 289                                 enable-mask = <0x2>;
 290                                 clock-output-names = "rtcclk";
 291                         };
 292
 293                         rngpkaclk: rngpkaclk@17000000 {
 294                                 compatible = "apm,xgene-device-clock";
 295                                 #clock-cells = <1>;
 296                                 clocks = <&socplldiv2 0>;
 297                                 reg = <0x0 0x17000000 0x0 0x2000>;
 298                                 reg-names = "csr-reg";
 299                                 csr-offset = <0xc>;
 300                                 csr-mask = <0x10>;
 301                                 enable-offset = <0x10>;
 302                                 enable-mask = <0x10>;
 303                                 clock-output-names = "rngpkaclk";
 304                         };
 305                 };
 306
 307                 serial0: serial@1c020000 {
 308                         status = "disabled";
 309                         device_type = "serial";
 310                         compatible = "ns16550a";
 311                         reg = <0 0x1c020000 0x0 0x1000>;
 312                         reg-shift = <2>;
 313                         clock-frequency = <10000000>; /* Updated by bootloader */
 314                         interrupt-parent = <&gic>;
 315                         interrupts = <0x0 0x4c 0x4>;
 316                 };
 317
 318                 serial1: serial@1c021000 {
 319                         status = "disabled";
 320                         device_type = "serial";
 321                         compatible = "ns16550a";
 322                         reg = <0 0x1c021000 0x0 0x1000>;
 323                         reg-shift = <2>;
 324                         clock-frequency = <10000000>; /* Updated by bootloader */
 325                         interrupt-parent = <&gic>;
 326                         interrupts = <0x0 0x4d 0x4>;
 327                 };
 328
 329                 serial2: serial@1c022000 {
 330                         status = "disabled";
 331                         device_type = "serial";
 332                         compatible = "ns16550a";
 333                         reg = <0 0x1c022000 0x0 0x1000>;
 334                         reg-shift = <2>;
 335                         clock-frequency = <10000000>; /* Updated by bootloader */
 336                         interrupt-parent = <&gic>;
 337                         interrupts = <0x0 0x4e 0x4>;
 338                 };
 339
 340                 serial3: serial@1c023000 {
 341                         status = "disabled";
 342                         device_type = "serial";
 343                         compatible = "ns16550a";
 344                         reg = <0 0x1c023000 0x0 0x1000>;
 345                         reg-shift = <2>;
 346                         clock-frequency = <10000000>; /* Updated by bootloader */
 347                         interrupt-parent = <&gic>;
 348                         interrupts = <0x0 0x4f 0x4>;
 349                 };
 350
 351                 phy1: phy@1f21a000 {
 352                         compatible = "apm,xgene-phy";
 353                         reg = <0x0 0x1f21a000 0x0 0x100>;
 354                         #phy-cells = <1>;
 355                         clocks = <&sataphy1clk 0>;
 356                         status = "disabled";
 357                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 358                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 359                 };
 360
 361                 phy2: phy@1f22a000 {
 362                         compatible = "apm,xgene-phy";
 363                         reg = <0x0 0x1f22a000 0x0 0x100>;
 364                         #phy-cells = <1>;
 365                         clocks = <&sataphy2clk 0>;
 366                         status = "ok";
 367                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 368                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 369                 };
 370
 371                 phy3: phy@1f23a000 {
 372                         compatible = "apm,xgene-phy";
 373                         reg = <0x0 0x1f23a000 0x0 0x100>;
 374                         #phy-cells = <1>;
 375                         clocks = <&sataphy3clk 0>;
 376                         status = "ok";
 377                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 378                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 379                 };
 380
 381                 sata1: sata@1a000000 {
 382                         compatible = "apm,xgene-ahci";
 383                         reg = <0x0 0x1a000000 0x0 0x1000>,
 384                               <0x0 0x1f210000 0x0 0x1000>,
 385                               <0x0 0x1f21d000 0x0 0x1000>,
 386                               <0x0 0x1f21e000 0x0 0x1000>,
 387                               <0x0 0x1f217000 0x0 0x1000>;
 388                         interrupts = <0x0 0x86 0x4>;
 389                         dma-coherent;
 390                         status = "disabled";
 391                         clocks = <&sata01clk 0>;
 392                         phys = <&phy1 0>;
 393                         phy-names = "sata-phy";
 394                 };
 395
 396                 sata2: sata@1a400000 {
 397                         compatible = "apm,xgene-ahci";
 398                         reg = <0x0 0x1a400000 0x0 0x1000>,
 399                               <0x0 0x1f220000 0x0 0x1000>,
 400                               <0x0 0x1f22d000 0x0 0x1000>,
 401                               <0x0 0x1f22e000 0x0 0x1000>,
 402                               <0x0 0x1f227000 0x0 0x1000>;
 403                         interrupts = <0x0 0x87 0x4>;
 404                         dma-coherent;
 405                         status = "ok";
 406                         clocks = <&sata23clk 0>;
 407                         phys = <&phy2 0>;
 408                         phy-names = "sata-phy";
 409                 };
 410
 411                 sata3: sata@1a800000 {
 412                         compatible = "apm,xgene-ahci";
 413                         reg = <0x0 0x1a800000 0x0 0x1000>,
 414                               <0x0 0x1f230000 0x0 0x1000>,
 415                               <0x0 0x1f23d000 0x0 0x1000>,
 416                               <0x0 0x1f23e000 0x0 0x1000>;
 417                         interrupts = <0x0 0x88 0x4>;
 418                         dma-coherent;
 419                         status = "ok";
 420                         clocks = <&sata45clk 0>;
 421                         phys = <&phy3 0>;
 422                         phy-names = "sata-phy";
 423                 };
 424
 425                 rtc: rtc@10510000 {
 426                         compatible = "apm,xgene-rtc";
 427                         reg = <0x0 0x10510000 0x0 0x400>;
 428                         interrupts = <0x0 0x46 0x4>;
 429                         #clock-cells = <1>;
 430                         clocks = <&rtcclk 0>;
 431                 };
 432
 433                 menet: ethernet@17020000 {
 434                         compatible = "apm,xgene-enet";
 435                         status = "disabled";
 436                         reg = <0x0 0x17020000 0x0 0xd100>,
 437                               <0x0 0X17030000 0x0 0X400>,
 438                               <0x0 0X10000000 0x0 0X200>;
 439                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 440                         interrupts = <0x0 0x3c 0x4>;
 441                         dma-coherent;
 442                         clocks = <&menetclk 0>;
 443                         /* mac address will be overwritten by the bootloader */
 444                         local-mac-address = [00 00 00 00 00 00];
 445                         phy-connection-type = "rgmii";
 446                         phy-handle = <&menetphy>;
 447                         mdio {
 448                                 compatible = "apm,xgene-mdio";
 449                                 #address-cells = <1>;
 450                                 #size-cells = <0>;
 451                                 menetphy: menetphy@3 {
 452                                         compatible = "ethernet-phy-id001c.c915";
 453                                         reg = <0x3>;
 454                                 };
 455
 456                         };
 457                 };
 458
 459                 sgenet0: ethernet@1f210000 {
 460                         compatible = "apm,xgene-enet";
 461                         status = "disabled";
 462                         reg = <0x0 0x1f210000 0x0 0x10000>,
 463                               <0x0 0x1f200000 0x0 0X10000>,
 464                               <0x0 0x1B000000 0x0 0X20000>;
 465                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 466                         interrupts = <0x0 0xA0 0x4>;
 467                         dma-coherent;
 468                         clocks = <&sge0clk 0>;
 469                         local-mac-address = [00 00 00 00 00 00];
 470                         phy-connection-type = "sgmii";
 471                 };
 472
 473                 xgenet: ethernet@1f610000 {
 474                         compatible = "apm,xgene-enet";
 475                         status = "disabled";
 476                         reg = <0x0 0x1f610000 0x0 0xd100>,
 477                               <0x0 0x1f600000 0x0 0X400>,
 478                               <0x0 0x18000000 0x0 0X200>;
 479                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 480                         interrupts = <0x0 0x60 0x4>;
 481                         dma-coherent;
 482                         clocks = <&xge0clk 0>;
 483                         /* mac address will be overwritten by the bootloader */
 484                         local-mac-address = [00 00 00 00 00 00];
 485                         phy-connection-type = "xgmii";
 486                 };
 487
 488                 rng: rng@10520000 {
 489                         compatible = "apm,xgene-rng";
 490                         reg = <0x0 0x10520000 0x0 0x100>;
 491                         interrupts = <0x0 0x41 0x4>;
 492                         clocks = <&rngpkaclk 0>;
 493                 };
 494         };
 495 };