2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
107 #address-cells = <2>;
111 compatible = "fixed-clock";
113 clock-frequency = <100000000>;
114 clock-output-names = "refclk";
117 pcppll: pcppll@17000100 {
118 compatible = "apm,xgene-pcppll-clock";
120 clocks = <&refclk 0>;
121 clock-names = "pcppll";
122 reg = <0x0 0x17000100 0x0 0x1000>;
123 clock-output-names = "pcppll";
127 socpll: socpll@17000120 {
128 compatible = "apm,xgene-socpll-clock";
130 clocks = <&refclk 0>;
131 clock-names = "socpll";
132 reg = <0x0 0x17000120 0x0 0x1000>;
133 clock-output-names = "socpll";
137 socplldiv2: socplldiv2 {
138 compatible = "fixed-factor-clock";
140 clocks = <&socpll 0>;
141 clock-names = "socplldiv2";
144 clock-output-names = "socplldiv2";
148 compatible = "apm,xgene-device-clock";
150 clocks = <&socplldiv2 0>;
151 clock-names = "qmlclk";
152 reg = <0x0 0x1703C000 0x0 0x1000>;
153 reg-names = "csr-reg";
154 clock-output-names = "qmlclk";
158 compatible = "apm,xgene-device-clock";
160 clocks = <&socplldiv2 0>;
161 clock-names = "ethclk";
162 reg = <0x0 0x17000000 0x0 0x1000>;
163 reg-names = "div-reg";
164 divider-offset = <0x238>;
165 divider-width = <0x9>;
166 divider-shift = <0x0>;
167 clock-output-names = "ethclk";
171 compatible = "apm,xgene-device-clock";
173 clocks = <ðclk 0>;
174 reg = <0x0 0x1702C000 0x0 0x1000>;
175 reg-names = "csr-reg";
176 clock-output-names = "menetclk";
179 xge0clk: xge0clk@1f61c000 {
180 compatible = "apm,xgene-device-clock";
182 clocks = <&socplldiv2 0>;
183 reg = <0x0 0x1f61c000 0x0 0x1000>;
184 reg-names = "csr-reg";
186 clock-output-names = "xge0clk";
189 sataphy1clk: sataphy1clk@1f21c000 {
190 compatible = "apm,xgene-device-clock";
192 clocks = <&socplldiv2 0>;
193 reg = <0x0 0x1f21c000 0x0 0x1000>;
194 reg-names = "csr-reg";
195 clock-output-names = "sataphy1clk";
199 enable-offset = <0x0>;
200 enable-mask = <0x06>;
203 sataphy2clk: sataphy1clk@1f22c000 {
204 compatible = "apm,xgene-device-clock";
206 clocks = <&socplldiv2 0>;
207 reg = <0x0 0x1f22c000 0x0 0x1000>;
208 reg-names = "csr-reg";
209 clock-output-names = "sataphy2clk";
213 enable-offset = <0x0>;
214 enable-mask = <0x06>;
217 sataphy3clk: sataphy1clk@1f23c000 {
218 compatible = "apm,xgene-device-clock";
220 clocks = <&socplldiv2 0>;
221 reg = <0x0 0x1f23c000 0x0 0x1000>;
222 reg-names = "csr-reg";
223 clock-output-names = "sataphy3clk";
227 enable-offset = <0x0>;
228 enable-mask = <0x06>;
231 sata01clk: sata01clk@1f21c000 {
232 compatible = "apm,xgene-device-clock";
234 clocks = <&socplldiv2 0>;
235 reg = <0x0 0x1f21c000 0x0 0x1000>;
236 reg-names = "csr-reg";
237 clock-output-names = "sata01clk";
240 enable-offset = <0x0>;
241 enable-mask = <0x39>;
244 sata23clk: sata23clk@1f22c000 {
245 compatible = "apm,xgene-device-clock";
247 clocks = <&socplldiv2 0>;
248 reg = <0x0 0x1f22c000 0x0 0x1000>;
249 reg-names = "csr-reg";
250 clock-output-names = "sata23clk";
253 enable-offset = <0x0>;
254 enable-mask = <0x39>;
257 sata45clk: sata45clk@1f23c000 {
258 compatible = "apm,xgene-device-clock";
260 clocks = <&socplldiv2 0>;
261 reg = <0x0 0x1f23c000 0x0 0x1000>;
262 reg-names = "csr-reg";
263 clock-output-names = "sata45clk";
266 enable-offset = <0x0>;
267 enable-mask = <0x39>;
270 rtcclk: rtcclk@17000000 {
271 compatible = "apm,xgene-device-clock";
273 clocks = <&socplldiv2 0>;
274 reg = <0x0 0x17000000 0x0 0x2000>;
275 reg-names = "csr-reg";
278 enable-offset = <0x10>;
280 clock-output-names = "rtcclk";
283 rngpkaclk: rngpkaclk@17000000 {
284 compatible = "apm,xgene-device-clock";
286 clocks = <&socplldiv2 0>;
287 reg = <0x0 0x17000000 0x0 0x2000>;
288 reg-names = "csr-reg";
291 enable-offset = <0x10>;
292 enable-mask = <0x10>;
293 clock-output-names = "rngpkaclk";
296 pcie0clk: pcie0clk@1f2bc000 {
298 compatible = "apm,xgene-device-clock";
300 clocks = <&socplldiv2 0>;
301 reg = <0x0 0x1f2bc000 0x0 0x1000>;
302 reg-names = "csr-reg";
303 clock-output-names = "pcie0clk";
306 pcie1clk: pcie1clk@1f2cc000 {
308 compatible = "apm,xgene-device-clock";
310 clocks = <&socplldiv2 0>;
311 reg = <0x0 0x1f2cc000 0x0 0x1000>;
312 reg-names = "csr-reg";
313 clock-output-names = "pcie1clk";
316 pcie2clk: pcie2clk@1f2dc000 {
318 compatible = "apm,xgene-device-clock";
320 clocks = <&socplldiv2 0>;
321 reg = <0x0 0x1f2dc000 0x0 0x1000>;
322 reg-names = "csr-reg";
323 clock-output-names = "pcie2clk";
326 pcie3clk: pcie3clk@1f50c000 {
328 compatible = "apm,xgene-device-clock";
330 clocks = <&socplldiv2 0>;
331 reg = <0x0 0x1f50c000 0x0 0x1000>;
332 reg-names = "csr-reg";
333 clock-output-names = "pcie3clk";
336 pcie4clk: pcie4clk@1f51c000 {
338 compatible = "apm,xgene-device-clock";
340 clocks = <&socplldiv2 0>;
341 reg = <0x0 0x1f51c000 0x0 0x1000>;
342 reg-names = "csr-reg";
343 clock-output-names = "pcie4clk";
347 pcie0: pcie@1f2b0000 {
350 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
351 #interrupt-cells = <1>;
353 #address-cells = <3>;
354 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
355 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
356 reg-names = "csr", "cfg";
357 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
358 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
359 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
360 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
361 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
362 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
363 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
364 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
365 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
367 clocks = <&pcie0clk 0>;
370 pcie1: pcie@1f2c0000 {
373 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
374 #interrupt-cells = <1>;
376 #address-cells = <3>;
377 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
378 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
379 reg-names = "csr", "cfg";
380 ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
381 0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
382 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
383 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
384 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
385 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
386 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
387 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
388 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
390 clocks = <&pcie1clk 0>;
393 pcie2: pcie@1f2d0000 {
396 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
397 #interrupt-cells = <1>;
399 #address-cells = <3>;
400 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
401 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
402 reg-names = "csr", "cfg";
403 ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */
404 0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
405 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
406 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
407 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
408 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
409 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
410 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
411 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
413 clocks = <&pcie2clk 0>;
416 pcie3: pcie@1f500000 {
419 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
420 #interrupt-cells = <1>;
422 #address-cells = <3>;
423 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
424 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
425 reg-names = "csr", "cfg";
426 ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */
427 0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */
428 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
429 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
430 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
431 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
432 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
433 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
434 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
436 clocks = <&pcie3clk 0>;
439 pcie4: pcie@1f510000 {
442 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
443 #interrupt-cells = <1>;
445 #address-cells = <3>;
446 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
447 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
448 reg-names = "csr", "cfg";
449 ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */
450 0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
451 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
452 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
453 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
454 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
455 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
456 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
457 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
459 clocks = <&pcie4clk 0>;
462 serial0: serial@1c020000 {
464 device_type = "serial";
465 compatible = "ns16550a";
466 reg = <0 0x1c020000 0x0 0x1000>;
468 clock-frequency = <10000000>; /* Updated by bootloader */
469 interrupt-parent = <&gic>;
470 interrupts = <0x0 0x4c 0x4>;
473 serial1: serial@1c021000 {
475 device_type = "serial";
476 compatible = "ns16550a";
477 reg = <0 0x1c021000 0x0 0x1000>;
479 clock-frequency = <10000000>; /* Updated by bootloader */
480 interrupt-parent = <&gic>;
481 interrupts = <0x0 0x4d 0x4>;
484 serial2: serial@1c022000 {
486 device_type = "serial";
487 compatible = "ns16550a";
488 reg = <0 0x1c022000 0x0 0x1000>;
490 clock-frequency = <10000000>; /* Updated by bootloader */
491 interrupt-parent = <&gic>;
492 interrupts = <0x0 0x4e 0x4>;
495 serial3: serial@1c023000 {
497 device_type = "serial";
498 compatible = "ns16550a";
499 reg = <0 0x1c023000 0x0 0x1000>;
501 clock-frequency = <10000000>; /* Updated by bootloader */
502 interrupt-parent = <&gic>;
503 interrupts = <0x0 0x4f 0x4>;
507 compatible = "apm,xgene-phy";
508 reg = <0x0 0x1f21a000 0x0 0x100>;
510 clocks = <&sataphy1clk 0>;
512 apm,tx-boost-gain = <30 30 30 30 30 30>;
513 apm,tx-eye-tuning = <2 10 10 2 10 10>;
517 compatible = "apm,xgene-phy";
518 reg = <0x0 0x1f22a000 0x0 0x100>;
520 clocks = <&sataphy2clk 0>;
522 apm,tx-boost-gain = <30 30 30 30 30 30>;
523 apm,tx-eye-tuning = <1 10 10 2 10 10>;
527 compatible = "apm,xgene-phy";
528 reg = <0x0 0x1f23a000 0x0 0x100>;
530 clocks = <&sataphy3clk 0>;
532 apm,tx-boost-gain = <31 31 31 31 31 31>;
533 apm,tx-eye-tuning = <2 10 10 2 10 10>;
536 sata1: sata@1a000000 {
537 compatible = "apm,xgene-ahci";
538 reg = <0x0 0x1a000000 0x0 0x1000>,
539 <0x0 0x1f210000 0x0 0x1000>,
540 <0x0 0x1f21d000 0x0 0x1000>,
541 <0x0 0x1f21e000 0x0 0x1000>,
542 <0x0 0x1f217000 0x0 0x1000>;
543 interrupts = <0x0 0x86 0x4>;
546 clocks = <&sata01clk 0>;
548 phy-names = "sata-phy";
551 sata2: sata@1a400000 {
552 compatible = "apm,xgene-ahci";
553 reg = <0x0 0x1a400000 0x0 0x1000>,
554 <0x0 0x1f220000 0x0 0x1000>,
555 <0x0 0x1f22d000 0x0 0x1000>,
556 <0x0 0x1f22e000 0x0 0x1000>,
557 <0x0 0x1f227000 0x0 0x1000>;
558 interrupts = <0x0 0x87 0x4>;
561 clocks = <&sata23clk 0>;
563 phy-names = "sata-phy";
566 sata3: sata@1a800000 {
567 compatible = "apm,xgene-ahci";
568 reg = <0x0 0x1a800000 0x0 0x1000>,
569 <0x0 0x1f230000 0x0 0x1000>,
570 <0x0 0x1f23d000 0x0 0x1000>,
571 <0x0 0x1f23e000 0x0 0x1000>;
572 interrupts = <0x0 0x88 0x4>;
575 clocks = <&sata45clk 0>;
577 phy-names = "sata-phy";
581 compatible = "apm,xgene-rtc";
582 reg = <0x0 0x10510000 0x0 0x400>;
583 interrupts = <0x0 0x46 0x4>;
585 clocks = <&rtcclk 0>;
588 menet: ethernet@17020000 {
589 compatible = "apm,xgene-enet";
591 reg = <0x0 0x17020000 0x0 0xd100>,
592 <0x0 0X17030000 0x0 0X400>,
593 <0x0 0X10000000 0x0 0X200>;
594 reg-names = "enet_csr", "ring_csr", "ring_cmd";
595 interrupts = <0x0 0x3c 0x4>;
597 clocks = <&menetclk 0>;
598 /* mac address will be overwritten by the bootloader */
599 local-mac-address = [00 00 00 00 00 00];
600 phy-connection-type = "rgmii";
601 phy-handle = <&menetphy>;
603 compatible = "apm,xgene-mdio";
604 #address-cells = <1>;
606 menetphy: menetphy@3 {
607 compatible = "ethernet-phy-id001c.c915";
614 xgenet: ethernet@1f610000 {
615 compatible = "apm,xgene-enet";
617 reg = <0x0 0x1f610000 0x0 0xd100>,
618 <0x0 0x1f600000 0x0 0X400>,
619 <0x0 0x18000000 0x0 0X200>;
620 reg-names = "enet_csr", "ring_csr", "ring_cmd";
621 interrupts = <0x0 0x60 0x4>;
623 clocks = <&xge0clk 0>;
624 /* mac address will be overwritten by the bootloader */
625 local-mac-address = [00 00 00 00 00 00];
626 phy-connection-type = "xgmii";
630 compatible = "apm,xgene-rng";
631 reg = <0x0 0x10520000 0x0 0x100>;
632 interrupts = <0x0 0x41 0x4>;
633 clocks = <&rngpkaclk 0>;