2 * ARM Juno Platform motherboard peripherals
4 * Copyright (c) 2013-2014 ARM Ltd
6 * This file is licensed under a dual GPLv2 or BSD license.
10 mb_clk24mhz: clk24mhz {
11 compatible = "fixed-clock";
13 clock-frequency = <24000000>;
14 clock-output-names = "juno_mb:clk24mhz";
17 mb_clk25mhz: clk25mhz {
18 compatible = "fixed-clock";
20 clock-frequency = <25000000>;
21 clock-output-names = "juno_mb:clk25mhz";
24 v2m_refclk1mhz: refclk1mhz {
25 compatible = "fixed-clock";
27 clock-frequency = <1000000>;
28 clock-output-names = "juno_mb:refclk1mhz";
31 v2m_refclk32khz: refclk32khz {
32 compatible = "fixed-clock";
34 clock-frequency = <32768>;
35 clock-output-names = "juno_mb:refclk32khz";
39 compatible = "arm,vexpress,v2p-p1", "simple-bus";
40 #address-cells = <2>; /* SMB chipselect number and offset */
42 #interrupt-cells = <1>;
46 arm,vexpress,site = <0>;
47 arm,v2m-memory-map = "rs1";
49 mb_fixed_3v3: fixedregulator@0 {
50 compatible = "regulator-fixed";
51 regulator-name = "MCC_SB_3V3";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
58 compatible = "gpio-keys";
63 debounce_interval = <50>;
67 gpios = <&iofpga_gpio0 0 0x4>;
70 debounce_interval = <50>;
74 gpios = <&iofpga_gpio0 1 0x4>;
77 debounce_interval = <50>;
81 gpios = <&iofpga_gpio0 2 0x4>;
84 debounce_interval = <50>;
88 gpios = <&iofpga_gpio0 3 0x4>;
91 debounce_interval = <50>;
95 gpios = <&iofpga_gpio0 4 0x4>;
98 debounce_interval = <50>;
102 gpios = <&iofpga_gpio0 5 0x4>;
106 ethernet@2,00000000 {
107 compatible = "smsc,lan9118", "smsc,lan9115";
108 reg = <2 0x00000000 0x10000>;
112 smsc,irq-active-high;
114 clocks = <&mb_clk25mhz>;
115 vdd33a-supply = <&mb_fixed_3v3>;
116 vddvario-supply = <&mb_fixed_3v3>;
120 compatible = "nxp,usb-isp1763";
121 reg = <5 0x00000000 0x20000>;
127 compatible = "arm,amba-bus", "simple-bus";
128 #address-cells = <1>;
130 ranges = <0 3 0 0x200000>;
132 v2m_sysctl: sysctl@020000 {
133 compatible = "arm,sp810", "arm,primecell";
134 reg = <0x020000 0x1000>;
135 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
136 clock-names = "refclk", "timclk", "apb_pclk";
138 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
139 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
140 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
144 compatible = "syscon", "simple-mfd";
145 reg = <0x010000 0x1000>;
148 compatible = "register-bit-led";
151 label = "vexpress:0";
152 linux,default-trigger = "heartbeat";
153 default-state = "on";
156 compatible = "register-bit-led";
159 label = "vexpress:1";
160 linux,default-trigger = "mmc0";
161 default-state = "off";
164 compatible = "register-bit-led";
167 label = "vexpress:2";
168 linux,default-trigger = "cpu0";
169 default-state = "off";
172 compatible = "register-bit-led";
175 label = "vexpress:3";
176 linux,default-trigger = "cpu1";
177 default-state = "off";
180 compatible = "register-bit-led";
183 label = "vexpress:4";
184 linux,default-trigger = "cpu2";
185 default-state = "off";
188 compatible = "register-bit-led";
191 label = "vexpress:5";
192 linux,default-trigger = "cpu3";
193 default-state = "off";
196 compatible = "register-bit-led";
199 label = "vexpress:6";
200 default-state = "off";
203 compatible = "register-bit-led";
206 label = "vexpress:7";
207 default-state = "off";
212 compatible = "arm,pl180", "arm,primecell";
213 reg = <0x050000 0x1000>;
215 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
216 wp-gpios = <&v2m_mmc_gpios 1 0>; */
217 max-frequency = <12000000>;
218 vmmc-supply = <&mb_fixed_3v3>;
219 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
220 clock-names = "mclk", "apb_pclk";
224 compatible = "arm,pl050", "arm,primecell";
225 reg = <0x060000 0x1000>;
227 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
228 clock-names = "KMIREFCLK", "apb_pclk";
232 compatible = "arm,pl050", "arm,primecell";
233 reg = <0x070000 0x1000>;
235 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
236 clock-names = "KMIREFCLK", "apb_pclk";
240 compatible = "arm,sp805", "arm,primecell";
241 reg = <0x0f0000 0x10000>;
243 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
244 clock-names = "wdogclk", "apb_pclk";
247 v2m_timer01: timer@110000 {
248 compatible = "arm,sp804", "arm,primecell";
249 reg = <0x110000 0x10000>;
251 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
252 clock-names = "timclken1", "timclken2", "apb_pclk";
255 v2m_timer23: timer@120000 {
256 compatible = "arm,sp804", "arm,primecell";
257 reg = <0x120000 0x10000>;
259 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
260 clock-names = "timclken1", "timclken2", "apb_pclk";
264 compatible = "arm,pl031", "arm,primecell";
265 reg = <0x170000 0x10000>;
267 clocks = <&soc_smc50mhz>;
268 clock-names = "apb_pclk";
271 iofpga_gpio0: gpio@1d0000 {
272 compatible = "arm,pl061", "arm,primecell";
273 reg = <0x1d0000 0x1000>;
275 clocks = <&soc_smc50mhz>;
276 clock-names = "apb_pclk";
279 interrupt-controller;
280 #interrupt-cells = <2>;