1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53", "arm,armv8";
44 enable-method = "psci";
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
54 compatible = "arm,cortex-a53", "arm,armv8";
56 enable-method = "psci";
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
66 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
72 compatible = "arm,cortex-a53", "arm,armv8";
74 enable-method = "psci";
78 compatible = "arm,cortex-a53", "arm,armv8";
80 enable-method = "psci";
84 compatible = "arm,cortex-a53", "arm,armv8";
86 enable-method = "psci";
122 compatible = "arm,psci";
124 cpu_on = <0xC4000003>;
127 gic: interrupt-controller@ffb70000 {
128 compatible = "arm,cortex-a15-gic";
129 #interrupt-cells = <3>;
130 #address-cells = <0>;
131 interrupt-controller;
132 reg = <0x0 0xffb71000 0 0x1000>,
133 <0x0 0xffb72000 0 0x1000>;
136 pmu: syscon@ff730000 {
137 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
138 reg = <0x0 0xff730000 0x0 0x1000>;
141 pmugrf: syscon@ff738000 {
142 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
143 reg = <0x0 0xff738000 0x0 0x1000>;
146 sgrf: syscon@ff740000 {
147 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
148 reg = <0x0 0xff740000 0x0 0x1000>;
152 cru: syscon@ff760000 {
153 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
154 reg = <0x0 0xff760000 0x0 0x1000>;
157 grf: syscon@ff770000 {
158 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
159 reg = <0x0 0xff770000 0x0 0x1000>;
163 compatible = "arm,armv8-pmuv3";
164 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
174 cpu_axi_bus: cpu_axi_bus {
175 compatible = "rockchip,cpu_axi_bus";
176 #address-cells = <2>;
181 #address-cells = <2>;
186 reg = <0x0 0xffa80000 0x0 0x20>;
189 reg = <0x0 0xffa80080 0x0 0x20>;
192 reg = <0x0 0xffa90000 0x0 0x20>;
195 reg = <0x0 0xffaa0000 0x0 0x20>;
198 reg = <0x0 0xffaa0080 0x0 0x20>;
201 reg = <0x0 0xffab0000 0x0 0x20>;
204 reg = <0x0 0xffad0000 0x0 0x20>;
207 reg = <0x0 0xffad0080 0x0 0x20>;
210 reg = <0x0 0xffad0100 0x0 0x20>;
213 reg = <0x0 0xffad0180 0x0 0x20>;
214 rockchip,priority = <2 2>;
217 reg = <0x0 0xffad0200 0x0 0x20>;
218 rockchip,priority = <2 2>;
221 reg = <0x0 0xffad0280 0x0 0x20>;
224 reg = <0x0 0xffad0300 0x0 0x20>;
225 rockchip,priority = <2 2>;
228 reg = <0x0 0xffad0380 0x0 0x20>;
231 reg = <0x0 0xffad0400 0x0 0x20>;
234 reg = <0x0 0xffae0000 0x0 0x20>;
237 reg = <0x0 0xffae0080 0x0 0x20>;
240 reg = <0x0 0xffae0100 0x0 0x20>;
245 #address-cells = <2>;
250 reg = <0x0 0xffac0000 0x0 0x3c>;
251 rockchip,read-latency = <0x34>;
257 compatible = "arm,armv8-timer";
258 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
259 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
260 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
261 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
262 clock-frequency = <24000000>;
266 compatible = "rockchip,timer";
267 reg = <0x0 0xff810000 0x0 0x20>;
268 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
269 rockchip,broadcast = <1>;
272 sram: sram@ff8c0000 {
273 compatible = "mmio-sram";
274 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
278 watchdog: wdt@ff800000 {
279 compatible = "rockchip,watch dog";
280 reg = <0x0 0xff800000 0x0 0x100>;
281 clocks = <&pclk_alive_pre>;
282 clock-names = "pclk_wdt";
283 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
285 rockchip,timeout = <60>;
286 rockchip,atboot = <1>;
287 rockchip,debug = <0>;
292 #address-cells = <2>;
294 compatible = "arm,amba-bus";
295 interrupt-parent = <&gic>;
298 pdma0: pdma@ff600000 {
299 compatible = "arm,pl330", "arm,primecell";
300 reg = <0x0 0xff600000 0x0 0x4000>;
301 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
306 pdma1: pdma@ff250000 {
307 compatible = "arm,pl330", "arm,primecell";
308 reg = <0x0 0xff250000 0x0 0x4000>;
309 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
315 reset: reset@ff760300{
316 compatible = "rockchip,reset";
317 reg = <0x0 0xff760300 0x0 0x38>;
318 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
322 nandc0: nandc@ff400000 {
323 compatible = "rockchip,rk-nandc";
324 reg = <0x0 0xff400000 0x0 0x4000>;
325 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
328 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
331 nandc0reg: nandc0@ff400000 {
332 compatible = "rockchip,rk-nandc";
333 reg = <0x0 0xff400000 0x0 0x4000>;
336 emmc: rksdmmc@ff0f0000 {
337 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
338 reg = <0x0 0xff0f0000 0x0 0x4000>;
339 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
342 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
343 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
344 rockchip,grf = <&grf>;
346 fifo-depth = <0x100>;
350 sdmmc: rksdmmc@ff0c0000 {
351 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
352 reg = <0x0 0xff0c0000 0x0 0x4000>;
353 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
356 pinctrl-names = "default", "idle";
357 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
358 pinctrl-1 = <&sdmmc_gpio>;
359 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
360 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
361 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
362 rockchip,grf = <&grf>;
364 fifo-depth = <0x100>;
368 sdio: rksdmmc@ff0d0000 {
369 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
370 reg = <0x0 0xff0d0000 0x0 0x4000>;
371 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
374 pinctrl-names = "default","idle";
375 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
376 pinctrl-1 = <&sdio0_gpio>;
377 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
378 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
379 rockchip,grf = <&grf>;
381 fifo-depth = <0x100>;
386 compatible = "rockchip,rockchip-spi";
387 reg = <0x0 0xff110000 0x0 0x1000>;
388 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
393 rockchip,spi-src-clk = <0>;
395 clocks =<&clk_spi0>, <&clk_gates19 4>;
396 clock-names = "spi", "pclk_spi0";
397 //dmas = <&pdma1 11>, <&pdma1 12>;
399 //dma-names = "tx", "rx";
404 compatible = "rockchip,rockchip-spi";
405 reg = <0x0 0xff120000 0x0 0x1000>;
406 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
411 rockchip,spi-src-clk = <1>;
413 clocks = <&clk_spi1>, <&clk_gates19 5>;
414 clock-names = "spi", "pclk_spi1";
415 //dmas = <&pdma1 13>, <&pdma1 14>;
417 //dma-names = "tx", "rx";
422 compatible = "rockchip,rockchip-spi";
423 reg = <0x0 0xff130000 0x0 0x1000>;
424 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
429 rockchip,spi-src-clk = <2>;
431 clocks = <&clk_spi2>, <&clk_gates19 6>;
432 clock-names = "spi", "pclk_spi2";
433 //dmas = <&pdma1 15>, <&pdma1 16>;
435 //dma-names = "tx", "rx";
439 uart_bt: serial@ff180000 {
440 compatible = "rockchip,serial";
441 reg = <0x0 0xff180000 0x0 0x100>;
442 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
443 clock-frequency = <24000000>;
444 clocks = <&clk_uart0>, <&clk_gates19 7>;
445 clock-names = "sclk_uart", "pclk_uart";
448 //dmas = <&pdma1 1>, <&pdma1 2>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
455 uart_bb: serial@ff190000 {
456 compatible = "rockchip,serial";
457 reg = <0x0 0xff190000 0x0 0x100>;
458 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
459 clock-frequency = <24000000>;
460 clocks = <&clk_uart1>, <&clk_gates19 8>;
461 clock-names = "sclk_uart", "pclk_uart";
464 //dmas = <&pdma1 3>, <&pdma1 4>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
471 uart_dbg: serial@ff690000 {
472 compatible = "rockchip,serial";
473 reg = <0x0 0xff690000 0x0 0x100>;
474 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
475 clock-frequency = <24000000>;
476 clocks = <&clk_uart2>, <&clk_gates13 5>;
477 clock-names = "sclk_uart", "pclk_uart";
480 //dmas = <&pdma0 4>, <&pdma0 5>;
482 //pinctrl-names = "default";
483 //pinctrl-0 = <&uart2_xfer>;
487 uart_gps: serial@ff1b0000 {
488 compatible = "rockchip,serial";
489 reg = <0x0 0xff1b0000 0x0 0x100>;
490 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
491 clock-frequency = <24000000>;
492 clocks = <&clk_uart3>, <&clk_gates19 9>;
493 clock-names = "sclk_uart", "pclk_uart";
494 current-speed = <115200>;
497 //dmas = <&pdma1 7>, <&pdma1 8>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
504 uart_exp: serial@ff1c0000 {
505 compatible = "rockchip,serial";
506 reg = <0x0 0xff1c0000 0x0 0x100>;
507 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
508 clock-frequency = <24000000>;
509 clocks = <&clk_uart4>, <&clk_gates19 10>;
510 clock-names = "sclk_uart", "pclk_uart";
513 //dmas = <&pdma1 9>, <&pdma1 10>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
520 rockchip_clocks_init: clocks-init{
521 compatible = "rockchip,clocks-init";
522 rockchip,clocks-init-parent =
523 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
524 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
525 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
526 <&clk_cs &clk_gpll>, <&clk_32k_mux &xin32k>;
527 rockchip,clocks-init-rate =
528 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
529 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
530 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
531 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
532 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
533 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
534 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
535 <&clk_cs 300000000>, <&clkin_trace 300000000>,
536 <&aclk_cci 600000000>, <&clk_mac 125000000>,
537 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
538 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
539 <&clk_isp 400000000>, <&clk_edp 200000000>,
540 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
541 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
542 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
543 <&clk_hevc_cabac 300000000>;
545 rockchip,clocks-uboot-has-init =
550 rockchip_clocks_enable: clocks-enable {
551 compatible = "rockchip,clocks-enable";
568 <&clk_gates12 12>,/*aclk_strc_sys*/
569 <&clk_gates12 6>,/*aclk_intmem1*/
570 <&clk_gates12 5>,/*aclk_intmem0*/
571 <&clk_gates12 4>,/*aclk_intmem*/
572 <&clk_gates13 9>,/*aclk_gic400*/
575 <&clk_gates22 13>,/*pclk_timer1*/
576 <&clk_gates22 12>,/*pclk_timer0*/
577 <&clk_gates22 9>,/*pclk_alive_niu*/
578 <&clk_gates22 8>,/*pclk_grf*/
581 <&clk_gates23 5>,/*pclk_pmugrf*/
582 <&clk_gates23 3>,/*pclk_sgrf*/
583 <&clk_gates23 2>,/*pclk_pmu_noc*/
584 <&clk_gates23 1>,/*pclk_intmem1*/
585 <&clk_gates23 0>,/*pclk_pmu*/
588 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
589 <&clk_gates20 8>,/*aclk_peri_niu*/
590 <&clk_gates21 4>,/*aclk_peri_mmu*/
591 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
592 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
593 <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
598 compatible = "rockchip,rk30-i2c";
599 reg = <0x0 0xff650000 0x0 0x1000>;
600 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
601 #address-cells = <1>;
603 pinctrl-names = "default", "gpio";
604 pinctrl-0 = <&i2c0_xfer>;
605 pinctrl-1 = <&i2c0_gpio>;
606 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
607 clocks = <&clk_gates12 2>;
608 rockchip,check-idle = <1>;
614 compatible = "rockchip,rk30-i2c";
615 reg = <0x0 0xff660000 0x0 0x1000>;
616 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
617 #address-cells = <1>;
619 pinctrl-names = "default", "gpio";
620 pinctrl-0 = <&i2c1_xfer>;
621 pinctrl-1 = <&i2c1_gpio>;
622 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
623 clocks = <&clk_gates12 3>;
624 rockchip,check-idle = <1>;
630 compatible = "rockchip,rk30-i2c";
631 reg = <0x0 0xff140000 0x0 0x1000>;
632 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
635 pinctrl-names = "default", "gpio";
636 pinctrl-0 = <&i2c2_xfer>;
637 pinctrl-1 = <&i2c2_gpio>;
638 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
639 clocks = <&clk_gates19 11>;
640 rockchip,check-idle = <1>;
646 compatible = "rockchip,rk30-i2c";
647 reg = <0x0 0xff150000 0x0 0x1000>;
648 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
649 #address-cells = <1>;
651 pinctrl-names = "default", "gpio";
652 pinctrl-0 = <&i2c3_xfer>;
653 pinctrl-1 = <&i2c3_gpio>;
654 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
655 clocks = <&clk_gates19 12>;
656 rockchip,check-idle = <1>;
662 compatible = "rockchip,rk30-i2c";
663 reg = <0x0 0xff160000 0x0 0x1000>;
664 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
665 #address-cells = <1>;
667 pinctrl-names = "default", "gpio";
668 pinctrl-0 = <&i2c4_xfer>;
669 pinctrl-1 = <&i2c4_gpio>;
670 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
671 clocks = <&clk_gates19 13>;
672 rockchip,check-idle = <1>;
678 compatible = "rockchip,rk30-i2c";
679 reg = <0x0 0xff170000 0x0 0x1000>;
680 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
681 #address-cells = <1>;
683 pinctrl-names = "default", "gpio";
684 pinctrl-0 = <&i2c5_xfer>;
685 pinctrl-1 = <&i2c5_gpio>;
686 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
687 clocks = <&clk_gates19 14>;
688 rockchip,check-idle = <1>;
693 compatible = "rockchip,rk-fb";
694 rockchip,disp-mode = <NO_DUAL>;
698 rk_screen: rk_screen {
699 compatible = "rockchip,screen";
702 dsihost0: mipi@ff960000{
703 compatible = "rockchip,rk3368-dsi";
705 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
706 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
707 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
709 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
713 lvds: lvds@ff968000 {
714 compatible = "rockchip,rk3368-lvds";
715 rockchip,grf = <&grf>;
716 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
717 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
718 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
719 clock-names = "pclk_lvds", "pclk_lvds_ctl";
724 compatible = "rockchip,rk32-edp";
725 reg = <0x0 0xff970000 0x0 0x4000>;
726 rockchip,grf = <&grf>;
727 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
729 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
730 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
731 reset-names = "edp_24m", "edp_apb";
734 hdmi: hdmi@ff980000 {
735 compatible = "rockchip,rk3368-hdmi";
736 reg = <0x0 0xff980000 0x0 0x20000>;
737 rockchip,grf = <&grf>;
738 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
739 pinctrl-names = "default", "gpio";
740 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
741 pinctrl-1 = <&i2c5_gpio>;
742 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
743 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
747 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
748 compatible = "rockchip,rk3368-hdmi-hdcp2";
749 reg = <0x0 0xff978000 0x0 0x2000>;
750 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
752 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
756 lcdc: lcdc@ff930000 {
757 compatible = "rockchip,rk3368-lcdc";
758 rockchip,grf = <&grf>;
759 rockchip,pmugrf = <&pmugrf>;
760 rockchip,prop = <PRMRY>;
761 rockchip,pwr18 = <0>;
762 rockchip,iommu-enabled = <0>;
763 reg = <0x0 0xff930000 0x0 0x10000>;
764 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
765 /*pinctrl-names = "default", "gpio";
766 *pinctrl-0 = <&lcdc_lcdc>;
767 *pinctrl-1 = <&lcdc_gpio>;
770 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
771 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
775 compatible = "rockchip,saradc";
776 reg = <0x0 0xff100000 0x0 0x100>;
777 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
778 #io-channel-cells = <1>;
780 rockchip,adc-vref = <1800>;
781 clock-frequency = <1000000>;
782 clocks = <&clk_saradc>, <&clk_gates19 15>;
783 clock-names = "saradc", "pclk_saradc";
788 compatible = "rockchip,rk3368-rga2";
789 reg = <0x0 0xff920000 0x0 0x1000>;
790 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
792 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
795 i2s0: i2s0@ff898000 {
796 compatible = "rockchip-i2s";
797 reg = <0x0 0xff898000 0x0 0x1000>;
799 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
800 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
801 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
802 dmas = <&pdma0 0>, <&pdma0 1>;
804 dma-names = "tx", "rx";
805 pinctrl-names = "default", "sleep";
806 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
807 pinctrl-1 = <&i2s_gpio>;
810 i2s1: i2s1@ff890000 {
811 compatible = "rockchip-i2s";
812 reg = <0x0 0xff890000 0x0 0x1000>;
814 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
815 clock-names = "i2s_clk", "i2s_hclk";
816 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
817 dmas = <&pdma0 6>, <&pdma0 7>;
819 dma-names = "tx", "rx";
822 spdif: spdif@ff880000 {
823 compatible = "rockchip-spdif";
824 reg = <0x0 0xff880000 0x0 0x1000>;
825 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
826 clock-names = "spdif_mclk", "spdif_hclk";
827 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
831 pinctrl-names = "default";
832 pinctrl-0 = <&spdif_tx>;
836 compatible = "rockchip,rk-pwm";
837 reg = <0x0 0xff680000 0x0 0x10>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&pwm0_pin>;
841 clocks = <&clk_gates13 6>;
842 clock-names = "pclk_pwm";
847 compatible = "rockchip,rk-pwm";
848 reg = <0x0 0xff680010 0x0 0x10>;
850 pinctrl-names = "default";
851 pinctrl-0 = <&pwm1_pin>;
852 clocks = <&clk_gates13 6>;
853 clock-names = "pclk_pwm";
858 compatible = "rockchip,rk-pwm";
859 reg = <0x0 0xff680020 0x0 0x10>;
861 //pinctrl-names = "default";
862 //pinctrl-0 = <&pwm1_pin>;
863 clocks = <&clk_gates13 6>;
864 clock-names = "pclk_pwm";
869 compatible = "rockchip,rk-pwm";
870 reg = <0x0 0xff680030 0x0 0x10>;
872 pinctrl-names = "default";
873 pinctrl-0 = <&pwm3_pin>;
874 clocks = <&clk_gates13 6>;
875 clock-names = "pclk_pwm";
879 remotectl: pwm@ff680030 {
880 compatible = "rockchip,remotectl-pwm";
881 reg = <0x0 0xff680030 0x0 0x50>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&pwm3_pin>;
885 clocks = <&clk_gates13 6>;
886 clock-names = "pclk_pwm";
891 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
895 voppwm: pwm@ff9301a0 {
896 compatible = "rockchip,vop-pwm";
897 reg = <0x0 0xff9301a0 0x0 0x10>;
899 pinctrl-names = "default";
900 pinctrl-0 = <&vop_pwm_pin>;
901 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
902 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
907 compatible = "rockchip,rk3368-pvtm";
908 rockchip,grf = <&grf>;
909 rockchip,pmugrf = <&pmugrf>;
910 rockchip,pvtm-clk-out = <0>;
914 compatible = "rockchip,rk3368-cpufreq";
915 rockchip,grf = <&grf>;
921 regulator_name = "vdd_arm";
922 suspend_volt = <1000>; //mV
924 clk_core_b_dvfs_table: clk_core_b {
934 clk_core_l_dvfs_table: clk_core_l {
948 regulator_name = "vdd_logic";
949 suspend_volt = <1000>; //mV
951 clk_ddr_dvfs_table: clk_ddr {
964 clk_gpu_dvfs_table: clk_gpu {
985 compatible = "rockchip,ion";
986 #address-cells = <1>;
989 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
990 compatible = "rockchip,ion-heap";
991 rockchip,ion_heap = <4>;
992 reg = <0x00000000 0x08000000>; /* 512MB */
994 rockchip,ion-heap@0 { /* VMALLOC HEAP */
995 compatible = "rockchip,ion-heap";
996 rockchip,ion_heap = <0>;
1001 compatible = "rockchip,vpu_sub";
1002 iommu_enabled = <0>;
1003 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1005 interrupt-names = "irq_enc", "irq_dec";
1007 name = "vpu_service";
1010 hevc: hevc_service {
1011 compatible = "rockchip,hevc_sub";
1012 iommu_enabled = <0>;
1013 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1014 interrupt-names = "irq_dec";
1016 name = "hevc_service";
1019 vpu_combo: vpu_combo@ff9a0000 {
1020 compatible = "rockchip,vpu_combo";
1021 reg = <0x0 0xff9a0000 0x0 0x800>;
1022 rockchip,grf = <&grf>;
1024 rockchip,sub = <&vpu>, <&hevc>;
1025 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1026 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1028 mode_ctrl = <0x418>;
1034 compatible = "rockchip,iep";
1035 iommu_enabled = <0>;
1036 reg = <0x0 0xff900000 0x0 0x800>;
1037 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1039 clock-names = "aclk_iep", "hclk_iep";
1043 gmac: eth@ff290000 {
1044 compatible = "rockchip,rk3368-gmac";
1045 reg = <0x0 0xff290000 0x0 0x10000>;
1046 rockchip,grf = <&grf>;
1047 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1048 interrupt-names = "macirq";
1050 clocks = <&clk_mac>, <&clk_gates7 4>,
1051 <&clk_gates7 5>, <&clk_gates7 6>,
1052 <&clk_gates7 7>, <&clk_gates20 13>,
1054 clock-names = "clk_mac", "mac_clk_rx",
1055 "mac_clk_tx", "clk_mac_ref",
1056 "clk_mac_refout", "aclk_mac",
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&rgmii_pins>;
1065 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1066 reg = <0x0 0xffa30000 0x0 0x10000>;
1067 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1068 interrupt-names = "GPU";
1073 compatible = "rockchip,iep_mmu";
1074 reg = <0x0 0xff900800 0x0 0x100>;
1075 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1076 interrupt-names = "iep_mmu";
1081 compatible = "rockchip,vip_mmu";
1082 reg = <0x0 0xff950800 0x0 0x100>;
1083 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1084 interrupt-names = "vip_mmu";
1089 compatible = "rockchip,vop_mmu";
1090 reg = <0x0 0xff930300 0x0 0x100>;
1091 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupt-names = "vop_mmu";
1096 dbgname = "isp_mmu";
1097 compatible = "rockchip,isp_mmu";
1098 reg = <0x0 0xff914000 0x0 0x100>,
1099 <0x0 0xff915000 0x0 0x100>;
1100 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1101 interrupt-names = "isp_mmu";
1105 dbgname = "hdcp_mmu";
1106 compatible = "rockchip,hdcp_mmu";
1107 reg = <0x0 0xff940000 0x0 0x100>;
1108 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1109 interrupt-names = "hdcp_mmu";
1114 compatible = "rockchip,hevc_mmu";
1115 reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
1116 <0x0 0xff9c0480 0x0 0x40>;
1117 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1118 interrupt-names = "hevc_mmu";
1123 compatible = "rockchip,vpu_mmu";
1124 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1125 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1126 interrupt-names = "vpu_mmu";
1130 rockchip,ctrbits = <
1137 |RKPM_CTR_SYSCLK_DIV
1138 |RKPM_CTR_IDLEAUTO_MD
1139 |RKPM_CTR_ARMOFF_LPMD
1141 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1144 rockchip,pmic-suspend_gpios = <
1145 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1147 rockchip,pmic-resume_gpios = <
1148 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1153 compatible = "rockchip,isp";
1154 reg = <0x0 0xff910000 0x0 0x10000>;
1155 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1157 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1158 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1159 pinctrl-0 = <&cif_clkout>;
1160 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1161 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1162 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1163 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1164 pinctrl-5 = <&cif_clkout>;
1165 pinctrl-6 = <&cif_clkout &isp_prelight>;
1166 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1167 pinctrl-8 = <&isp_flash_trigger>;
1168 rockchip,isp,mipiphy = <2>;
1169 rockchip,isp,cifphy = <1>;
1170 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1171 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1172 rockchip,grf = <&grf>;
1173 rockchip,cru = <&cru>;
1174 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1175 rockchip,isp,iommu_enable = <0>;
1180 compatible = "rockchip,cif";
1181 reg = <0x0 0xff950000 0x0 0x10000>;
1182 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1183 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1184 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1185 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1186 pinctrl-names = "cif_pin_all";
1187 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1188 rockchip,grf = <&grf>;
1189 rockchip,cru = <&cru>;
1194 #include "rk3368-thermal.dtsi"
1197 tsadc: tsadc@ff280000 {
1198 compatible = "rockchip,rk3368-tsadc";
1199 reg = <0x0 0xff280000 0x0 0x100>;
1200 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1202 clock-names = "tsadc", "apb_pclk";
1203 resets = <&reset RK3368_SRST_TSADC_P>;
1204 reset-names = "tsadc-apb";
1205 pinctrl-names = "default";
1206 pinctrl-0 = <&tsadc_int>;
1207 #thermal-sensor-cells = <1>;
1208 hw-shut-temp = <120000>;
1209 status = "disabled";
1213 compatible = "rockchip,rk3368-tsp";
1214 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1215 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1216 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1217 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1218 interrupt-names = "irq_tsp";
1219 // pinctrl-names = "default";
1220 // pinctrl-0 = <&isp_hsadc>;
1224 crypto: crypto@FF8A0000{
1225 compatible = "rockchip,rk3368-crypto";
1226 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1227 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1228 interrupt-names = "irq_crypto";
1229 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1230 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1234 dwc_control_usb: dwc-control-usb {
1235 compatible = "rockchip,rk3368-dwc-control-usb";
1236 rockchip,grf = <&grf>;
1237 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1239 interrupt-names = "otg_id", "otg_bvalid",
1240 "otg_linestate", "host0_linestate";
1241 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1242 clock-names = "hclk_usb_peri", "usbphy_480m";
1243 //resets = <&reset RK3128_RST_USBPOR>;
1244 //reset-names = "usbphy_por";
1246 compatible = "inno,phy";
1247 regbase = &dwc_control_usb;
1248 rk_usb,bvalid = <0x4bc 23 1>;
1249 rk_usb,iddig = <0x4bc 26 1>;
1250 rk_usb,vdmsrcen = <0x718 12 1>;
1251 rk_usb,vdpsrcen = <0x718 11 1>;
1252 rk_usb,rdmpden = <0x718 10 1>;
1253 rk_usb,idpsrcen = <0x718 9 1>;
1254 rk_usb,idmsinken = <0x718 8 1>;
1255 rk_usb,idpsinken = <0x718 7 1>;
1256 rk_usb,dpattach = <0x4b8 31 1>;
1257 rk_usb,cpdet = <0x4b8 30 1>;
1258 rk_usb,dcpattach = <0x4b8 29 1>;
1262 usb0: usb@ff580000 {
1263 compatible = "rockchip,rk3368_usb20_otg";
1264 reg = <0x0 0xff580000 0x0 0x40000>;
1265 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1267 clock-names = "clk_usbphy0", "hclk_otg";
1268 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1269 <&reset RK3368_SRST_USBOTGC0>;
1270 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1271 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1272 rockchip,usb-mode = <0>;
1275 usb_ehci: usb@ff500000 {
1276 compatible = "generic-ehci";
1277 reg = <0x0 0xff500000 0x0 0x20000>;
1278 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1280 clock-names = "clk_usbphy0", "hclk_ehci";
1281 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1282 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1283 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1286 usb_ohci: usb@ff520000 {
1287 compatible = "generic-ohci";
1288 reg = <0x0 0xff520000 0x0 0x20000>;
1289 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1290 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1291 clock-names = "clk_usbphy0", "hclk_ohci";
1294 usb_hsic: usb@ff5c0000 {
1295 compatible = "rockchip,rk3288_rk_hsic_host";
1296 reg = <0x0 0xff5c0000 0x0 0x40000>;
1297 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1300 <&hsicphy_12m>, <&usbphy_480m>,
1301 <&otgphy1_480m>, <&otgphy2_480m>;
1302 clock-names = "hsicphy_480m", "hclk_hsic",
1303 "hsicphy_12m", "usbphy_480m",
1304 "hsic_usbphy1", "hsic_usbphy2";
1305 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1306 <&reset RK3288_SOFT_RST_HSICPHY>;
1307 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1309 status = "disabled";
1313 compatible = "rockchip,rk3368-pinctrl";
1314 rockchip,grf = <&grf>;
1315 rockchip,pmugrf = <&pmugrf>;
1316 #address-cells = <2>;
1320 gpio0: gpio0@ff750000 {
1321 compatible = "rockchip,gpio-bank";
1322 reg = <0x0 0xff750000 0x0 0x100>;
1323 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1324 clocks = <&clk_gates23 4>;
1329 interrupt-controller;
1330 #interrupt-cells = <2>;
1333 gpio1: gpio1@ff780000 {
1334 compatible = "rockchip,gpio-bank";
1335 reg = <0x0 0xff780000 0x0 0x100>;
1336 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&clk_gates22 1>;
1342 interrupt-controller;
1343 #interrupt-cells = <2>;
1346 gpio2: gpio2@ff790000 {
1347 compatible = "rockchip,gpio-bank";
1348 reg = <0x0 0xff790000 0x0 0x100>;
1349 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1350 clocks = <&clk_gates22 2>;
1355 interrupt-controller;
1356 #interrupt-cells = <2>;
1359 gpio3: gpio3@ff7a0000 {
1360 compatible = "rockchip,gpio-bank";
1361 reg = <0x0 0xff7a0000 0x0 0x100>;
1362 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1363 clocks = <&clk_gates22 3>;
1368 interrupt-controller;
1369 #interrupt-cells = <2>;
1372 pcfg_pull_up: pcfg-pull-up {
1376 pcfg_pull_down: pcfg-pull-down {
1380 pcfg_pull_none: pcfg-pull-none {
1384 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1385 drive-strength = <8>;
1388 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1389 drive-strength = <12>;
1392 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1394 drive-strength = <8>;
1397 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1398 drive-strength = <4>;
1401 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1403 drive-strength = <4>;
1406 pcfg_output_high: pcfg-output-high {
1410 pcfg_output_low: pcfg-output-low {
1415 i2c0_xfer: i2c0-xfer {
1416 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1417 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1419 i2c0_gpio: i2c0-gpio {
1420 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1421 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1426 i2c1_xfer: i2c1-xfer {
1427 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1428 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1430 i2c1_gpio: i2c1-gpio {
1431 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1432 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1437 i2c2_xfer: i2c2-xfer {
1438 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1439 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1441 i2c2_gpio: i2c2-gpio {
1442 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1443 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1448 i2c3_xfer: i2c3-xfer {
1449 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1450 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1452 i2c3_gpio: i2c3-gpio {
1453 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1454 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1459 i2c4_xfer: i2c4-xfer {
1460 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1461 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1463 i2c4_gpio: i2c4-gpio {
1464 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1465 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1470 i2c5_xfer: i2c5-xfer {
1471 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1472 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1474 i2c5_gpio: i2c5-gpio {
1475 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1476 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1481 uart0_xfer: uart0-xfer {
1482 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1483 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1486 uart0_cts: uart0-cts {
1487 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1490 uart0_rts: uart0-rts {
1491 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1494 uart0_rts_gpio: uart0-rts-gpio {
1495 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1500 uart1_xfer: uart1-xfer {
1501 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1502 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1505 uart1_cts: uart1-cts {
1506 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1509 uart1_rts: uart1-rts {
1510 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1515 uart2_xfer: uart2-xfer {
1516 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1517 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1522 uart3_xfer: uart3-xfer {
1523 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1524 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1527 uart3_cts: uart3-cts {
1528 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1531 uart3_rts: uart3-rts {
1532 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1537 uart4_xfer: uart4-xfer {
1538 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1539 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1542 uart4_cts: uart4-cts {
1543 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1546 uart4_rts: uart4-rts {
1547 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1552 spi0_clk: spi0-clk {
1553 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1555 spi0_cs0: spi0-cs0 {
1556 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1559 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1562 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1564 spi0_cs1: spi0-cs1 {
1565 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1570 spi1_clk: spi1-clk {
1571 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1573 spi1_cs0: spi1-cs0 {
1574 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1577 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1580 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1585 spi2_clk: spi2-clk {
1586 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1588 spi2_cs0: spi2-cs0 {
1589 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1592 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1595 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1600 i2s_mclk: i2s-mclk {
1601 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1605 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1608 i2s_lrckrx:i2s-lrckrx {
1609 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1612 i2s_lrcktx:i2s-lrcktx {
1613 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1617 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1621 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1625 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1629 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1633 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1636 i2s_gpio: i2s-gpio {
1637 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1638 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1639 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1640 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1641 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1642 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1643 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1644 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1645 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1650 spdif_tx: spdif-tx {
1651 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1656 sdmmc_clk: sdmmc-clk {
1657 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1660 sdmmc_cmd: sdmmc-cmd {
1661 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1664 sdmmc_dectn: sdmmc-dectn {
1665 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1668 sdmmc_bus1: sdmmc-bus1 {
1669 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1672 sdmmc_bus4: sdmmc-bus4 {
1673 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1674 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1675 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1676 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1679 sdmmc_gpio: sdmmc-gpio {
1680 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1681 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1682 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1683 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1684 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1685 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1686 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1691 sdio0_bus1: sdio0-bus1 {
1692 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1695 sdio0_bus4: sdio0-bus4 {
1696 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1697 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1698 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1699 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1702 sdio0_cmd: sdio0-cmd {
1703 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1706 sdio0_clk: sdio0-clk {
1707 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1710 sdio0_dectn: sdio0-dectn {
1711 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1714 sdio0_wrprt: sdio0-wrprt {
1715 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1718 sdio0_pwren: sdio0-pwren {
1719 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1722 sdio0_bkpwr: sdio0-bkpwr {
1723 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1726 sdio0_int: sdio0-int {
1727 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1730 sdio0_gpio: sdio0-gpio {
1731 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1732 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1733 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1734 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1735 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1736 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1737 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1738 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1739 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1740 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1741 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1746 emmc_clk: emmc-clk {
1747 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1750 emmc_cmd: emmc-cmd {
1751 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1754 emmc_pwren: emmc-pwren {
1755 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1758 emmc_rstnout: emmc_rstnout {
1759 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1762 emmc_bus1: emmc-bus1 {
1763 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1766 emmc_bus4: emmc-bus4 {
1767 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1768 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1769 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1770 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1775 pwm0_pin: pwm0-pin {
1776 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1779 vop_pwm_pin:vop-pwm {
1780 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1785 pwm1_pin: pwm1-pin {
1786 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1791 pwm3_pin: pwm3-pin {
1792 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1797 lcdc_lcdc: lcdc-lcdc {
1799 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1800 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1801 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1802 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1803 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1804 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1805 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1806 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1807 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1808 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1809 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1810 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1811 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1812 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1813 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1814 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1815 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1816 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1819 lcdc_gpio: lcdc-gpio {
1821 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1822 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1823 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1824 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1825 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1826 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1827 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1828 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1829 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1830 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1831 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1832 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1833 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1834 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1835 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1836 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1837 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1838 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1843 cif_clkout: cif-clkout {
1844 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1847 isp_dvp_d2d9: isp-dvp-d2d9 {
1848 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1849 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1850 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1851 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1852 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1853 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1854 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1855 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1856 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1857 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1858 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1859 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1862 isp_dvp_d0d1: isp-dvp-d0d1 {
1863 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1864 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1867 isp_dvp_d10d11:isp_d10d11 {
1868 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1869 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1872 isp_dvp_d0d7: isp-dvp-d0d7 {
1873 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1874 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1875 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1876 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1877 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1878 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1879 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1880 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1883 isp_shutter: isp-shutter {
1884 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1885 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1888 isp_flash_trigger: isp-flash-trigger {
1889 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1892 isp_prelight: isp-prelight {
1893 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1896 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1897 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1903 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1907 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1911 gps_rfclk: gps-rfclk {
1912 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1917 rgmii_pins: rgmii-pins {
1918 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1919 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1920 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1921 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1922 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1923 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1924 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1925 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1926 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1927 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1928 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1929 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1930 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1931 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1932 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1935 rmii_pins: rmii-pins {
1936 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1937 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1938 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1939 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1940 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1941 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1942 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1943 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1944 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1945 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1950 tsadc_int: tsadc-int {
1951 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1953 tsadc_gpio: tsadc-gpio {
1954 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1959 hdmi_cec: hdmi-cec {
1960 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1965 hdmii2c_xfer: hdmii2c-xfer {
1966 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1967 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1973 compatible = "rockchip,rk3368-reboot";
1974 rockchip,cru = <&cru>;
1975 rockchip,pmugrf = <&pmugrf>;